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[209.132.180.67]) by mx.google.com with ESMTP id z66si8004455pff.284.2017.08.21.16.52.28; Mon, 21 Aug 2017 16:52:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jxrZiFDX; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754388AbdHUXw0 (ORCPT + 3 others); Mon, 21 Aug 2017 19:52:26 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45958 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754190AbdHUXwY (ORCPT ); Mon, 21 Aug 2017 19:52:24 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNq0cB028513; Mon, 21 Aug 2017 18:52:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359520; bh=MTiWrxiHOwmVHVzcdr4EvkdY5Euiad9jzg/hoPsFMVI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jxrZiFDXVRl1r/s3OdV3pRDpXab1wjcv7UBfQ3qgyPTL4Kwg9W5baGyS7Ap+RtOis Rxj1nWUwHh+yTfBG1G7MxjK5HEGTaWx0CTlxxE4ljKkwjsyWIjQQNlmk4gGfUjMJXe D7go+mGqXOHSKLxCW6ys2a7DGg014OUDPXzqvaFc= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNq0xg006536; Mon, 21 Aug 2017 18:52:00 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:51:59 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:51:59 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNpxo4001430; Mon, 21 Aug 2017 18:51:59 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNpx307291; Mon, 21 Aug 2017 18:51:59 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 2/5] ARM: dts: dra72-evm-common: Enable relevant IPU and DSP MMU nodes Date: Mon, 21 Aug 2017 18:51:55 -0500 Message-ID: <20170821235158.4968-3-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821235158.4968-1-s-anna@ti.com> References: <20170821235158.4968-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The MMU nodes for the remote processors IPU1, IPU2 and DSP1 have all been enabled. All these nodes are relevant and valid for both the DRA72x EVM variants and the DRA71 EVM, so are added in the common dts file. DSP2 MMU nodes are not present on DRA72x/DRA71x SoCs. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra72-evm-common.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 2e485a13dfd7..a72bcfd032d3 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -564,6 +564,22 @@ }; }; +&mmu0_dsp1 { + status = "okay"; +}; + +&mmu1_dsp1 { + status = "okay"; +}; + +&mmu_ipu1 { + status = "okay"; +}; + +&mmu_ipu2 { + status = "okay"; +}; + &pcie1_rc { status = "okay"; };