From patchwork Thu Feb 20 17:07:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 204537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1297C11D0C for ; Thu, 20 Feb 2020 17:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 71566206F4 for ; Thu, 20 Feb 2020 17:08:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Mjm+BuSi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728611AbgBTRHo (ORCPT ); Thu, 20 Feb 2020 12:07:44 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:44588 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728173AbgBTRHn (ORCPT ); Thu, 20 Feb 2020 12:07:43 -0500 Received: by mail-wr1-f65.google.com with SMTP id m16so5445964wrx.11; Thu, 20 Feb 2020 09:07:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Di1qslRPbTpLpq+RzibDLTYgsINPkOU2t7v0O3JomH8=; b=Mjm+BuSiQBS2VswHPp0u1QKG8m12DE0h5dALWHDoWm3i6hxbi7FK+5dEyOHjsBvq8m NFraNVDul4Vj2KO9oauH95aVg3YjeLEYffKUgVmNB1cgLQdD4aWMa8aV+p0M2FK95qZV ZfVQuyGQkNyrdhcJTfjf7gmANVbOB8BrQvEeZmP56vsqePorLEG2L4fIuRTGJodS7jKv TUy/KLdQ014cYXprEnG9F7/v/7XqcowT4JHev/9psrRed57VcbnxyZIIjntmNAI1HY6q l18JsmpnISHP4ylzzNdZ7yEuyeCT/+01TvXrvYUnphmxxFXTQXJEWHFbXvK6paxWiVuh 0zeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Di1qslRPbTpLpq+RzibDLTYgsINPkOU2t7v0O3JomH8=; b=TbrMZ4/PDhYOrsMUQHjmDgM0cC0jIyP0gHZ/RhV6reVyfvjmBc+S3Fe3pnEMZET8nm nW9XEwjpPtT8DeNgRIRlbgn2Cm23BdR8oA0Acr59cVR1k9ajazIkNGLSWZxtPOOHgDhI 3KVZKxUt4DH1gksQfoRryU82BNjWG/H0twXArv0PIZ6KQ3ZrNW+Q16giifnImyR6AKSo BMal0sZYSHMU/KcvJ1o9J7Z5f/susDqqg8afqIlCnPDeFvJJMnjq1YbmZabbGt8UQDw9 UWZxlM1/CZGeUgji5wDFuSI2V66b+AlL8ZuJeqJHzPeemHcHvSUNuFJFoxoYW18693HY +Hbw== X-Gm-Message-State: APjAAAXtBwk8SQ0e1kzWIuSRLjaIvUuNclIaJ7SAIfbcVSq5oDKSvPgY YxGuE7q2Ax/Ou4jUm9bsznz6iAOGu+8= X-Google-Smtp-Source: APXvYqxAOSbO3AykzBqmnNNS/TXxyh2rND4jYMPHgD3rmbzyWSIjdEhy0dh5d3iIqUYb2m+x5g5NTQ== X-Received: by 2002:a5d:4651:: with SMTP id j17mr44011351wrs.237.1582218461138; Thu, 20 Feb 2020 09:07:41 -0800 (PST) Received: from Ansuel-XPS.localdomain (93-39-149-95.ip76.fastwebnet.it. [93.39.149.95]) by smtp.googlemail.com with ESMTPSA id o77sm5817883wme.34.2020.02.20.09.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2020 09:07:40 -0800 (PST) From: Ansuel Smith Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , "David S. Miller" , Rob Herring , Mark Rutland , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] net: mdio: add ipq8064 mdio driver Date: Thu, 20 Feb 2020 18:07:28 +0100 Message-Id: <20200220170732.12741-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently ipq806x soc use generi bitbang driver to comunicate with the gmac ethernet interface. Add a dedicated driver created by chunkeey to fix this. Christian Lamparter Signed-off-by: Ansuel Smith --- drivers/net/phy/Kconfig | 8 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/net/phy/mdio-ipq8064.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 9dabe03a668c..ec2a5493a7e8 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -157,6 +157,14 @@ config MDIO_I2C This is library mode. +config MDIO_IPQ8064 + tristate "Qualcomm IPQ8064 MDIO interface support" + depends on HAS_IOMEM && OF_MDIO + depends on MFD_SYSCON + help + This driver supports the MDIO interface found in the network + interface units of the IPQ8064 SoC + config MDIO_MOXART tristate "MOXA ART MDIO interface support" depends on ARCH_MOXART || COMPILE_TEST diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fe5badf13b65..8f02bd2089f3 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o +obj-$(CONFIG_MDIO_IPQ8064) += mdio-ipq8064.o obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o diff --git a/drivers/net/phy/mdio-ipq8064.c b/drivers/net/phy/mdio-ipq8064.c new file mode 100644 index 000000000000..e974a6f5d5ef --- /dev/null +++ b/drivers/net/phy/mdio-ipq8064.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Qualcomm IPQ8064 MDIO interface driver +// +// Copyright (C) 2019 Christian Lamparter + +#include +#include +#include +#include +#include +#include +#include +#include + +/* MII address register definitions */ +#define MII_ADDR_REG_ADDR 0x10 +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) +#define MII_CLKRANGE_60_100M (0 << 2) +#define MII_CLKRANGE_100_150M (1 << 2) +#define MII_CLKRANGE_20_35M (2 << 2) +#define MII_CLKRANGE_35_60M (3 << 2) +#define MII_CLKRANGE_150_250M (4 << 2) +#define MII_CLKRANGE_250_300M (5 << 2) +#define MII_CLKRANGE_MASK GENMASK(4, 2) +#define MII_REG_SHIFT 6 +#define MII_REG_MASK GENMASK(10, 6) +#define MII_ADDR_SHIFT 11 +#define MII_ADDR_MASK GENMASK(15, 11) + +#define MII_DATA_REG_ADDR 0x14 + +#define MII_MDIO_DELAY (1000) +#define MII_MDIO_RETRY (10) + +struct ipq8064_mdio { + struct regmap *base; /* NSS_GMAC0_BASE */ +}; + +static int +ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv) +{ + u32 busy; + + return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy, + !(busy & MII_BUSY), MII_MDIO_DELAY, + MII_MDIO_RETRY * USEC_PER_MSEC); +} + +static int +ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) +{ + struct ipq8064_mdio *priv = bus->priv; + u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M; + u32 ret_val; + int err; + + /* Reject clause 45 */ + if (reg_offset & MII_ADDR_C45) + return -EOPNOTSUPP; + + miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | + ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); + + regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + usleep_range(10, 20); + + err = ipq8064_mdio_wait_busy(priv); + if (err) + return err; + + regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); + return (int)ret_val; +} + +static int +ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) +{ + struct ipq8064_mdio *priv = bus->priv; + u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M; + + /* Reject clause 45 */ + if (reg_offset & MII_ADDR_C45) + return -EOPNOTSUPP; + + regmap_write(priv->base, MII_DATA_REG_ADDR, data); + + miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) | + ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); + + regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); + usleep_range(10, 20); + + return ipq8064_mdio_wait_busy(priv); +} + +static int +ipq8064_mdio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct ipq8064_mdio *priv; + struct mii_bus *bus; + int ret; + + bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); + if (!bus) + return -ENOMEM; + + bus->name = "ipq8064_mdio_bus"; + bus->read = ipq8064_mdio_read; + bus->write = ipq8064_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); + bus->parent = &pdev->dev; + + priv = bus->priv; + priv->base = syscon_node_to_regmap(np); + if (IS_ERR_OR_NULL(priv->base)) { + priv->base = syscon_regmap_lookup_by_phandle(np, "master"); + if (IS_ERR_OR_NULL(priv->base)) { + dev_err(&pdev->dev, "master phandle not found\n"); + return -EINVAL; + } + } + + ret = of_mdiobus_register(bus, np); + if (ret) + return ret; + + platform_set_drvdata(pdev, bus); + return 0; +} + +static int +ipq8064_mdio_remove(struct platform_device *pdev) +{ + struct mii_bus *bus = platform_get_drvdata(pdev); + + mdiobus_unregister(bus); + + return 0; +} + +static const struct of_device_id ipq8064_mdio_dt_ids[] = { + { .compatible = "qcom,ipq8064-mdio" }, + { } +}; +MODULE_DEVICE_TABLE(of, ipq8064_mdio_dt_ids); + +static struct platform_driver ipq8064_mdio_driver = { + .probe = ipq8064_mdio_probe, + .remove = ipq8064_mdio_remove, + .driver = { + .name = "ipq8064-mdio", + .of_match_table = ipq8064_mdio_dt_ids, + }, +}; + +module_platform_driver(ipq8064_mdio_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver"); +MODULE_AUTHOR("Christian Lamparter "); +MODULE_LICENSE("GPL"); From patchwork Thu Feb 20 17:07:29 2020 Content-Type: text/plain; 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[93.39.149.95]) by smtp.googlemail.com with ESMTPSA id o77sm5817883wme.34.2020.02.20.09.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2020 09:07:45 -0800 (PST) From: Ansuel Smith Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , "David S. Miller" , Rob Herring , Mark Rutland , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Russell King , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] Documentation: devictree: Add ipq806x mdio bindings Date: Thu, 20 Feb 2020 18:07:29 +0100 Message-Id: <20200220170732.12741-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200220170732.12741-1-ansuelsmth@gmail.com> References: <20200220170732.12741-1-ansuelsmth@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentations for ipq806x mdio driver. Signed-off-by: Ansuel Smith --- .../bindings/net/qcom,ipq8064-mdio.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml new file mode 100644 index 000000000000..c5a21c0b5325 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.txt +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x MDIO bus controller + +description: |+ + The ipq806x soc have a MDIO dedicated controller that is + used to comunicate with the gmac phy conntected. + Child nodes of this MDIO bus controller node are standard + Ethernet PHY device nodes as described in + Documentation/devicetree/bindings/net/phy.txt + +allOf: + - $ref: "mdio.yaml#" + +properties: + compatible: + const: qcom,ipq8064-mdio + reg: + maxItems: 1 + description: address and length of the register set for the device + clocks: + maxItems: 1 + description: A reference to the clock supplying the MDIO bus controller + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + +examples: + - | + mdio@37000000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,ipq8064-mdio", "syscon"; + reg = <0x37000000 0x200000>; + resets = <&gcc GMAC_CORE1_RESET>; + reset-names = "stmmaceth"; + clocks = <&gcc GMAC_CORE1_CLK>; + + switch@10 { + compatible = "qca,qca8337"; + ... + } + }; \ No newline at end of file