From patchwork Mon Jan 27 20:03:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 205326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1219FC2D0DB for ; Mon, 27 Jan 2020 20:04:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D60A224681 for ; Mon, 27 Jan 2020 20:04:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="M5GMLT5S" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726605AbgA0UEV (ORCPT ); Mon, 27 Jan 2020 15:04:21 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:21884 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726428AbgA0UEU (ORCPT ); Mon, 27 Jan 2020 15:04:20 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580155459; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=RJAMdUDP8dF7r2pNL8GlWJRlgLG0/Bk8X3egAxim7JQ=; b=M5GMLT5S2Lify/wg0vpUEClQasSAvixuQ6YIAVHlofdxE0O7TIpJQjKQQnNnKDH3YhYD/bbf 1Tj95GPPctEoi6VM0bTQVLm5U+L0kXswpguyseFOdNbge2tJdu3Y6JejoSICiGWAsMs3WdNV 7GqGKlvm4Uet0WPjRzcvJhv5qNI= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e2f4242.7fb047415148-smtp-out-n02; Mon, 27 Jan 2020 20:04:18 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C584CC447A6; Mon, 27 Jan 2020 20:04:18 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id EE142C447A4; Mon, 27 Jan 2020 20:04:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org EE142C447A4 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, mka@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, Sibi Sankar Subject: [RFC v3 02/10] cpufreq: blacklist SDM845 in cpufreq-dt-platdev Date: Tue, 28 Jan 2020 01:33:42 +0530 Message-Id: <20200127200350.24465-3-sibis@codeaurora.org> X-Mailer: git-send-email 2.22.1 In-Reply-To: <20200127200350.24465-1-sibis@codeaurora.org> References: <20200127200350.24465-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add SDM845 to cpufreq-dt-platdev blacklist. Signed-off-by: Sibi Sankar --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index f2ae9cd455c17..5492cf3c9dc18 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -130,6 +130,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,apq8096", }, { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, + { .compatible = "qcom,sdm845", }, { .compatible = "st,stih407", }, { .compatible = "st,stih410", }, From patchwork Mon Jan 27 20:03:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 205325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33C63C33CB7 for ; Mon, 27 Jan 2020 20:04:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0224724690 for ; Mon, 27 Jan 2020 20:04:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="QaRlV8pL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727215AbgA0UEg (ORCPT ); Mon, 27 Jan 2020 15:04:36 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:25529 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727141AbgA0UEf (ORCPT ); Mon, 27 Jan 2020 15:04:35 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580155475; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=tRkiug46cbevcWIh2EsjxvwfdWbmSAuqNGdTaK/He0k=; b=QaRlV8pL8Nf0ncN5knbgH2K6kOOL2km2FYF7+GubWtljbxCebT/vPwVJ/XQhSHx0JV0tibsL 40zPkof6nwQF2MLi3n2mk1+smmgyi9fSMVWsTh6/qkySJKu+Hy/np17ZX25Mx25VrxFuTImt firMcM1Hbnb7Tz2j5AnPomjZvGg= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e2f4251.7f0f2c0193b0-smtp-out-n03; Mon, 27 Jan 2020 20:04:33 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0E1F6C447A6; Mon, 27 Jan 2020 20:04:32 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6658EC433CB; Mon, 27 Jan 2020 20:04:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6658EC433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, mka@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, Sibi Sankar Subject: [RFC v3 04/10] OPP: Add and export helper to update voltage Date: Tue, 28 Jan 2020 01:33:44 +0530 Message-Id: <20200127200350.24465-5-sibis@codeaurora.org> X-Mailer: git-send-email 2.22.1 In-Reply-To: <20200127200350.24465-1-sibis@codeaurora.org> References: <20200127200350.24465-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add and export 'dev_pm_opp_update_voltage' to find and update voltage of an opp for a given frequency. This will be useful to update the opps with voltages read back from firmware. Signed-off-by: Sibi Sankar --- drivers/opp/core.c | 55 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 10 ++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 9aa2a44a5d638..f241e83ec926a 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2503,6 +2503,61 @@ int dev_pm_opp_disable(struct device *dev, unsigned long freq) } EXPORT_SYMBOL_GPL(dev_pm_opp_disable); +/** + * dev_pm_opp_update_voltage() - Find and update voltage + * @dev: device for which we do this operation + * @freq: OPP frequency to update voltage + * @u_volt: voltage requested for this opp + * + * Find and update voltage of a disabled opp corresponding to the given + * frequency. This is useful only for devices with single power supply. + * + * Return: 0 if modification was successful or a negative error value. + */ +int dev_pm_opp_update_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt) +{ + struct dev_pm_opp *opp = ERR_PTR(-ENODEV); + struct opp_table *opp_table; + unsigned long tol; + int ret = 0; + + /* Find the opp_table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + ret = PTR_ERR(opp_table); + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, ret); + return PTR_ERR(opp_table); + } + + opp = dev_pm_opp_find_freq_exact(dev, freq, false); + if (IS_ERR(opp)) { + ret = PTR_ERR(opp); + goto put_table; + } + + mutex_lock(&opp_table->lock); + + /* update only if the opp is disabled */ + if (opp->available) { + ret = -EBUSY; + goto unlock; + } + + tol = u_volt * opp_table->voltage_tolerance_v1 / 100; + opp->supplies[0].u_volt_min = u_volt - tol; + opp->supplies[0].u_volt = u_volt; + opp->supplies[0].u_volt_min = u_volt + tol; + +unlock: + mutex_unlock(&opp_table->lock); + dev_pm_opp_put(opp); +put_table: + dev_pm_opp_put_opp_table(opp_table); + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_update_voltage); + /** * dev_pm_opp_register_notifier() - Register OPP notifier for the device * @dev: Device for which notifier needs to be registered diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 62c88898bae46..b26d492cbd635 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -132,6 +132,9 @@ int dev_pm_opp_enable(struct device *dev, unsigned long freq); int dev_pm_opp_disable(struct device *dev, unsigned long freq); +int dev_pm_opp_update_voltage(struct device *dev, unsigned long freq, + unsigned long u_volt); + int dev_pm_opp_register_notifier(struct device *dev, struct notifier_block *nb); int dev_pm_opp_unregister_notifier(struct device *dev, struct notifier_block *nb); @@ -311,6 +314,13 @@ static inline int dev_pm_opp_disable(struct device *dev, unsigned long freq) return 0; } +static inline int dev_pm_opp_update_voltage(struct device *dev, + unsigned long freq, + unsigned long u_volt) +{ + return 0; +} + static inline int dev_pm_opp_register_notifier(struct device *dev, struct notifier_block *nb) { return -ENOTSUPP; From patchwork Mon Jan 27 20:03:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 205324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD74BC33CB7 for ; Mon, 27 Jan 2020 20:04:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD4012467B for ; Mon, 27 Jan 2020 20:04:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="b9PIir9b" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727312AbgA0UEz (ORCPT ); Mon, 27 Jan 2020 15:04:55 -0500 Received: from mail25.static.mailgun.info ([104.130.122.25]:59383 "EHLO mail25.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727296AbgA0UEz (ORCPT ); Mon, 27 Jan 2020 15:04:55 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580155494; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=1/OCv/YWi9A5ql/vJL6uSomFHcmrXg+3BhQMo7h7H4I=; b=b9PIir9bN6vkHfrMconkhm00guG8z1QnHpepjo+dVZM/zr/7tM+6MEDSACyS7Z5QCRUfzjTn EYHJiMErsTIbP0vKhqPO7Fdiy/w/fnX7mzU73pI5fTmg3vWJ6MgAUHAWhaHl7bfAakV7rdxa hOSov0nnL6EJAf1x5RF0dX0bTrM= X-Mailgun-Sending-Ip: 104.130.122.25 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e2f4266.7fd3cd82a9d0-smtp-out-n03; Mon, 27 Jan 2020 20:04:54 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 249EBC447A4; Mon, 27 Jan 2020 20:04:53 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 409D1C447A1; Mon, 27 Jan 2020 20:04:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 409D1C447A1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, mka@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, Sibi Sankar Subject: [RFC v3 07/10] opp: Remove multiple attached opp tables from a device Date: Tue, 28 Jan 2020 01:33:47 +0530 Message-Id: <20200127200350.24465-8-sibis@codeaurora.org> X-Mailer: git-send-email 2.22.1 In-Reply-To: <20200127200350.24465-1-sibis@codeaurora.org> References: <20200127200350.24465-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce _dev_pm_opp_find_and_remove_table_indexed to remove all the linked opp tables from a device. Signed-off-by: Sibi Sankar --- drivers/opp/core.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index e9d633c9e40b1..cc2f156db7fda 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2632,12 +2632,13 @@ int dev_pm_opp_unregister_notifier(struct device *dev, } EXPORT_SYMBOL(dev_pm_opp_unregister_notifier); -void _dev_pm_opp_find_and_remove_table(struct device *dev) +static void _dev_pm_opp_find_and_remove_table_indexed(struct device *dev, + int index) { struct opp_table *opp_table; /* Check for existing table for 'dev' */ - opp_table = _find_opp_table_indexed(dev, 0); + opp_table = _find_opp_table_indexed(dev, index); if (IS_ERR(opp_table)) { int error = PTR_ERR(opp_table); @@ -2658,6 +2659,18 @@ void _dev_pm_opp_find_and_remove_table(struct device *dev) dev_pm_opp_put_opp_table(opp_table); } +void _dev_pm_opp_find_and_remove_table(struct device *dev) +{ + int count, i; + + count = of_count_phandle_with_args(dev->of_node, + "operating-points-v2", NULL); + count = max(count, 1); + + for (i = 0; i < count; i++) + _dev_pm_opp_find_and_remove_table_indexed(dev, i); +} + /** * dev_pm_opp_remove_table() - Free all OPPs associated with the device * @dev: device pointer used to lookup OPP table. From patchwork Mon Jan 27 20:03:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 205323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C5FBC2D0DB for ; Mon, 27 Jan 2020 20:05:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F188124682 for ; Mon, 27 Jan 2020 20:05:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="M0qaC6DM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727964AbgA0UFK (ORCPT ); Mon, 27 Jan 2020 15:05:10 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:51737 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727966AbgA0UFJ (ORCPT ); Mon, 27 Jan 2020 15:05:09 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1580155509; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=vXpcj24gh8Hf2SF5qmdc6zSo0d57MQ7C6Pr/nZ9vIMU=; b=M0qaC6DMTsq3OinXGIqSjwk7wYggEfzWe+wKVrKqhcGPBT5nwlkiX0YlTPgpIoWR7+PKT18l 2tNWu8VVbGOsrCAbkc6xUMU7MocqNoSxvOkD5HoxEaLUerdLxyxjeMS1yv4maWo3nZDy+/OC 2jeejzdZzQAU5UD7KhCE6TwwoRc= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e2f426e.7fd3cd82ac00-smtp-out-n03; Mon, 27 Jan 2020 20:05:02 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0D2B4C447A1; Mon, 27 Jan 2020 20:05:00 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id EBA6CC447A2; Mon, 27 Jan 2020 20:04:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org EBA6CC447A2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, mka@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, Sibi Sankar Subject: [RFC v3 08/10] cpufreq: qcom: Update the bandwidth levels on frequency change Date: Tue, 28 Jan 2020 01:33:48 +0530 Message-Id: <20200127200350.24465-9-sibis@codeaurora.org> X-Mailer: git-send-email 2.22.1 In-Reply-To: <20200127200350.24465-1-sibis@codeaurora.org> References: <20200127200350.24465-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to parse and update OPP tables attached to the cpu device when the required OPP bandwidth values are populated to enable scaling of DDR/L3 bandwidth levels with frequency change. Signed-off-by: Sibi Sankar --- drivers/cpufreq/qcom-cpufreq-hw.c | 246 +++++++++++++++++++++++++++--- 1 file changed, 225 insertions(+), 21 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index fc92a8842e252..348eb2fdaccaf 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -28,17 +29,194 @@ #define REG_VOLT_LUT 0x114 #define REG_PERF_STATE 0x920 +#define QCOM_ICC_TAG_ACTIVE_ONLY 1 + static unsigned long cpu_hw_rate, xo_rate; static struct platform_device *global_pdev; +/* opp table indices */ +enum { + QCOM_CPU_OPP_TABLE_INDEX, + QCOM_CPU_DDR_OPP_TABLE_INDEX, + QCOM_CPU_L3_OPP_TABLE_INDEX, +}; + +/* icc path indices */ +enum { + ICC_DDR_PATH, + ICC_L3_PATH, +}; + +struct qcom_cpufreq_hw_res { + void __iomem *base; + + struct device *cpu_dev; + + /* ddr/l3 icc paths */ + struct icc_path *path[2]; + + /* cpu/ddr/l3 opp tables */ + struct opp_table *opp_table[3]; +}; + +struct cpufreq_hw_icc_info { + const char *icc_path_name; + u8 table_index; + u32 tag; +}; + +static const struct cpufreq_hw_icc_info icc_info[] = { + { + .icc_path_name = "cpu-ddr", + .table_index = QCOM_CPU_DDR_OPP_TABLE_INDEX, + .tag = QCOM_ICC_TAG_ACTIVE_ONLY, + }, + { + .icc_path_name = "cpu-l3", + .table_index = QCOM_CPU_L3_OPP_TABLE_INDEX, + .tag = 0, + }, +}; + +static int qcom_cpufreq_hw_add_opp_table(struct qcom_cpufreq_hw_res *res) +{ + struct opp_table **table = res->opp_table; + struct device_node *opp_table_np, *np; + struct device *dev = res->cpu_dev; + int ret, i; + u64 rate; + + for (i = 0; i <= QCOM_CPU_L3_OPP_TABLE_INDEX; i++) { + ret = dev_pm_opp_of_add_table_indexed(dev, i); + if (ret) { + dev_dbg(dev, "Add OPP table failed index %d: %d\n", + i, ret); + goto err; + } + + table[i] = dev_pm_opp_get_opp_table_indexed(dev, i); + if (!table[i]) { + dev_dbg(dev, "Get OPP table failed index %d\n", i); + ret = -EINVAL; + goto err; + } + } + + /* Disable all cpu opps and cross-validate against LUT */ + opp_table_np = dev_pm_opp_of_get_opp_desc_node(dev); + for_each_available_child_of_node(opp_table_np, np) { + ret = of_property_read_u64(np, "opp-hz", &rate); + if (ret) + continue; + + dev_pm_opp_disable(dev, rate); + } + of_node_put(opp_table_np); + + return 0; + +err: + for (; i >= 0; i--) { + if (table[i]) { + dev_pm_opp_put_opp_table(table[i]); + table[i] = NULL; + } + } + + dev_pm_opp_remove_table(dev); + return ret; +} + +static int qcom_cpufreq_hw_icc_init(struct qcom_cpufreq_hw_res *res, u8 index) +{ + const struct cpufreq_hw_icc_info *info = &icc_info[index]; + struct icc_path **path = res->path; + struct device *dev = res->cpu_dev; + + path[index] = of_icc_get(dev, info->icc_path_name); + if (IS_ERR(path[index])) { + dev_dbg(dev, "ICC %s path get failed ret: %ld\n", + info->icc_path_name, PTR_ERR(path[index])); + return PTR_ERR(path[index]); + } + + icc_set_tag(path[index], info->tag); + + return 0; +} + +static void qcom_cpufreq_hw_icc_set(struct qcom_cpufreq_hw_res *res, + unsigned long freq) +{ + struct opp_table **table = res->opp_table; + const struct cpufreq_hw_icc_info *info; + unsigned long freq_hz = freq * 1000; + struct icc_path **path = res->path; + struct device *dev = res->cpu_dev; + struct dev_pm_opp *cpu_opp, *opp; + struct opp_table *cpu_opp_table; + unsigned long peak_bw, avg_bw; + int ret; + int i; + + cpu_opp_table = table[QCOM_CPU_OPP_TABLE_INDEX]; + if (!cpu_opp_table) + return; + + cpu_opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); + if (IS_ERR_OR_NULL(cpu_opp)) + return; + + for (i = 0; i <= ICC_L3_PATH; i++) { + if (IS_ERR(path[i])) { + if (PTR_ERR(path[i]) != -EPROBE_DEFER) + continue; + + ret = qcom_cpufreq_hw_icc_init(res, i); + if (ret) + continue; + } + + info = &icc_info[i]; + + opp = dev_pm_opp_xlate_required_opp(cpu_opp_table, + table[info->table_index], + cpu_opp); + if (IS_ERR_OR_NULL(opp)) + continue; + + peak_bw = dev_pm_opp_get_bw(opp, &avg_bw); + dev_pm_opp_put(opp); + + icc_set_bw(res->path[i], avg_bw, peak_bw); + } + dev_pm_opp_put(cpu_opp); +} + +static int qcom_cpufreq_update_opp(struct device *dev, + unsigned long freq_khz, + unsigned long volt) +{ + unsigned long freq_hz = freq_khz * 1000; + + if (dev_pm_opp_update_voltage(dev, freq_hz, volt)) + return dev_pm_opp_add(dev, freq_hz, volt); + + /* Enable the opp after voltage update*/ + return dev_pm_opp_enable(dev, freq_hz); +} + static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { - void __iomem *perf_state_reg = policy->driver_data; + struct qcom_cpufreq_hw_res *res = policy->driver_data; + void __iomem *perf_state_reg = res->base + REG_PERF_STATE; unsigned long freq = policy->freq_table[index].frequency; writel_relaxed(index, perf_state_reg); + qcom_cpufreq_hw_icc_set(res, freq); + arch_set_freq_scale(policy->related_cpus, freq, policy->cpuinfo.max_freq); return 0; @@ -46,6 +224,7 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) { + struct qcom_cpufreq_hw_res *res; void __iomem *perf_state_reg; struct cpufreq_policy *policy; unsigned int index; @@ -54,7 +233,8 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) if (!policy) return 0; - perf_state_reg = policy->driver_data; + res = policy->driver_data; + perf_state_reg = res->base + REG_PERF_STATE; index = readl_relaxed(perf_state_reg); index = min(index, LUT_MAX_ENTRIES - 1); @@ -65,7 +245,8 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, unsigned int target_freq) { - void __iomem *perf_state_reg = policy->driver_data; + struct qcom_cpufreq_hw_res *res = policy->driver_data; + void __iomem *perf_state_reg = res->base + REG_PERF_STATE; int index; unsigned long freq; @@ -82,18 +263,24 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, return freq; } -static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, - struct cpufreq_policy *policy, - void __iomem *base) +static int qcom_cpufreq_hw_read_lut(struct cpufreq_policy *policy, + struct qcom_cpufreq_hw_res *res) { u32 data, src, lval, i, core_count, prev_freq = 0, freq; u32 volt; struct cpufreq_frequency_table *table; + struct device *cpu_dev = res->cpu_dev; + void __iomem *base = res->base; + int ret; table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) return -ENOMEM; + ret = qcom_cpufreq_hw_add_opp_table(res); + if (ret) + dev_dbg(cpu_dev, "Add OPP tables failed from dt\n"); + for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base + REG_FREQ_LUT + i * LUT_ROW_SIZE); @@ -112,7 +299,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, if (freq != prev_freq && core_count != LUT_TURBO_IND) { table[i].frequency = freq; - dev_pm_opp_add(cpu_dev, freq * 1000, volt); + qcom_cpufreq_update_opp(cpu_dev, freq, volt); dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, freq, core_count); } else if (core_count == LUT_TURBO_IND) { @@ -133,7 +320,8 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, if (prev->frequency == CPUFREQ_ENTRY_INVALID) { prev->frequency = prev_freq; prev->flags = CPUFREQ_BOOST_FREQ; - dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt); + qcom_cpufreq_update_opp(cpu_dev, prev_freq, + volt); } break; @@ -175,11 +363,10 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct device *dev = &global_pdev->dev; + struct qcom_cpufreq_hw_res *res; struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; - struct resource *res; - void __iomem *base; int ret, index; cpu_dev = get_cpu_device(policy->cpu); @@ -201,16 +388,17 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) index = args.args[0]; - res = platform_get_resource(global_pdev, IORESOURCE_MEM, index); + res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL); if (!res) - return -ENODEV; - - base = devm_ioremap(dev, res->start, resource_size(res)); - if (!base) return -ENOMEM; + res->cpu_dev = cpu_dev; + res->base = devm_platform_ioremap_resource(global_pdev, index); + if (IS_ERR(res->base)) + return PTR_ERR(res->base); + /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) { + if (!(readl_relaxed(res->base + REG_ENABLE) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); ret = -ENODEV; goto error; @@ -223,9 +411,9 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) goto error; } - policy->driver_data = base + REG_PERF_STATE; + policy->driver_data = res; - ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base); + ret = qcom_cpufreq_hw_read_lut(policy, res); if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); goto error; @@ -240,22 +428,38 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) dev_pm_opp_of_register_em(policy->cpus); - policy->fast_switch_possible = true; + if (!res->opp_table[QCOM_CPU_OPP_TABLE_INDEX]) { + policy->fast_switch_possible = true; + } else { + qcom_cpufreq_hw_icc_init(res, ICC_DDR_PATH); + qcom_cpufreq_hw_icc_init(res, ICC_L3_PATH); + } return 0; error: - devm_iounmap(dev, base); + devm_iounmap(dev, res->base); + devm_kfree(&global_pdev->dev, res); return ret; } static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { + struct qcom_cpufreq_hw_res *res = policy->driver_data; struct device *cpu_dev = get_cpu_device(policy->cpu); - void __iomem *base = policy->driver_data - REG_PERF_STATE; + struct opp_table **table = res->opp_table; + void __iomem *base = res->base; + int i; + + for (i = 0; i <= QCOM_CPU_L3_OPP_TABLE_INDEX; i++) { + if (table[i]) + dev_pm_opp_put_opp_table(table[i]); + } dev_pm_opp_remove_all_dynamic(cpu_dev); kfree(policy->freq_table); + dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); devm_iounmap(&global_pdev->dev, base); + devm_kfree(&global_pdev->dev, res); return 0; } From patchwork Mon Jan 27 20:03:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 205322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87F76C2D0DB for ; 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Mon, 27 Jan 2020 20:05:17 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id D7E22C433CB; Mon, 27 Jan 2020 20:05:15 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id EA089C433CB; Mon, 27 Jan 2020 20:05:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org EA089C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, david.brown@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, mka@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, ulf.hansson@linaro.org, Sibi Sankar Subject: [RFC v3 10/10] arm64: dts: qcom: sc7180: Add cpu OPP tables Date: Tue, 28 Jan 2020 01:33:50 +0530 Message-Id: <20200127200350.24465-11-sibis@codeaurora.org> X-Mailer: git-send-email 2.22.1 In-Reply-To: <20200127200350.24465-1-sibis@codeaurora.org> References: <20200127200350.24465-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add OPP tables required to scale DDR/L3 per freq-domain on SC7180 SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ba53ddf17ee3a..699cafc1a727d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -109,6 +109,12 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>, + <&cpu0_ddr_bw_opp_table>, + <&cpu0_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; next-level-cache = <&L2_0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -129,6 +135,12 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>, + <&cpu0_ddr_bw_opp_table>, + <&cpu0_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { @@ -145,6 +157,12 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>, + <&cpu0_ddr_bw_opp_table>, + <&cpu0_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { @@ -161,6 +179,12 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>, + <&cpu0_ddr_bw_opp_table>, + <&cpu0_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { @@ -177,6 +201,12 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu0_opp_table>, + <&cpu0_ddr_bw_opp_table>, + <&cpu0_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { @@ -193,6 +223,12 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu0_opp_table>, + <&cpu0_ddr_bw_opp_table>, + <&cpu0_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { @@ -209,6 +245,12 @@ capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu6_opp_table>, + <&cpu6_ddr_bw_opp_table>, + <&cpu6_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { @@ -225,6 +267,12 @@ capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu6_opp_table>, + <&cpu6_ddr_bw_opp_table>, + <&cpu6_l3_bw_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnect-names = "cpu-ddr", "cpu-l3"; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { @@ -270,6 +318,245 @@ }; }; + cpu0_opp_table: cpu0_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cpu0_ddr_bw_opp1>, <&cpu0_l3_bw_opp1>; + }; + + cpu0_opp2: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&cpu0_ddr_bw_opp1>, <&cpu0_l3_bw_opp1>; + }; + + cpu0_opp3: opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + required-opps = <&cpu0_ddr_bw_opp1>, <&cpu0_l3_bw_opp1>; + }; + + cpu0_opp4: opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + required-opps = <&cpu0_ddr_bw_opp2>, <&cpu0_l3_bw_opp2>; + }; + + cpu0_opp5: opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cpu0_ddr_bw_opp3>, <&cpu0_l3_bw_opp3>; + }; + + cpu0_opp6: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + required-opps = <&cpu0_ddr_bw_opp3>, <&cpu0_l3_bw_opp3>; + }; + + cpu0_opp7: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + required-opps = <&cpu0_ddr_bw_opp4>, <&cpu0_l3_bw_opp4>; + }; + + cpu0_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + required-opps = <&cpu0_ddr_bw_opp4>, <&cpu0_l3_bw_opp4>; + }; + + cpu0_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + required-opps = <&cpu0_ddr_bw_opp4>, <&cpu0_l3_bw_opp4>; + }; + + cpu0_opp10: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + required-opps = <&cpu0_ddr_bw_opp5>, <&cpu0_l3_bw_opp5>; + }; + }; + + cpu6_opp_table: cpu6_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>; + }; + + cpu6_opp2: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>; + }; + + cpu6_opp3: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>; + }; + + cpu6_opp4: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>; + }; + + cpu6_opp5: opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + required-opps = <&cpu6_ddr_bw_opp1>, <&cpu6_l3_bw_opp1>; + }; + + cpu6_opp6: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + required-opps = <&cpu6_ddr_bw_opp2>, <&cpu6_l3_bw_opp2>; + }; + + cpu6_opp7: opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + required-opps = <&cpu6_ddr_bw_opp2>, <&cpu6_l3_bw_opp3>; + }; + + cpu6_opp8: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp4>; + }; + + cpu6_opp9: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp4>; + }; + + cpu6_opp10: opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp5>; + }; + + cpu6_opp11: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp5>; + }; + + cpu6_opp12: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + required-opps = <&cpu6_ddr_bw_opp3>, <&cpu6_l3_bw_opp5>; + }; + + cpu6_opp13: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + required-opps = <&cpu6_ddr_bw_opp4>, <&cpu6_l3_bw_opp5>; + }; + + cpu6_opp14: opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + required-opps = <&cpu6_ddr_bw_opp4>, <&cpu6_l3_bw_opp5>; + }; + + cpu6_opp15: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + required-opps = <&cpu6_ddr_bw_opp5>, <&cpu6_l3_bw_opp6>; + }; + }; + + cpu0_ddr_bw_opp_table: cpu0-ddr-bw-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_ddr_bw_opp1: opp-300000000 { + opp-peak-kBps =/bits/ 32 <1200000>; + }; + + cpu0_ddr_bw_opp2: opp-451000000 { + opp-peak-kBps =/bits/ 32 <1804000>; + }; + + cpu0_ddr_bw_opp3: opp-547000000 { + opp-peak-kBps =/bits/ 32 <2188000>; + }; + + cpu0_ddr_bw_opp4: opp-768000000 { + opp-peak-kBps =/bits/ 32 <3072000>; + }; + + cpu0_ddr_bw_opp5: opp-1017000000 { + opp-peak-kBps =/bits/ 32 <4068000>; + }; + }; + + cpu0_l3_bw_opp_table: cpu0-l3-bw-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_l3_bw_opp1: opp-300000000 { + opp-peak-kBps = /bits/ 32 <4800000>; + }; + + cpu0_l3_bw_opp2: opp-556800000 { + opp-peak-kBps = /bits/ 32 <8908800>; + }; + + cpu0_l3_bw_opp3: opp-806400000 { + opp-peak-kBps = /bits/ 32 <12902400>; + }; + + cpu0_l3_bw_opp4: opp-940800000 { + opp-peak-kBps = /bits/ 32 <15052800>; + }; + + cpu0_l3_bw_opp5: opp-1401000000 { + opp-peak-kBps = /bits/ 32 <22425600>; + }; + }; + + cpu6_ddr_bw_opp_table: cpu6-ddr-bw-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_ddr_bw_opp1: opp-547000000 { + opp-peak-kBps =/bits/ 32 <2188000>; + }; + + cpu6_ddr_bw_opp2: opp-1017000000 { + opp-peak-kBps =/bits/ 32 <4068000>; + }; + + cpu6_ddr_bw_opp3: opp-1555000000 { + opp-peak-kBps =/bits/ 32 <6220000>; + }; + + cpu6_ddr_bw_opp4: opp-1804000000 { + opp-peak-kBps =/bits/ 32 <7216000>; + }; + + cpu6_ddr_bw_opp5: opp-2133000000 { + opp-peak-kBps =/bits/ 32 <8532000>; + }; + }; + + cpu6_l3_bw_opp_table: cpu6-l3-bw-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_l3_bw_opp1: opp-556800000 { + opp-peak-kBps = /bits/ 32 <8908800>; + }; + + cpu6_l3_bw_opp2: opp-806400000 { + opp-peak-kBps = /bits/ 32 <12902400>; + }; + + cpu6_l3_bw_opp3: opp-940800000 { + opp-peak-kBps = /bits/ 32 <15052800>; + }; + + cpu6_l3_bw_opp4: opp-1209600000 { + opp-peak-kBps = /bits/ 32 <19353600>; + }; + + cpu6_l3_bw_opp5: opp-1401000000 { + opp-peak-kBps = /bits/ 32 <22425600>; + }; + + cpu6_l3_bw_opp6: opp-1459000000 { + opp-peak-kBps = /bits/ 32 <23347200>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */