From patchwork Sat Aug 26 08:57:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111046 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2175874qge; Sat, 26 Aug 2017 01:59:59 -0700 (PDT) X-Received: by 10.80.170.145 with SMTP id q17mr1156623edc.283.1503737999320; Sat, 26 Aug 2017 01:59:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503737999; cv=none; d=google.com; s=arc-20160816; b=deEVtpcdvlWUXbr4lU1VYiB3oSIPCSCE4fGKloMp+UR85AqrgeV4jpsslXj0dVqRe+ U0cfLqD4/aA5FN3ovoLvVI+0TPFj23gTEc8e1VJ3enUAfC3iUpicOD6qoROSks1WPd2G Dhdcw9tJhxJWw75jEblddUMpB2qP+Jha9iyHWhLBIGyr+zsP/PJPF2CSjw37sCh6gmVC 71Tbr9A8o2jaTiELsc4pi5vBEPYSE1Uie2P+x56HaS/K940EZyNlyFbc1con4p1zJqSU g32qwbAV6TIvjkQt8qeO5Lj2W8mES8hKhW2xXFtBIlm0jm99VVgiL+r9QIueSHsR5/gZ u/6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=QA7JW9uun+0QholNRLFQcMPsy4UrpBzZYp+r44PnaBQ=; b=hALjvmN9cORcDo+UfMBdYo+MsXvkt3buockx1zqamXWLBDvY/3s6GTQWeYwRuX5oOO Zh12kyDpBrAgeG7w08QlSkprEQPOcBbMKi/PU9d1MHMbO6NP5URbktrcoJRD1k7GhCHy KIADn2BNFxpNRGhrTZSp3sUfUYM9Z7+sKgI44URnYA4Gn1XWpbbIEa1MhVHONJw0u108 DLjR9TwjMUpSSF/WRL0khiFpKienJEvuw5xMzv0/CNpwm2w/G4xti+12tjd5JKAYPZbX 1kCuxEv1+fwVRI+Rxw+2WeE1E5fEpLjcaMeTzrlQf6EVJrVgPOav19p0ux9qzL6jywzL NADQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=SM9+sXjK; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id r12si5353344edd.122.2017.08.26.01.59.59; Sat, 26 Aug 2017 01:59:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=SM9+sXjK; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id D221AC22084; Sat, 26 Aug 2017 08:59:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B9238C22080; Sat, 26 Aug 2017 08:58:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 46DAAC2206A; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 1D7FFC22071 for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANM031195; Sat, 26 Aug 2017 17:58:11 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANM031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737891; bh=LP8obSSG5S9aaGvQigqrrO32OxPXN1l/cnXJZ1vN4qs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SM9+sXjKAppGRCQWnTnMbDZ1YBaCdoKHt3qFZaC2uo7bca5mWnn+Vsp8+1DSQkfZq C3sKp6w5iqbfhQvQs6ubEyW2N2Y4KVCP9RB6lCIE1jxyneQXn4ub+DgkpOeJnjyCtl Y8qe3gHdmQK4vCRAx2jrxfVdf76JwUcVuPUDf64AX4jXCNKy3sP/1vQWqKCo4IQWNU F849GVwpGy60XYcuoj4eHeg8IQ5GJ6zkJ2gQA5pFoPgZ+XmX28hKmpkDCZtmn0QPkC Z2QdZHYCIXF7dFic8ArfDYb4g3K8afl/XjYvDSc0OXfOVEpk5J9amAaehdZYYsiiUv fyHhi/wAKaIlQ== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:57:58 +0900 Message-Id: <1503737883-14236-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 1/6] ARM: uniphier: replace with in pll settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The #include was added for mdelay(). Later, the declaration of mdelay was moved to by commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h"). There is no need to include now. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-ld11.c | 2 +- arch/arm/mach-uniphier/clk/pll-ld20.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index 02befa298b46..b4a97d21610f 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include #include #include "../init.h" diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 121a3690e834..50b91598d64d 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include +#include #include "../init.h" #include "../sc64-regs.h" From patchwork Sat Aug 26 08:57:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111047 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2176633qge; Sat, 26 Aug 2017 02:00:40 -0700 (PDT) X-Received: by 10.80.172.166 with SMTP id x35mr1098331edc.209.1503738040156; Sat, 26 Aug 2017 02:00:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503738040; cv=none; d=google.com; s=arc-20160816; b=QzcBNXh6PRsbD0UfSXkbrh8F9D6a7AOWAjZUSNkyG12AE3QHzIiGYZgg2d1Qum4mLA 5RmonrgssUcBWtkZyEZZNJO3rjocvywB8bysWXtA0U3vg2gNEX9Pt3f9zoXSiA1Rr/oq obZGezqmTl3add8awUcQpR48jWZKEGwFYE8EJ4dNjrhVPxcGJDi04W1ofDt5N+UoCwyj a+cZ0bbCqQxQUwgOx5/KPl7O/y4/mAkA8rdNLaeNFbrWNiEJXtIjDs/CKgWjRctkYLx7 qCMt8wdjsF1dLBQ4uqZSLdTJNblISIN1OsAikz5zt9AwUxc4wV3IWTmui23bVcFb2nbU GCJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=1Y/iwob8ncIXyiGumMOAGVjR47jjuiJ0hZxJs0Gs5Lg=; b=IlQD+SPYxJB1fop3wK6tsHNMl7rF/7MdXFy85m6LcBUA443Ks21kufOAgM0aI0B98o HxQo8iohLQ6C3QcViaqO29u8UsdzNGpRDq/cJy2JO7+ih4g33VxA1HRRJK2JW1QCHwku O39xX0Qcw64NHkFwduywqu322aGJVSQUf9qQEDiaqtbUIJQxXm987W9Ho3unmIG0nan+ M5HVWJh5UH+8ckWnoCiAPbXj57+7V3J0Q/1vLrspmUSMxgIwj2F3S4eqBcPbSPlwx5zU j7d754iFMxFZlrZNDe+E7jgUuBJK5OOhKkOhPuG1VdfRDll65pebpNrgbVgaEVrBOKIR AMyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=hGoiAghh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l5si1719028ede.402.2017.08.26.02.00.39; Sat, 26 Aug 2017 02:00:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=hGoiAghh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id AEA30C22083; Sat, 26 Aug 2017 08:59:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 92836C2208B; Sat, 26 Aug 2017 08:58:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 66618C2206E; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 126D1C2206E for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANN031195; Sat, 26 Aug 2017 17:58:12 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANN031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737892; bh=jVQtLSyRP5VoMUpJMBHGG+4wNWFvtYcPEMqT3mvFDs8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hGoiAghheBFVdY66JoJx0k95/E9k4RRl3/G8YYaQ/7vDRU/A06o+VHR1FGvW01zjk T5iumJFskz6cU7Ttr8i3WPHGC4n4JMIY2/x0kfSvHvbFZXueckBYXgJI8G0LXWAZVo co358xph8/6oOyF8HMid4TpjQQwknPb+CPZ/br6n/5b5GUCrj98NxeXQ9gAyY5a06X XKGUE53MVY7cffyPJQofYuWBCpPqTxux/2IhIaf+X0ihuKsb8BG+yp+HL1hEyU2z2o LBneBTpYvZw2ObLWs0uktn+O4nBhtAGFUElOjQrTpyh4XuUOtNKibf0sIA6v/o6RBr gzPQGaGD9kExQ== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:57:59 +0900 Message-Id: <1503737883-14236-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 2/6] ARM: uniphier: move PLLCTRL register macros to each SoC .c file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-ld11.c | 11 +++++++++++ arch/arm/mach-uniphier/clk/pll-ld20.c | 19 +++++++++++++++++++ arch/arm/mach-uniphier/sc64-regs.h | 21 --------------------- 3 files changed, 30 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index b4a97d21610f..1a7ec2952524 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -11,6 +11,17 @@ #include "../sc64-regs.h" #include "pll.h" +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */ +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + void uniphier_ld11_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */ diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 50b91598d64d..5e072c6dff77 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -11,6 +11,25 @@ #include "../sc64-regs.h" #include "pll.h" +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ +#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) + void uniphier_ld20_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index d3aa18530d97..d0a51f239c38 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -12,27 +12,6 @@ #define SC_BASE_ADDR 0x61840000 -/* PLL type: SSC */ -#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */ -#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */ -#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */ -#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */ -#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */ -#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */ -#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */ -#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */ -#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */ -#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */ -#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */ - -/* PLL type: VPLL27 */ -#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) -#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) - -/* PLL type: DSPLL */ -#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) -#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) - #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) From patchwork Sat Aug 26 08:58:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111048 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2177478qge; Sat, 26 Aug 2017 02:01:24 -0700 (PDT) X-Received: by 10.80.240.199 with SMTP id a7mr1073355edm.268.1503738084424; Sat, 26 Aug 2017 02:01:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503738084; cv=none; d=google.com; s=arc-20160816; b=yY4lms5pfvAQle84V6je/fz5iQ+5ocwcTqq5p4wYZMFgcNlMHJcCp54FYeufh9Zpi3 vs0/Hq225nmdYGAZGdB1hovyxzMOvqaa2Je42PcLrwAVbVTeRzEoQ1ArnWPICgciaF5k UxsdeR+67KaQyjtBxv+Pkrg7MBUj1mVo6tws7ZsVonxSWwbw5BA7E4n89dpogrRA3Y7Q d5hOavxptwFakS9j/dIeKGjhdUb3YKQClZaBYxSVZqmBGVt92bWcAK/60gBCYND6GNMJ NnrW4kYr+qdJrNtCm7oY0kZXtotGaXF8Wh1i6zOMn3ce/3gYyLWhJTatTzBGPYOxuf8C lE7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; 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Sat, 26 Aug 2017 08:58:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 89DA2C2206F; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 2167BC22072 for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANO031195; Sat, 26 Aug 2017 17:58:12 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANO031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737892; bh=qDMTszA/zXp1b9Y23ziItA9FQB5oRNryjscBY0I7pcg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vm3fLlM3NF9KyOJEFsEV3VmRD7zvKG7h84KW5qHjPDeXvBPOS9WkQJAupTVI0OLDB 4eogUxzU/FLRrPPCEADvF/I1v8/32D5tupd9NmqHYwYpcaZkJut2AnCISZyZXGRcFh +BvzjqJGKgbXCx6zbwvuRu9kXNIzugNvZ5dmvaqLgivb6RrODSUKp72xB0nfIE/kfe Qig0+FfRqTt5rc3//WR7RDtQhHAwGBpHQJmYMOfOd3pxMrIiWo15iDVfNW7CzDArKS ONNyguAoWM5zNUMJ4X2hnnElwDg4PFmyQwQe393MXn2LRpviM4trBpz5AXOvUncqWt AGs0iO0FLO0KA== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:58:00 +0900 Message-Id: <1503737883-14236-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 3/6] ARM: uniphier: add PLL settings for PXs3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-pxs3.c | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index 201d3517a86a..e84d52b80f3b 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -1,9 +1,64 @@ /* + * Copyright (C) 2017 Socionext Inc. + * * SPDX-License-Identifier: GPL-2.0+ */ +#include + #include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ +#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) +#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) +#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) +#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) void uniphier_pxs3_pll_init(void) { + uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + uniphier_ld20_dspll_init(SC_VPLL8KCTRL); } From patchwork Sat Aug 26 08:58:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111049 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2177527qge; Sat, 26 Aug 2017 02:01:27 -0700 (PDT) X-Received: by 10.80.225.66 with SMTP id i2mr1094990edl.211.1503738086968; Sat, 26 Aug 2017 02:01:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503738086; cv=none; d=google.com; s=arc-20160816; b=qtdljYQ72ZrmZ0utNveUNpPk5mBbSKrjVGZMXXIAz3aVWywNv9BQgHP8FYXSsGPprS UqsfoOin5smP9IqtC8QWOJrkPPDB8TbVszVmi5/5WCmeHXnt5U3PExywbmhe2jvdElbp 6jJgrjbMKyqK+WVSYJGHVs+H3V+jigOh/7Ec1JnyXL3+GZHXZJnV/HDoqWdZILaWL1yq RVn0jPKuCbLrFQ3Hyr+Nxwsq3KU0QTHVk4fpZeowvkvY9B05DlblS6GLTHbLOi2AY9JC o5S/H0FtBKf7tu6jAtJm5Zif/YJJSvqvAzOZG9qg8F/zS1GB7BTfoSzVM0heW8J7tdiB kKGA== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id z2si7570965eda.386.2017.08.26.02.01.26; Sat, 26 Aug 2017 02:01:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ogoBLplv; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 63357C220A4; Sat, 26 Aug 2017 08:59:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CEDD9C2208F; Sat, 26 Aug 2017 08:58:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 725CCC22064; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 22C3EC22073 for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANP031195; Sat, 26 Aug 2017 17:58:12 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANP031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737893; bh=y/cmzG1/vRxmwUpXw75welAdRvR4Nm9PEerg06/uJZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ogoBLplvYRQIiDYcLxYn9MSIUkKtXIunaOvoSyXNz8tV3mNXwl13W7VpIAnxQBfjC WEeUp0pOb6JFYd6CiZeIMufR92JDFY+Sg7jJxMfOrbDiMJWBoBUhNfWInnmpEik5B+ 6nPAFceYAfGoZXXVntW5EiqObPZFAN9pr/FAm8VZA8gM6edkC4xLSgBWexp0DvRBBz uz/QIm9Cb/0mHR3eDbSWxOOLilk/kETWHvX47osswgrXfV6eyBNx25W+mhDFl/wwGB kKYT0A8NKZbSocsJlM/17TpXXT9xgD6rnLfltl11vCqJWfGegpNcnEFS9VW4hNe/cB AjEHompWumleA== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:58:01 +0900 Message-Id: <1503737883-14236-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 4/6] ARM: uniphier: remove unneeded NAND config options X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the NAND initialization process is driven by the driver itself. CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 9a64063c3ee6..884e59c35e41 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -83,7 +83,6 @@ #endif #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 2 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_NAND_DENALI_ECC_SIZE 1024 @@ -91,8 +90,6 @@ #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) - #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 From patchwork Sat Aug 26 08:58:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111044 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2174890qge; Sat, 26 Aug 2017 01:58:42 -0700 (PDT) X-Received: by 10.80.181.163 with SMTP id a32mr1143478ede.199.1503737922291; Sat, 26 Aug 2017 01:58:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503737922; cv=none; d=google.com; s=arc-20160816; b=iUlXB65Y3Ojy2/kgIJYt6pYA7+e4rPcYlZ07YGqD6NfT35YEgw9uDo//T4DKQaNDPV DuNTapPTVjHVeaxETYbjgOF1C/b2xHk6FXdm9k6Ey/k7xTdRmm69gHHQky2SyVKXqTNy jUlZqxAjXoPROkTJPtj/elY69fFRvLeB6KNpEZiZjU8HP0VEo7DGq1BdU2dMcPoXVuW6 f+xXtqibmLzc+PCY2eWg04IU3PBAwy0y8kZXgtUAGwpxuhncbeC3Lj5V6Gzr1D2We4T2 SsU4He8tVK34N39c2dndpXC8FDzKTzSogGVTacJe//POS4WZlBTRy0IiEQDxB08NgvVb rK4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=PU55THh9PAQJmFdVWeftpMnhXP3weAS7CAtq2hLRpy8=; b=urpWmtFXg3dY9D5sZS3ZnpAvDovYPNiVKNlrk2qlDR1DKwYpTEt0Fr1//ePRJMwBbl AhrfKOntQ0+NTcu8YPjW3C1GHBxdYdl6KsX85XKNkV/4gUxzANhH9iQ3W/CGalrwUGUE nfqmKdAZhj9tzFljtQBE3HNsaPG5ZLdnkGbtqFvQApoA1cgwLZbq7jcnRd1FbmDvAvuM ZA26/Tl/oWs5PZg4eXPUiBtiD2q3Pe00/iaYN2qQ5dJlWfZgInN7x3dLISSn98UpLzuZ hrkIQFZLc30nqlgABsnCyXmZkc5SC2k8qiYQuvLw28rjzJ6eDBLD1hvRNhW08vwP8t/h ti7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ns+3o+ie; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id w3si7844078edl.493.2017.08.26.01.58.41; Sat, 26 Aug 2017 01:58:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=ns+3o+ie; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 16246C2209A; Sat, 26 Aug 2017 08:58:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 79672C2206A; Sat, 26 Aug 2017 08:58:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 18581C22074; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 08EB9C22064 for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANQ031195; Sat, 26 Aug 2017 17:58:13 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANQ031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737893; bh=7tN6skltNQQBhxydcwjanpxwklUvjeinVSpaUvv0L7k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ns+3o+iecznRkGJC6kg7p7ZUcUhMOJl6q9Ctb1bu9zAQHiO6j9zs6YMk19IePTDNd aKFG1gPPxQFhQ/SMvf7VlDQtJoVMbzhe3I1dfz5l+TTT1CuwGtU1vJY2tfnTaPs1RC C00gnWUQt4O52AfjSbhZV96+Br93Q/2Qzk31FYMMP9dAgglK1VrwXM1bE5tjUAMIf3 ajS4/a1lsRZDKRE6ZC2F0ovjWKKyNkIJMsxZh6Zy2Avt5AU0/QxLKjFOcVsPp9WaMh tkkvv6eEc3GUJBNCY7xG1fq7TdFbUFD/nvdNJqUoYZmJcUiN4rLULdo5rDfsLTC0jL D11grfoIzF4bQ== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:58:02 +0900 Message-Id: <1503737883-14236-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 5/6] ARM: uniphier: enable CONFIG_NAND_DENALI_DT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Migrate to the DT-based NAND init entry. Signed-off-by: Masahiro Yamada --- configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_pro4_defconfig | 1 + configs/uniphier_pxs2_ld6b_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index be0ae70f1a89..39f80188105e 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -37,6 +37,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y +CONFIG_NAND_DENALI_DT=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 5ba8879af6ae..f4181b164163 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -36,6 +36,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y +CONFIG_NAND_DENALI_DT=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index 22c21548b6d7..a7b517ea8da2 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -37,6 +37,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_MMC_UNIPHIER=y CONFIG_NAND_DENALI=y +CONFIG_NAND_DENALI_DT=y CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y From patchwork Sat Aug 26 08:58:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111045 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2175327qge; Sat, 26 Aug 2017 01:59:17 -0700 (PDT) X-Received: by 10.80.148.77 with SMTP id q13mr1079378eda.296.1503737957847; Sat, 26 Aug 2017 01:59:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503737957; cv=none; d=google.com; s=arc-20160816; b=WCHkJYY0qWYneiCbgpr3AhKsCwixosbww4AS+z9CnnOd36NcVyWoE2FFU8kjSOVTnC RNoOltZ+cEuDVE2irfVh581+7o50nEYYUvadreWu7pLgA4pwrJGh+JeKe5jpyB1GyWHV 9K06wsVZghtZ75OzHfdgBdUQ0UZXGv8SMphXuZ1qhnLwkfae0B56UgNMAo0sZ0dESoTK dwTTY7Et33fqb2qdq5UgWMSs5nw+ReguJj06Y+yjBJatRvWs3QhVst5Pn3fIEaXfd0Az bICsgoBC25PA5ORem254YWLMq4V8oBg7cakpyW+Pr7cPbrl2hPGVPK8FbPr/qMYKMrRs +xnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=p9NlGtH/SymWsDm66gxWl1hFZ8f0Mo+lg4ZsUBDfK50=; b=y1qdbdP/D2w9fD+CG088y0n49H2nlHw3KRRkaguGTxodaSWgdYR+XyD7WDkQlRUEj1 rj6J723x0bMZERggQius9Tml+WCU+K/Cz32ib0J+qX+R3P95uY03bcxZXBYdbVUG/g9+ NkM2GAmXD6yLqWkgiVIIwBWb6p57oEUhyNxT7S/EXrI3DZUm1BKeRkO5R26SjxQT6kBT 0anjvUbqAE3EU9jReM6i6fSKAz6QwLcZVuUAbE61sTtkETsu/6OD5ehZWshfG3zBwq9J a37+sjTmb7WR3lFcOo+ea+Dha5ZnYHdsZ7nY12l0a1W1TVaSfZqfv/M35dpH5VlRMvGk 2J0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=tU7SlU6J; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id e13si4553923edd.17.2017.08.26.01.59.17; Sat, 26 Aug 2017 01:59:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=tU7SlU6J; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 555E5C22073; Sat, 26 Aug 2017 08:58:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 35354C22079; Sat, 26 Aug 2017 08:58:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 22DB2C22064; Sat, 26 Aug 2017 08:58:35 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 0E6ABC2206A for ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7Q8wANR031195; Sat, 26 Aug 2017 17:58:13 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANR031195 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503737894; bh=QflOtGhSTNcYvJWWLvuybAYYcFLJprDDZt2w7WBQf0Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tU7SlU6J58/JCk1cWE6SkxK8IobVgPR0PB11i8ox0WUTm/G0Zr1/af/dXL/wxcObg Fej4MTE7jupShCqgdk96L3CUV01eYZxUz0yIQuI7DHdDQq+EZn4OgiC7reVih8HObj A1frq9IoeU1HXnAMmrHI2LpTRdDVlKCr6QPggHbHYK2/H1MXKDFlNsYknSlDKddK75 qQtWwqIoOv+TYxNK+5mBdms35qdQgEilOnyA9pQafzivqIZBuZaJu5OYm9lZVlcbHQ DMKFwyh2+6SOula3ybiy7K3aBbqJMTUvm6oGg1vkXXGy461FslAk5bD2Mp4NLVqNbj cXGIGtbX4hbPw== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 17:58:03 +0900 Message-Id: <1503737883-14236-7-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> References: <1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 6/6] ARM: uniphier: remove ad-hoc pin settings for NAND X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is now set up by the pinctrl driver when the NAND driver is probed. Remove the legacy code. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_init.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index ed58d07f7e50..9c0bed0b8b26 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -78,7 +78,6 @@ static void uniphier_ld20_misc_init(void) struct uniphier_initdata { unsigned int soc_id; - bool nand_2cs; void (*sbc_init)(void); void (*pll_init)(void); void (*clk_init)(void); @@ -89,7 +88,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD4) { .soc_id = UNIPHIER_LD4_ID, - .nand_2cs = true, .sbc_init = uniphier_ld4_sbc_init, .pll_init = uniphier_ld4_pll_init, .clk_init = uniphier_ld4_clk_init, @@ -98,7 +96,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PRO4) { .soc_id = UNIPHIER_PRO4_ID, - .nand_2cs = false, .sbc_init = uniphier_sbc_init_savepin, .pll_init = uniphier_pro4_pll_init, .clk_init = uniphier_pro4_clk_init, @@ -107,7 +104,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_SLD8) { .soc_id = UNIPHIER_SLD8_ID, - .nand_2cs = true, .sbc_init = uniphier_ld4_sbc_init, .pll_init = uniphier_ld4_pll_init, .clk_init = uniphier_ld4_clk_init, @@ -116,7 +112,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PRO5) { .soc_id = UNIPHIER_PRO5_ID, - .nand_2cs = true, .sbc_init = uniphier_sbc_init_savepin, .clk_init = uniphier_pro5_clk_init, }, @@ -124,7 +119,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS2) { .soc_id = UNIPHIER_PXS2_ID, - .nand_2cs = true, .sbc_init = uniphier_pxs2_sbc_init, .clk_init = uniphier_pxs2_clk_init, }, @@ -132,7 +126,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { .soc_id = UNIPHIER_LD6B_ID, - .nand_2cs = true, .sbc_init = uniphier_pxs2_sbc_init, .clk_init = uniphier_pxs2_clk_init, }, @@ -140,7 +133,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) { .soc_id = UNIPHIER_LD11_ID, - .nand_2cs = false, .sbc_init = uniphier_ld11_sbc_init, .pll_init = uniphier_ld11_pll_init, .clk_init = uniphier_ld11_clk_init, @@ -150,7 +142,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD20) { .soc_id = UNIPHIER_LD20_ID, - .nand_2cs = false, .sbc_init = uniphier_ld11_sbc_init, .pll_init = uniphier_ld20_pll_init, .clk_init = uniphier_ld20_clk_init, @@ -160,7 +151,6 @@ static const struct uniphier_initdata uniphier_initdata[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) { .soc_id = UNIPHIER_PXS3_ID, - .nand_2cs = false, .sbc_init = uniphier_pxs2_sbc_init, .pll_init = uniphier_pxs3_pll_init, .clk_init = uniphier_pxs3_clk_init, @@ -188,33 +178,24 @@ int board_init(void) led_puts("U0"); - if (IS_ENABLED(CONFIG_NAND_DENALI)) { - ret = uniphier_pin_init(initdata->nand_2cs ? - "nand2cs_grp" : "nand_grp"); - if (ret) - pr_err("failed to init NAND pins\n"); - } - - led_puts("U1"); - if (initdata->pll_init) initdata->pll_init(); - led_puts("U2"); + led_puts("U1"); if (initdata->clk_init) initdata->clk_init(); - led_puts("U3"); + led_puts("U2"); if (initdata->misc_init) initdata->misc_init(); - led_puts("U4"); + led_puts("U3"); uniphier_setup_xirq(); - led_puts("U5"); + led_puts("U4"); support_card_late_init();