From patchwork Thu Jan 16 00:56:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 205653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28F69C32771 for ; Thu, 16 Jan 2020 00:57:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B1232467E for ; Thu, 16 Jan 2020 00:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729702AbgAPA5O (ORCPT ); Wed, 15 Jan 2020 19:57:14 -0500 Received: from foss.arm.com ([217.140.110.172]:43790 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729673AbgAPA5O (ORCPT ); Wed, 15 Jan 2020 19:57:14 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CFF761007; Wed, 15 Jan 2020 16:57:13 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4E8113F718; Wed, 15 Jan 2020 16:57:12 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: linux-spi@vger.kernel.org, Mark Brown , Icenowy Zheng , Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, devicetree@vger.kernel.org Subject: [PATCH v2 1/3] arm64: dts: sun50i: H6: Add SPI controllers nodes and pinmuxes Date: Thu, 16 Jan 2020 00:56:52 +0000 Message-Id: <20200116005654.27672-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200116005654.27672-1-andre.przywara@arm.com> References: <20200116005654.27672-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, but with the added capability of 3-wire and 4-wire operation modes. For now the driver does not support those, but the SPI registers are fully backwards-compatible, just adding bits and registers which were formerly reserved. So we can use the existing driver in "legacy" SPI modes, for instance to access the SPI NOR flash soldered on the PineH64 board. We use an H6 specific compatible string in addition to the existing H3 string, so when the driver later gains QSPI support, it should work automatically without any DT changes. Tested by accessing the SPI flash on a Pine H64 board (SPI0), also connecting another SPI flash to the SPI1 header pins. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 3329283e38ab..41b58ffa8596 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -338,6 +338,31 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC3"; + function = "spi0"; + }; + + /* pin shared with MMC2-CMD (eMMC) */ + /omit-if-no-ref/ + spi0_cs_pin: spi0-cs-pin { + pins = "PC5"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PH4", "PH5", "PH6"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs_pin: spi1-cs-pin { + pins = "PH3"; + function = "spi1"; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PH7"; function = "spdif"; @@ -504,6 +529,36 @@ #size-cells = <0>; }; + spi0: spi@5010000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05010000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@5011000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05011000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; From patchwork Thu Jan 16 00:56:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 205652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 835F9C32771 for ; Thu, 16 Jan 2020 00:57:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5913C2467A for ; Thu, 16 Jan 2020 00:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729858AbgAPA5S (ORCPT ); Wed, 15 Jan 2020 19:57:18 -0500 Received: from foss.arm.com ([217.140.110.172]:43822 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726310AbgAPA5R (ORCPT ); Wed, 15 Jan 2020 19:57:17 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 587F41396; Wed, 15 Jan 2020 16:57:17 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CAA5F3F718; Wed, 15 Jan 2020 16:57:15 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai Cc: linux-spi@vger.kernel.org, Mark Brown , Icenowy Zheng , Mark Rutland , Rob Herring , linux-arm-kernel@lists.infradead.org, linux-sunxi@googlegroups.com, devicetree@vger.kernel.org Subject: [PATCH v2 3/3] dt-bindings: spi: sunxi: Document new compatible strings Date: Thu, 16 Jan 2020 00:56:54 +0000 Message-Id: <20200116005654.27672-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200116005654.27672-1-andre.przywara@arm.com> References: <20200116005654.27672-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Allwinner H6 SPI controller has advanced features over the H3 version, but remains compatible with it. Document the usual "specific", "fallback" compatible string pair. Also add the R40 version while at it. Signed-off-by: Andre Przywara --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index f36c46d236d7..c19dfbe42d90 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -18,9 +18,15 @@ properties: "#size-cells": true compatible: - enum: - - allwinner,sun6i-a31-spi - - allwinner,sun8i-h3-spi + oneOf: + - const: allwinner,sun6i-a31-spi + - const: allwinner,sun8i-h3-spi + - items: + - const: allwinner,sun8i-r40-spi + - const: allwinner,sun8i-h3-spi + - items: + - const: allwinner,sun50i-h6-spi + - const: allwinner,sun8i-h3-spi reg: maxItems: 1