From patchwork Tue Aug 29 09:34:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111201 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1061414qge; Tue, 29 Aug 2017 02:35:58 -0700 (PDT) X-Received: by 10.98.205.1 with SMTP id o1mr3509534pfg.116.1503999358779; Tue, 29 Aug 2017 02:35:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999358; cv=none; d=google.com; s=arc-20160816; b=DLjb6bGrJH+l5DCBL/POAhAhgIYHqcDlJJRuBgMe1KYCdWkqWqmQwiNQ4yWkLbO1qd qe0o07bIL6Ez3vqO8jH4xpi/yV0Y4803tLMaLC8XssV/YSbEABJ2YjSmNSVd+WTtdNbF +/aZdbu9yupaAba6yAGn8scG2NbrgGXbmjHoLvD2wNtpYepONRQWsLutKgq0iv9oSLf8 v/K2+10ifvCqQzmrJVgGJ80ZkgiMVGhWvJKuo+IvPu+YplH3X9YwQnEdSQz1SXkE7B0k h4u7Ha8Plz63U+4tcDCOxX9x9w7lesz4oVnBGC030nRKoz47y9XCrnGsPBtInnLw7Lj3 IdzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=rBku61CsbHrdE21oKXSrwh6LJpkkFzAAvkadjAT5GKQ=; b=w39ftWfsqWgYiGzDfFHJeBZH761JhKiWYQ8iFNMsq1qcFSiDeiIQ8vq4Y1Pe8HGxQ+ xaLZUq/9crcnjQ03rm5zxa/hPFZEK3qI/7FjYS2CZgom9KvRw7tFErgjeB9J4bqsSxsC dy6npNPzSxVRJWNuIDi8znFOo3Asuqrhot1u49lIcZ/7rxAw+CY5jujv8WaYfYgUZrJc smzN+RG9Haw5o1lCYMYsQZBF1M/YAzHNwLQdFbS6tD671T69tmuGal2rIR9PNJjLXQUG 54Y0SovXpH7pT/SW5vPuiu0no09ohpRqYrj0PKqbRjMPMOmZr+k82vErDqG5xGS39O9h 3LmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OGPeB1A6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j61si654167plb.534.2017.08.29.02.35.58; Tue, 29 Aug 2017 02:35:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OGPeB1A6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752107AbdH2Jfz (ORCPT + 26 others); Tue, 29 Aug 2017 05:35:55 -0400 Received: from mail-wm0-f54.google.com ([74.125.82.54]:36427 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751250AbdH2Jfv (ORCPT ); Tue, 29 Aug 2017 05:35:51 -0400 Received: by mail-wm0-f54.google.com with SMTP id b82so16996304wmd.1 for ; Tue, 29 Aug 2017 02:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rBku61CsbHrdE21oKXSrwh6LJpkkFzAAvkadjAT5GKQ=; b=OGPeB1A6s8BN/A6gPqvA7tTrHErD83rlDOXSaaOc8hVLG4vj29o1q/FVlRvOymHPJn bX/cI2qNmd+urmbikOpDeXXL8D2v7JLkBiqwgs7d4ftxuj3FEN3Bo6Zp/0IaczyB5OlA QNseb8meiSU0VKePr8LEzSPR5ddGbp+H5uW9E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rBku61CsbHrdE21oKXSrwh6LJpkkFzAAvkadjAT5GKQ=; b=NxS9EsxoovUx/x1MxZfsZZfUJaDmBa6tVit097idsz+PgTjbAKM1yTrS2HsYOsSnBH sFEBa0KKmuW1nCWF8Dl1IdjVcDvZVDFDkwUYHFpmzD89JkliDLXs/1ah+iPuPqTXFuss H8OYol45TlqBVk24LHr8PlpCE138ECtQXjoTE9gxDEkuI9XDy1Xi/Qkws5j1n1YL7Qs/ /dMqPM8sPuxbZlr6czMhvaG5rcNl3j6voRbEb0iBILvnz94Ik0WDX0JazSsNUwh2bPhx /Om1Ivjg5QEcXdtAmBIVYUyRlIQHIfmHEHWW9i2bUs2YlnMIIydOlirBfEVtyZI0CsLw Zipw== X-Gm-Message-State: AHYfb5jSmiJqiNXeoqhR8zFjjITfehWl39AYVlbd/9iUyRuCw9OFJ8pY aZddUL4xJRE1fMO+ X-Received: by 10.28.149.137 with SMTP id x131mr827184wmd.53.1503999350055; Tue, 29 Aug 2017 02:35:50 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:49 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dong Aisheng , Arnd Bergmann , Shawn Guo , Anson Huang , Bai Ping Subject: [PATCH 2/9] clocksource/drivers/imx-tpm: Add imx tpm timer support Date: Tue, 29 Aug 2017 11:34:20 +0200 Message-Id: <1503999271-15712-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dong Aisheng IMX Timer/PWM Module (TPM) supports both timer and pwm function while this patch only adds the timer support. PWM would be added later. The TPM counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes. NOTE: We observed in a very small probability, the bus fabric contention between GPU and A7 may results a few cycles delay of writing CNT registers which may cause the min_delta event got missed, so we need add a ETIME check here in case it happened. Cc: Daniel Lezcano Cc: Arnd Bergmann Cc: Thomas Gleixner Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-imx-tpm.c | 239 ++++++++++++++++++++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 drivers/clocksource/timer-imx-tpm.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index fcae5ca..0a953fc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -598,6 +598,14 @@ config CLKSRC_IMX_GPT depends on ARM && CLKDEV_LOOKUP select CLKSRC_MMIO +config CLKSRC_IMX_TPM + bool "Clocksource using i.MX TPM" if COMPILE_TEST + depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + help + Enable this option to use IMX Timer/PWM Module (TPM) timer as + clocksource. + config CLKSRC_ST_LPC bool "Low power clocksource found in the LPC" if COMPILE_TEST select TIMER_OF if OF diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 6df9494..dbc1ad1 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o +obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o obj-$(CONFIG_H8300_TMR8) += h8300_timer8.o obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c new file mode 100644 index 0000000..21bffdc --- /dev/null +++ b/drivers/clocksource/timer-imx-tpm.c @@ -0,0 +1,239 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define TPM_SC 0x10 +#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3) +#define TPM_SC_CMOD_DIV_DEFAULT 0x3 +#define TPM_CNT 0x14 +#define TPM_MOD 0x18 +#define TPM_STATUS 0x1c +#define TPM_STATUS_CH0F BIT(0) +#define TPM_C0SC 0x20 +#define TPM_C0SC_CHIE BIT(6) +#define TPM_C0SC_MODE_SHIFT 2 +#define TPM_C0SC_MODE_MASK 0x3c +#define TPM_C0SC_MODE_SW_COMPARE 0x4 +#define TPM_C0V 0x24 + +static void __iomem *timer_base; +static struct clock_event_device clockevent_tpm; + +static inline void tpm_timer_disable(void) +{ + unsigned int val; + + /* channel disable */ + val = readl(timer_base + TPM_C0SC); + val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE); + writel(val, timer_base + TPM_C0SC); +} + +static inline void tpm_timer_enable(void) +{ + unsigned int val; + + /* channel enabled in sw compare mode */ + val = readl(timer_base + TPM_C0SC); + val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) | + TPM_C0SC_CHIE; + writel(val, timer_base + TPM_C0SC); +} + +static inline void tpm_irq_acknowledge(void) +{ + writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS); +} + +static struct delay_timer tpm_delay_timer; + +static inline unsigned long tpm_read_counter(void) +{ + return readl(timer_base + TPM_CNT); +} + +static unsigned long tpm_read_current_timer(void) +{ + return tpm_read_counter(); +} + +static u64 notrace tpm_read_sched_clock(void) +{ + return tpm_read_counter(); +} + +static int __init tpm_clocksource_init(unsigned long rate) +{ + tpm_delay_timer.read_current_timer = &tpm_read_current_timer; + tpm_delay_timer.freq = rate; + register_current_timer_delay(&tpm_delay_timer); + + sched_clock_register(tpm_read_sched_clock, 32, rate); + + return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", + rate, 200, 32, clocksource_mmio_readl_up); +} + +static int tpm_set_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned long next, now; + + next = tpm_read_counter(); + next += delta; + writel(next, timer_base + TPM_C0V); + now = tpm_read_counter(); + + /* + * NOTE: We observed in a very small probability, the bus fabric + * contention between GPU and A7 may results a few cycles delay + * of writing CNT registers which may cause the min_delta event got + * missed, so we need add a ETIME check here in case it happened. + */ + return (int)((next - now) <= 0) ? -ETIME : 0; +} + +static int tpm_set_state_oneshot(struct clock_event_device *evt) +{ + tpm_timer_enable(); + + return 0; +} + +static int tpm_set_state_shutdown(struct clock_event_device *evt) +{ + tpm_timer_disable(); + + return 0; +} + +static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + tpm_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct clock_event_device clockevent_tpm = { + .name = "i.MX7ULP TPM Timer", + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_oneshot = tpm_set_state_oneshot, + .set_next_event = tpm_set_next_event, + .set_state_shutdown = tpm_set_state_shutdown, + .rating = 200, +}; + +static int __init tpm_clockevent_init(unsigned long rate, int irq) +{ + int ret; + + ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, + "i.MX7ULP TPM Timer", &clockevent_tpm); + + clockevent_tpm.cpumask = cpumask_of(0); + clockevent_tpm.irq = irq; + clockevents_config_and_register(&clockevent_tpm, + rate, 300, 0xfffffffe); + + return ret; +} + +static int __init tpm_timer_init(struct device_node *np) +{ + struct clk *ipg, *per; + int irq, ret; + u32 rate; + + timer_base = of_iomap(np, 0); + if (!timer_base) { + pr_err("tpm: failed to get base address\n"); + return -ENXIO; + } + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + pr_err("tpm: failed to get irq\n"); + ret = -ENOENT; + goto err_iomap; + } + + ipg = of_clk_get_by_name(np, "ipg"); + per = of_clk_get_by_name(np, "per"); + if (IS_ERR(ipg) || IS_ERR(per)) { + pr_err("tpm: failed to get igp or per clk\n"); + ret = -ENODEV; + goto err_clk_get; + } + + /* enable clk before accessing registers */ + ret = clk_prepare_enable(ipg); + if (ret) { + pr_err("tpm: ipg clock enable failed (%d)\n", ret); + goto err_clk_get; + } + + ret = clk_prepare_enable(per); + if (ret) { + pr_err("tpm: per clock enable failed (%d)\n", ret); + goto err_per_clk_enable; + } + + /* + * Initialize tpm module to a known state + * 1) Counter disabled + * 2) TPM counter operates in up counting mode + * 3) Timer Overflow Interrupt disabled + * 4) Channel0 disabled + * 5) DMA transfers disabled + */ + writel(0, timer_base + TPM_SC); + writel(0, timer_base + TPM_CNT); + writel(0, timer_base + TPM_C0SC); + + /* increase per cnt, div 8 by default */ + writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT, + timer_base + TPM_SC); + + /* set MOD register to maximum for free running mode */ + writel(0xffffffff, timer_base + TPM_MOD); + + rate = clk_get_rate(per) >> 3; + ret = tpm_clocksource_init(rate); + if (ret) + goto err_per_clk_enable; + + ret = tpm_clockevent_init(rate, irq); + if (ret) + goto err_per_clk_enable; + + return 0; + +err_per_clk_enable: + clk_disable_unprepare(ipg); +err_clk_get: + clk_put(per); + clk_put(ipg); +err_iomap: + iounmap(timer_base); + return ret; +} +TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init); From patchwork Tue Aug 29 09:34:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111208 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1063050qge; Tue, 29 Aug 2017 02:37:35 -0700 (PDT) X-Received: by 10.84.229.77 with SMTP id d13mr321079pln.235.1503999455099; Tue, 29 Aug 2017 02:37:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999455; cv=none; d=google.com; s=arc-20160816; b=ON2wRr912+zPF0nnIBdz2m/qu9p7c2doTCZB0W2MSJzq8TJ4d4L6iNnMmz5aZN8S/Y zVcaIALTtH5uUtpnIV5PJe8Hs/aWZr+AItGtYaaJw0OEWUbcO/hPOzTV5AAsOACCLOV0 l9oDosqxJ4lHshVWxFpQjy8jPwCSCMCVHpLdIOBRa9NT+02U8iU4XSMZwnXPh6ades8l y2POOkrWqCUknJe49TJMMOt/zPNYdvx56YxFmuKbn2K8XDa+SfS9sEeqyOPCYYRRRnEb p/w1m8tmvgE5E+cybECyuF0tfJ1nBkrq0zrDgKSfVP+m6O58t+DbMo7NxQhz25NcE1MD 9AaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Y6Y6j4jy3nNhVyt5YIu01w/u7A536PqHwLjICFwSg2A=; b=mB9NJ2n4Ig3rODhkEimNkOlW+150sfSH1/lvH1mHfMm1PPGiAqlsytqK9iKRm/ZlPL dUQxb7s0zi5EcsUqd2BL0DEo43pUF99LyfBBuDkRD0K3PU78NvDup5o7KdZzxDlIdDNH fgROb+taXDQZ1Kw9oHmFQgCkL+6O2ojyvP/jX3x9CA1880Py5cClF1BrbGpHMvmOr5k7 hFgbMKYlSg0pjU9HohQaMqFGzza6X6U66KgP+ymO5mqEbvU1o4FSKQFKlogxITCZQgGL uzXL99Rh808H0iJXEXc9mDo7lbPI6CGOztD55VpVOILah8ESn0WWWxJDtd+4PHzY4qYC NS0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Psuv/Pof; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i5si2014164pgf.424.2017.08.29.02.37.34; Tue, 29 Aug 2017 02:37:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Psuv/Pof; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752320AbdH2Jhc (ORCPT + 26 others); Tue, 29 Aug 2017 05:37:32 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:37163 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752082AbdH2Jfy (ORCPT ); Tue, 29 Aug 2017 05:35:54 -0400 Received: by mail-wm0-f46.google.com with SMTP id u26so18642132wma.0 for ; Tue, 29 Aug 2017 02:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y6Y6j4jy3nNhVyt5YIu01w/u7A536PqHwLjICFwSg2A=; b=Psuv/Pofzt1Fj9kwLurAjBgheRcJ/o8m/RTKTaVSng6pbAQnMpgjD8e2wPYX7yhkoz CO18OOBqp/4Qf8YXvIrpCY1/LSXit/FV81aRd6r1X07HIp4y++3n7OAznZC8Suv7tYS+ oQHJIUSzHFFpiutzmGDcopQDstRkHWlnfVS8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y6Y6j4jy3nNhVyt5YIu01w/u7A536PqHwLjICFwSg2A=; b=OEDZIqmAdlrLNzgCwHK6ngNcEt8o+DwRXTTw+5B9nHdaQD7vu/6IxBtB4KLeAjkoAc RJrPY10+ccMALD2ZpgHbVNufGtLjbFJAOaAYXielFHPKpcuRn1wuX9xDbCtZWkHZB/zh gqYRVrFp52jaXVwmemT3Ez7tiAQKkAgEgY0OiZ5qGzpQBG2WMWaDVbrH898vg5CuJqyN aTiKcvr6oE60vsOOeCEtc/Gocqz54pQYHz8j7KgNjMOLn4nTLI6wHG3fCRvTDwwr05DA KfeWTF3g9kqAlZTihs3B9lHfxrw9SEntS4WkNroSMxOwPtvHvAHB1z3XSXTcsyOvrpY9 GXUA== X-Gm-Message-State: AHYfb5jfhC6CVBoXaJ3rrWrsuq4fxbKLzVFRhgMXYSGDoOtW7KbFMO7l eTamqjOg+8h0lCU3 X-Received: by 10.28.232.193 with SMTP id f62mr811681wmi.155.1503999353264; Tue, 29 Aug 2017 02:35:53 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:52 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 3/9] devicetree: bindings: Remove sh7372 CMT binding Date: Tue, 29 Aug 2017 11:34:21 +0200 Message-Id: <1503999271-15712-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Remove the sh7372 CMT compat string to reduce maintenance burden. It should be fine to break DT compatibility because: 1) The sh7372 SoC support has been removed from upstream 2) The sh7372 CMT DT binding was never part of upstream DTS 3) The CMT driver never matches on the sh7372 binding Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Rob Herring Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 1a05c1b..961c0b6 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -14,32 +14,26 @@ Required Properties: - compatible: must contain one or more of the following: - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT (CMT0) - - "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT - (CMT0) - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT (CMT0) - "renesas,cmt-32" for all 32-bit CMT without fast clock support - (CMT0 on sh7372, sh73a0 and r8a7740) + (CMT0 on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-32-* entries. - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast clock support (CMT[234]) - - "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast - clock support (CMT[234]) - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast clock support (CMT[234]) - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support - (CMT[234] on sh7372, sh73a0 and r8a7740) + (CMT[234] on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-32-fast-* entries. - - "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT - (CMT1) - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT (CMT1) - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT (CMT1) - "renesas,cmt-48" for all non-second generation 48-bit CMT - (CMT1 on sh7372, sh73a0 and r8a7740) + (CMT1 on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-48-* entries. - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT From patchwork Tue Aug 29 09:34:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111202 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1061537qge; Tue, 29 Aug 2017 02:36:06 -0700 (PDT) X-Received: by 10.84.178.129 with SMTP id z1mr359986plb.72.1503999366736; Tue, 29 Aug 2017 02:36:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999366; cv=none; d=google.com; s=arc-20160816; b=xXzA8khxYG0Mfx4ox1tXfOMlwzOx6267nl5UQPP1DIyw8atlctmSUCI7LgpWmsh+ES ZDGHJWntBW62wW1nb+E/JJnHTMLKsRdOYbDNs4X1mKRThVAc2KkWJAeCajV/70A5Dy2f FHkmDFIs5mEKIPLx0ttGPaVAOWrbh/WwPyqvW6rhioOr3fO4mNtItH9WGYZw4r0cBkGM V7pJDPOhxbCYxXxE8ovhIBsRZerSRGkEkVoRPobG/kyvuf95gcm31x8J1wFpjEx9BSj0 etGfQqg+Anl/qcDY//UBxXR6VWcvMmptX51HEYARgcUKo/yHHv+Eomlmd5STl0zsXKl6 oPjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=sD6Ek8VniU8pKen2r9FZBpm+8IjMEt7E0uNsDwvzI5U=; b=rtH6ke/EQr36hbLVeEE0miBSAmySVQ0f876wsy8BIdvwAxhZyBzc6exk9hd8VicW+H 4+1zMrPYL4EN3c69OQBj9pj7sZLrss5/bhSu05lN13n17yxmvfBlFZAqMmp5NnUo9nKx oCbZgPtxqyIMkmBDDwkWcF7EAkZn28iP31uDO3ypPdvaFhF/TaXIRtjO74hDnnZwO4nl 6soJiufDBiWhhOKnxL1zCnUaX6jFG71SHvHxAohGhDEs7TGwb+E46nRJE/INncbMllt8 bb4CE/94z2MHJ/As6elV7HnOBUfNTE+UyKlGwzkxXtLy/J6dh45sR/UWMAmRU8IxRCti lf6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QK5U+oNz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j61si654167plb.534.2017.08.29.02.36.06; Tue, 29 Aug 2017 02:36:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QK5U+oNz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752131AbdH2JgC (ORCPT + 26 others); Tue, 29 Aug 2017 05:36:02 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:35833 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751250AbdH2Jf5 (ORCPT ); Tue, 29 Aug 2017 05:35:57 -0400 Received: by mail-wm0-f43.google.com with SMTP id y71so17215535wmd.0 for ; Tue, 29 Aug 2017 02:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sD6Ek8VniU8pKen2r9FZBpm+8IjMEt7E0uNsDwvzI5U=; b=QK5U+oNzzrNNffGtDml7LNxfsypxD3j53WZECk2Nw4cM6RvMhkQJeHcMTRBIyvJlrf wAZw3TJES201XtjGFcSFAyXt7R69sWO9ZLgteBroW513c9EJmpw6R2MKs2ZkDSHPFRYW 6iyTEd9gzQBNxRz6lBdNGhtDOO3gcHUGd6Oqs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sD6Ek8VniU8pKen2r9FZBpm+8IjMEt7E0uNsDwvzI5U=; b=QWVGREkDqNG5Eot0rmg2JxYLXZiQrx8Qb/p+XVtEJdmBh/EFyDkpDDFXoYh36n18Ax 00Oquf6bKmim6+ISY4b+IVOmjEv5DCXWPHNIZLsE0knEkFWjqLvHXPzlcPti+Lv7HHr2 8Rf5VCsF6q/9SiihnAiyDI7sZnsiHbyuP+0Itqk2ggoBuE+e1Ll6/o/n88dhKisBo3Aj 9ck3wdxVlq8syC4K1j22/cbxjcZPjw2uh+zpqAcqOcbsLSgZuhJNm7G4HOmuX41PyxE5 DZvvzWasFVxNCbYqWK7EszjLMb9IQPx1pr6BFlHsg1hCP0eTIZDa6GA03CQG3eE6kTE3 8a9w== X-Gm-Message-State: AHYfb5iAMCL+8HCPxiiUA++gaUGsGRHPVl61+wXxJG1A/vMolhO8Scnn KCyHoFCEu9JIuO34 X-Received: by 10.28.94.84 with SMTP id s81mr1885533wmb.3.1503999356320; Tue, 29 Aug 2017 02:35:56 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:55 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 4/9] devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings Date: Tue, 29 Aug 2017 11:34:22 +0200 Message-Id: <1503999271-15712-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Add documentation for new separate CMT0 and CMT1 DT compatible strings for R-Car Gen2. These compat strings allow us to enable CMT1-specific features in the driver. The old compat strings will be deprecated in the not so distant future. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Rob Herring Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 961c0b6..2583aeb 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -36,6 +36,9 @@ Required Properties: (CMT1 on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-48-* entries. + - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2. + - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2. + - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT (CMT[01]) - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT From patchwork Tue Aug 29 09:34:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111207 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1062703qge; Tue, 29 Aug 2017 02:37:15 -0700 (PDT) X-Received: by 10.84.217.11 with SMTP id o11mr325078pli.245.1503999435120; Tue, 29 Aug 2017 02:37:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999435; cv=none; d=google.com; s=arc-20160816; b=0QQ0SeD+0KcDNMDg5OBZ4XCZoILD1v+8GegqcA1Q+Xa2VhM9T0ra+4hkNBoMC6J6Qb Cy4J/LEnjs+sJxp/cGQ/gzvofUUSu4eOV2v3KqO8Uz+QN47zkIncN2hz148oSgPP9mY4 oom3S314V2GroBvlKgnubFXJOplIphLR4Y+FZMeOHo902skLPcD+Y+d51wYcbK40zSXs bdjkJmjsOUVC88SKgiwkQDLzJ5YNioN3jFFXUR+NOEISbLCVnO+9NO54S25ctKTCPz2w 2baNMXHTUfYA9Bdm88ebPcUM7yehhLeMI6ttXDh18AFTFhmkyaThoY+iVD/5zvu5xFAe eEIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tXpsYGXETUHGWAB27CuFQF8nNUMRh/IOVM/Bap36nU8=; b=hIVQFzRqYUAcJT1Gm2dOJMg9vUspr6U83gbDQqC7AopmU7WT27DRyrXYBQRttEJufN BUvoiGpcCtPCeGAAHYbDZDm2UQjzehIMVpVioH/66aVBGS6KuGQosOpQ5S/LuTDtqKq7 mwRUervXaFC0K3MpoagMFZO7t7PslRpiBO56fuLg/hgiG6nNp3S+HERW0eWKoe93rP8W iEqgx3k5O7XiOS1rjzY63miVqrDh3afd+jyZ44mP+GYKEwdkuhPyakOteBI1qyz8YrAl GFNJpEV6o3VhwikOjs03DksLR8sR8le0TZyBh7eJqyRSCXexsy0hmij+BXzXlyYD0xl/ mMCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Abts+BUR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 83si2021065pfy.267.2017.08.29.02.37.14; Tue, 29 Aug 2017 02:37:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Abts+BUR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752283AbdH2JhL (ORCPT + 26 others); Tue, 29 Aug 2017 05:37:11 -0400 Received: from mail-wr0-f170.google.com ([209.85.128.170]:37898 "EHLO mail-wr0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752111AbdH2JgA (ORCPT ); Tue, 29 Aug 2017 05:36:00 -0400 Received: by mail-wr0-f170.google.com with SMTP id 40so7880585wrv.5 for ; Tue, 29 Aug 2017 02:36:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tXpsYGXETUHGWAB27CuFQF8nNUMRh/IOVM/Bap36nU8=; b=Abts+BURDl3k94HpcGeXVPttqD0wQvTyBuZ7GGq6Pn/fJizVQeZeWvdVCmnwijaAUt Z/atfJkdnoORR7S7seAMrQauPYMQbd6jOrS6atvv6ExEHLAzTjekLPaZnaUl4qbr2Pds nKxkFyDPFHO10P5RDy5DhBKNNBPcKQi2QJLWM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tXpsYGXETUHGWAB27CuFQF8nNUMRh/IOVM/Bap36nU8=; b=dC6JrnAZjmls4KJDxQuicp+ddl0w/dPgVOnUtFP9aSqKZunLJnnjAVfgKB+093FNz7 zf01Ep+wgLQ66S9BUfECEoNMC9uXDLi5G21t4uU94ve/73BF5/IELVazRLLwz7JE6H4d EIq41/YD9FgTj2UmwESTjKBNOFCI+PNEYXa9AQnO5GibKA6Z8r4zbohKJTEROEorcr+R Mh7jyD64t9mN6OLAfjAIbtPbqH59avIBzp+SA8FvQyrSHquIJPQPTu6Agl5HXPXLRyqC OzWlmNWpjG46dJ1KY/Ig8CajPrMKcXB4Pck7F/YQXiUCEj+fIMMw1dyyhMNm42hVs/CO xh5w== X-Gm-Message-State: AHYfb5jwL1bOOpZ55+NVO7kMdxrM8WrtyYmPBskxmGzJnhxsOpKkPqaF 6qzb/2uCUfqwyqMH X-Received: by 10.223.174.225 with SMTP id y88mr2111064wrc.7.1503999359364; Tue, 29 Aug 2017 02:35:59 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.35.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:35:58 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Geert Uytterhoeven , Laurent Pinchart , Rob Herring , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 5/9] devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings Date: Tue, 29 Aug 2017 11:34:23 +0200 Message-Id: <1503999271-15712-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Update SoC-specific bindings for r8a73a4 and R-Car Gen2 CMT0 and CMT1. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/renesas,cmt.txt | 24 +++++++++++++--------- 1 file changed, 14 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 2583aeb..e81e0d2 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -36,19 +36,23 @@ Required Properties: (CMT1 on sh73a0 and r8a7740) This is a fallback for the above renesas,cmt-48-* entries. + - "renesas,cmt0-r8a73a4" for the 32-bit CMT0 device included in r8a73a4. + - "renesas,cmt1-r8a73a4" for the 48-bit CMT1 device included in r8a73a4. + - "renesas,cmt0-r8a7790" for the 32-bit CMT0 device included in r8a7790. + - "renesas,cmt1-r8a7790" for the 48-bit CMT1 device included in r8a7790. + - "renesas,cmt0-r8a7791" for the 32-bit CMT0 device included in r8a7791. + - "renesas,cmt1-r8a7791" for the 48-bit CMT1 device included in r8a7791. + - "renesas,cmt0-r8a7793" for the 32-bit CMT0 device included in r8a7793. + - "renesas,cmt1-r8a7793" for the 48-bit CMT1 device included in r8a7793. + - "renesas,cmt0-r8a7794" for the 32-bit CMT0 device included in r8a7794. + - "renesas,cmt1-r8a7794" for the 48-bit CMT1 device included in r8a7794. + - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2. - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2. + These are fallbacks for r8a73a4 and all the R-Car Gen2 + entries listed above. - - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT - (CMT[01]) - - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT - (CMT[01]) - - "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT - (CMT[01]) - - "renesas,cmt-48-gen2" for all second generation 48-bit CMT - (CMT[01] on r8a73a4, r8a7790 and r8a7791) - This is a fallback for the renesas,cmt-48-r8a73a4, - renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. + - "renesas,cmt-48-gen2" is , use "renesas,cmt[01]-*" instead. - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. From patchwork Tue Aug 29 09:34:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111206 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1062259qge; Tue, 29 Aug 2017 02:36:48 -0700 (PDT) X-Received: by 10.99.137.199 with SMTP id v190mr3211330pgd.375.1503999408766; Tue, 29 Aug 2017 02:36:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999408; cv=none; d=google.com; s=arc-20160816; b=Sg07wiMA2O6LganpIYJImqIWqi7rv5jDuiaVbZ9W4NMnzL9VhE67WaI+UpX/Ay13Ab AEixqaIvdSXd3E3qu/wBCr8AtZFQOyuBH/8V3KkAUrjkluseWUiY/FIK0InJ1J+SSB8W cSx4gj3AC6W1doRmyaVwgYAHBTQwzzHWvoWUNBBPAjx0AZ+MkDzcieOJPLwoKAzjG47K 8nKJQc9R917rn0XlygvuQZgpe5o572/19/CsgCuKHbf1zqDXvnF4/F/DdGYE3o27uyO0 ngL8zXuAMzvKX6LiTd+ja7IPmTHlRmqTPQSjGiRoZR3LpJfyIjaclC9ndED9Fdd0DGVV VVbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=z1PUWPN1XeohBeckT3xVJz1vgjbtdzk4NZt6nOthY5w=; b=0TLBdR+cC4F7BygVB73LPx1Ua1yYIM/lfBo8/OG9ItNlwqJdCsWw6C9+70A81FB31Q 8+dqX9mdwvpflbgsCZ+WPbmLXqRpqRhlJx0y0/ojVXeChBLyCJAXS858eFZ2mw9nxpeg 1Pf0TG3yJgfKYvDUxoii9jjBj/GVCBHootYR3L1QtBVIwTiAbV6RKFCHi7SaWtJv2jtE 6DitNx38rRGKA2DDyieMm/lM9KusJs887iSn8g0+0V1+RQC9iilNqwtoLL/V3AHfhGu4 9kPQiReQQm8BVg3TG6Eb+Niheznljkzg6RY0mTFKJffNetAORuQcIJT4CUaWAk+DKBK7 glfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YohQCRUx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e189si2009550pfa.184.2017.08.29.02.36.48; Tue, 29 Aug 2017 02:36:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YohQCRUx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752238AbdH2Jgr (ORCPT + 26 others); Tue, 29 Aug 2017 05:36:47 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:38090 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752139AbdH2JgG (ORCPT ); Tue, 29 Aug 2017 05:36:06 -0400 Received: by mail-wm0-f53.google.com with SMTP id t201so18600830wmt.1 for ; Tue, 29 Aug 2017 02:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z1PUWPN1XeohBeckT3xVJz1vgjbtdzk4NZt6nOthY5w=; b=YohQCRUxTsVtmockxFkDAs3ryrR+7BixgzS+3A9/pKWKVL49D262JOAQVQxXhpqINI OiQ6JMj91m3fArYc3bQGLfoO1OFyFg/6Lo97Y7Gq6rACfiPso77GqTWbcCbYE5wDyC4o LXnbyg68vJmlXtt1EOvdowwB9oSNXh6NA2LBI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z1PUWPN1XeohBeckT3xVJz1vgjbtdzk4NZt6nOthY5w=; b=GSFAIu9M7+k9HvzvHWuWvP7QV9Jkd+OaGb1sjFT/FIYiW88UqWtNvQ+zro0pnL8i7F d2WCIlcLBe75PAzNtyOTYXf3KonYG9UVG4qTr7PuhDq4tW/cq9ibXtvKRN4KdBnIAGy0 pHh0WF4+JOJ/hupImfOthSTrdjM7uke+JzxmqK6p7MONhs4727ZUXTwbrbRUszJUU1qx M1Izb1Jp2J/fpQ5llLDQ8/UazNEZXkUthBx5rYBHmp/SEelE7gxNAxYTS+6ZPUMHgW9K 3o9txDro/rd6nK2KDFRWp55DUnPRS8/9IfW0bop5NdpMPQv1t4HesTeTGYj3YUynAgE9 JKwQ== X-Gm-Message-State: AHYfb5gX1dUNRFCyRJbF7n34XQkzYRPpw/r9nYLb0gqU23/ROI5126cN c2d3pegd/FfkeBES X-Received: by 10.28.138.84 with SMTP id m81mr844355wmd.61.1503999365697; Tue, 29 Aug 2017 02:36:05 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.36.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:36:05 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Rob Herring , Geert Uytterhoeven , Rob Herring , Mark Rutland , Laurent Pinchart , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 7/9] devicetree: bindings: Remove unused 32-bit CMT bindings Date: Tue, 29 Aug 2017 11:34:25 +0200 Message-Id: <1503999271-15712-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm Remove the 32-bit CMT compat strings to reduce maintenance burden. It should be fine to break DT compatibility because the 32-bit CMT DT binding was never part of any upstream DTS file. Signed-off-by: Magnus Damm Acked-by: Rob Herring Acked-by: Geert Uytterhoeven Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 16 ---------------- 1 file changed, 16 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 8fb7c93..d79293a 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -12,22 +12,6 @@ datasheets. Required Properties: - compatible: must contain one or more of the following: - - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT - (CMT0) - - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT - (CMT0) - - "renesas,cmt-32" for all 32-bit CMT without fast clock support - (CMT0 on sh73a0 and r8a7740) - This is a fallback for the above renesas,cmt-32-* entries. - - - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast - clock support (CMT[234]) - - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast - clock support (CMT[234]) - - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support - (CMT[234] on sh73a0 and r8a7740) - This is a fallback for the above renesas,cmt-32-fast-* entries. - - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT (CMT1) - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT From patchwork Tue Aug 29 09:34:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111204 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1061724qge; Tue, 29 Aug 2017 02:36:17 -0700 (PDT) X-Received: by 10.98.103.71 with SMTP id b68mr3299744pfc.333.1503999377617; Tue, 29 Aug 2017 02:36:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999377; cv=none; d=google.com; s=arc-20160816; b=ooTHfpFAG1tOmIZiMU6/kTisgHIZKGMYaIf53/TQmJuPeiNZRNya0N3LbUDcvbMv2t E484JB91ctHg2GO92sbSAL3Ksjwm4LlzoRjPPOa0QcDAYyh/GB1T62Y/VJqBwnes/lY3 7ESLLvRprOFi3AUw6mUcEJ3/Csg8+nysVet3BtBMZhQhz3clcZIhp/tDvt8OiHuK/MpI J9Kzk0lhGas50QP55jo9+CYHJsebo+7SfVjpujEjBPMPhCZaeeji77E1e2E+VjFA0o2M t4GDE+flYh0H5AzIESQCuN5AxglNdjRUfqP4ZqMtvg5x4b62xDZ41R/ff4ehueWHJCY/ txcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=/jgmtQq2svqTRK64yzxtNFRPJlLfJUbkIbeERJ92M1s=; b=cfLtCi/oUkxXMcfochSbR4BjzLJWfMmela2iWGSTyWU6squzbilzKu3AbmnCv/l0nE DW3FYU8CAnJd8rP2I1hggJ6oUOj/yV22SPuUeb61gvclOwjYgzXs4I0h//2hMWNKmIN1 33o3P0XSD89/cTSyhDlbFzU+UQtJcDbAlLCJHcROHaotfrlEqPr+YrVMG89ZZpHrFDw4 3FO+wNJEkuFyut9QO9gfTtKSNBy5N7FXKsu/Oo1HhpIDO+Szss4+GoEZLzyu8CQyUm4z EzvM/24tB+SDSseW6lkWcVAKQysBAR2qrJ5Z+2EnrtYyODRy91h69odUjxqG3jdJ3Qrv Qnrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IxaAKtlh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si2085229plx.822.2017.08.29.02.36.17; Tue, 29 Aug 2017 02:36:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IxaAKtlh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751180AbdH2JgN (ORCPT + 26 others); Tue, 29 Aug 2017 05:36:13 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:38117 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752135AbdH2JgK (ORCPT ); Tue, 29 Aug 2017 05:36:10 -0400 Received: by mail-wm0-f46.google.com with SMTP id t201so18601650wmt.1 for ; Tue, 29 Aug 2017 02:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/jgmtQq2svqTRK64yzxtNFRPJlLfJUbkIbeERJ92M1s=; b=IxaAKtlhpnYdiHk5hNVdy13WGfiE8nnMDAxQFu9/W92WL85tWgkvUHUVNbPhgU1wlV vrPKCCoQKfeQ8WfZQFwk2PS6ivhIRkk4Mgyv99ZVVg5ODWzAAGxOtkwfk2ixAnr9v127 aSL+Jpr2IVeMc/wDJbF/CYBSBQwjVdA4upgUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/jgmtQq2svqTRK64yzxtNFRPJlLfJUbkIbeERJ92M1s=; b=JJXjMyM/snbDYjqCA8n70Fi4RLvemPhMASABFf8Gp0VWj78Eji70nILvvEnpWIQXv1 og+oHmyv85L1CB+DCpsekfX2Vd4FmblZxj+HIJ/8zSYb3mSEli9idMACzJ+wTlzuYEtB umgXeV7zqEPTvrK5ADFURINkz3fdxe5nldjsWNbCgKwYP6q+xMRX+VdF22Gnc2mRTwPZ 2kGvUET0FnUeqSjfIkUlpDQKjid/glNWEiuZ7MY5ITYXuXIluatt1RPSkLyHKeYqDzVb No4fixKxiMklmjDJotYcbM3fZPAAArA+ZpIX1FYfgaYO3su+7eC1n/2IoxnyOtWsch2d 6HBg== X-Gm-Message-State: AHYfb5jGueWSTabRIST9jEZHDg/umPO+H60ULmeWvhL4CMG2bH/zmUD2 QsRmIt5gP9fJ8Fss X-Received: by 10.28.153.11 with SMTP id b11mr886666wme.98.1503999368875; Tue, 29 Aug 2017 02:36:08 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.36.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:36:08 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Magnus Damm , Rob Herring , Geert Uytterhoeven , Rob Herring , Mark Rutland , Laurent Pinchart , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 8/9] devicetree: bindings: Remove deprecated properties Date: Tue, 29 Aug 2017 11:34:26 +0200 Message-Id: <1503999271-15712-8-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Magnus Damm The deprecated DT properties are part of the GIT history, no need to keep them around any longer. Signed-off-by: Magnus Damm Acked-by: Rob Herring Acked-by: Geert Uytterhoeven Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 4 ---- 1 file changed, 4 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index d79293a..6ca6b9e 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -36,16 +36,12 @@ Required Properties: These are fallbacks for r8a73a4 and all the R-Car Gen2 entries listed above. - - "renesas,cmt-48-gen2" is , use "renesas,cmt[01]-*" instead. - - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel. - clocks: a list of phandle + clock-specifier pairs, one for each entry in clock-names. - clock-names: must contain "fck" for the functional clock. - - renesas,channels-mask: , information kept in device driver. - Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes From patchwork Tue Aug 29 09:34:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 111205 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1061976qge; Tue, 29 Aug 2017 02:36:31 -0700 (PDT) X-Received: by 10.98.34.28 with SMTP id i28mr3316358pfi.135.1503999391695; Tue, 29 Aug 2017 02:36:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503999391; cv=none; d=google.com; s=arc-20160816; b=W4UVGMeQkHFBwFasKxEwuIUY/64W4lb04i7yy0LYK5FzYZu/cylGosNp3QuU6y2i5Y nHkQIubRIs8Det32tqH8rKuY+6ytU3/N2HsopinInOSppiZ0ywz2jddpTjOtBM21lu9e zOjhOQU4PAgvokgVF4nBtUWpuc6RgrWFPnXUYzhSZegoTtQH+emY2KNitX5YrM/9Z5rz nvjqAGbU4RYsP/EFAQKiJ0dXI2x7s1GzguUKsxmaiBGaI+k9iP221oUM61uj1ZDW+DKk GCcg5FVuCaCcpsgoEDennFJaBQTpK91nS6iocFMoxTLe1OnGGc4lIa7t6ohsDgMmnw9F tPdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5icsjUkWTCP2G8LcGra3SEyc0qKFAE2aeiMQy/Om83o=; b=snAnutK0d7LoSKuW/4fHBGcxa2U+hipVNJoNd30T7w8jqb0tsG0zKAE+eGGp5SFRnx V/KP+nxZTN2vCpwkxZit1lXvm+0iK6NeYhiSvvcQMEGjP99Gj9hzxG1Oqcc80G0qjbj9 +xocjdt51Dwi7EUiOlWTUu0DEtgHLr+DsVbS7NTKrTnbImdG00vluGx4gpl8jfPSzCRb VC6Mz1dgPIHbDwIdvSPcUBrXLy5fNRVmTJQvPNlU+a8HBsaFqtCLy3rVIKo1m0UegPXK B532lDXbVnQNUVSn7bSi1SqZcxDiPfug0DzjgtvpO4Bh/Xc+m5yhTnt9uBPk+amfnhTv WY4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sr4CpFl8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e189si2009550pfa.184.2017.08.29.02.36.31; Tue, 29 Aug 2017 02:36:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sr4CpFl8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752206AbdH2Jg3 (ORCPT + 26 others); Tue, 29 Aug 2017 05:36:29 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:37308 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752163AbdH2JgL (ORCPT ); Tue, 29 Aug 2017 05:36:11 -0400 Received: by mail-wm0-f44.google.com with SMTP id u26so18646646wma.0 for ; Tue, 29 Aug 2017 02:36:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5icsjUkWTCP2G8LcGra3SEyc0qKFAE2aeiMQy/Om83o=; b=Sr4CpFl8q0nx+8Arikocvj3Hh4bzH/6YeKOvW3CHlggZJX5Cpfmth4zvJdDg0Pq0nD mMOYlNnJisqrlDCd6yEl3FJIwoQs1lLOjMLeuWRIVgSeXt8pKv7M7L2lTV77BEjcPkBs V0nobJXwc2P8FfBOt10C4WeVAisthnNA5JIoo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5icsjUkWTCP2G8LcGra3SEyc0qKFAE2aeiMQy/Om83o=; b=WjZK69uNLNCOpHYhLNm+d01zrbexnlTjlyuXkuS6UcVEDLjb5y9jgFWYyyl4LZfecY ZfDiAWRW+pjkOzwKEsZYIKT9Ceht+OKwsuhZfvj9bNUWPlV/OvilVOxPqy/ZYgd5JD3B ZTR1l0FSXSoIFr72hEGTxOiDQ7rB5y769WUCHEVA9AkppflWdQngFTukjYcp8wN7vuXj FfEsoCvLhwmhROaAZHE2uS9bvFujtgFbm5kiMFyyuE8DyHkX6OzcFYtpJd0/EaxSBjFR PVhUmo/9o/gvc30QzlnELO939OL3QZvbI7aCLjpZUDBlRWH7ts+AjJjj71bOAEnzXqWV JpZg== X-Gm-Message-State: AHYfb5gAEaT9I0ZKnUbKpduy5mi+P4RAbcxrkl4P6M5zeXTdfT7juAxY b1uD8M+GielH+ah8 X-Received: by 10.28.187.4 with SMTP id l4mr1916204wmf.168.1503999370653; Tue, 29 Aug 2017 02:36:10 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf]) by smtp.gmail.com with ESMTPSA id r18sm3621775wrc.44.2017.08.29.02.36.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 02:36:10 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Markus Elfring , Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...), Eric Anholt , Stefan Wahren , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2835 ARM ARCHITECTURE) Subject: [PATCH 9/9] clocksource/drivers/bcm2835: Remove message on memory allocation failure Date: Tue, 29 Aug 2017 11:34:27 +0200 Message-Id: <1503999271-15712-9-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> References: <20170829093354.GA2572@mai> <1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Markus Elfring The bcm2835_timer_init() function emits an error message in case of a memory allocation failure. This is pointless as the mm core already do that. Remove this message. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring Signed-off-by: Daniel Lezcano --- drivers/clocksource/bcm2835_timer.c | 1 - 1 file changed, 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c index 82828d3..39e489a 100644 --- a/drivers/clocksource/bcm2835_timer.c +++ b/drivers/clocksource/bcm2835_timer.c @@ -114,7 +114,6 @@ static int __init bcm2835_timer_init(struct device_node *node) timer = kzalloc(sizeof(*timer), GFP_KERNEL); if (!timer) { - pr_err("Can't allocate timer struct\n"); ret = -ENOMEM; goto err_iounmap; }