From patchwork Wed Aug 30 14:41:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dietmar Eggemann X-Patchwork-Id: 111318 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1040363qge; Wed, 30 Aug 2017 07:42:30 -0700 (PDT) X-Received: by 10.84.238.138 with SMTP id v10mr2243239plk.185.1504104150704; Wed, 30 Aug 2017 07:42:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504104150; cv=none; d=google.com; s=arc-20160816; b=e1dATJsoM6KEYFOg0XYQ1WNegW2GK/seJdBQdwvoJ5c9t8JkdDe1m401Q+PH1Pt6o5 W+jf0qCmYc3sTxxpn3IHr9DJmADj/B4+/zZcpfMqkXalSxtN9cd3FpgCcJGbt3h1vDjc PTJndDT/ruQ1h/Fa/4gesluelezHheNXvi4hV8/+xmSHjxe7ZqY6W/DuwdrFOaWqEe5a yKcefEE2AKKDIBzwNjDcTYD0SDBjt+q1YCNrEO9dV0HUvPYymX4jzgjZYUkF3Md6ekCF 7DyguFxgKOk48L0qwfITK+bpvzepJZQn9dm7PSN6Ox/38vfOlcwNxaq3pzZousV7yRc1 DRxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=iWE/oQCbC19xNKWM/JYBWF+oiYYLrFHWNh0bYFF47ZA=; b=NK+fGfLIw9AQAmTnhIiY66ABR6UojaGyk8soNO1n4cfRRsbnXOE1nb2njKoI4qlpS2 nAOYZJFFuPTez6Ub1G1aGdr4zQJ76tGAXp/50tzpWlknQcMQl+W2ud40waDh7vD7OQFI dvKSwB/bDrFjdLCr/IRzs2fPPhhI5MJICf49/xYWFCpTPprJwmkdTYOUOAZcv20t/rNs YPTX4YIOCwoxVuMy0GFnGSGTPoDwId79ygyAE7hcbzaAvbJDbOQcwKWelkKDNpRqG0rL +GC9DCJfRYcb2+hN/hMU5+oGmyWk4d2bfFx2BxbuQgzQIn0HWlqH8e3Qm8+DZ1Tw93A/ Fthw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i35si4726245plg.483.2017.08.30.07.42.30; Wed, 30 Aug 2017 07:42:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751805AbdH3Om1 (ORCPT + 26 others); Wed, 30 Aug 2017 10:42:27 -0400 Received: from foss.arm.com ([217.140.101.70]:45544 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751694AbdH3Ols (ORCPT ); Wed, 30 Aug 2017 10:41:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4116215BE; Wed, 30 Aug 2017 07:41:48 -0700 (PDT) Received: from e107985-lin.cambridge.arm.com (e107985-lin.cambridge.arm.com [10.1.210.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2A9B73F483; Wed, 30 Aug 2017 07:41:46 -0700 (PDT) From: Dietmar Eggemann To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Russell King , Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , Vincent Guittot , Juri Lelli Subject: [PATCH 2/4] arm: dts: exynos: add exynos5420 cpu capacity-dmips-mhz information Date: Wed, 30 Aug 2017 15:41:18 +0100 Message-Id: <20170830144120.9312-3-dietmar.eggemann@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170830144120.9312-1-dietmar.eggemann@arm.com> References: <20170830144120.9312-1-dietmar.eggemann@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived from the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platforms are affected once cpu-invariant accounting support is re-connected to the task scheduler: arndale-octa, peach-pi, peach-pit, smdk5420 The patch has been tested on Samsung Chromebook 2 13" (peach-pi, Exynos 5800). $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 389 389 389 389 The Cortex-A15 vs Cortex-A7 performance ratio is 1024/389 = 2.63. The values derived with the 'cpu_efficiency/clock-frequency dt property' solution are: $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1535 1535 1535 1535 448 448 448 448 The Cortex-A15 vs Cortex-A7 performance ratio is 1535/448 = 3.43. The discrepancy between 2.63 and 3.43 is due to the false assumption when using the 'cpu_efficiency/clock-frequency dt property' solution that the max cpu frequency of the little cpus is 1 GHZ and not 1.3 GHz. The Cortex-A7 cluster runs with a max cpu frequency of 1.3 GHZ whereas the 'clock-frequency' property value is set to 1 GHz. 3.43/1.3 = 2.64 $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq 1800000 1800000 1800000 1800000 1300000 <-- max cpu frequency of the Cortex-A7s (little cores) 1300000 1300000 1300000 Running another benchmark (single-threaded sysbench affine to the individual cpus) with performance cpufreq governor on the Samsung Chromebook 2 13" showed the following numbers: $ for i in `seq 0 7`; do taskset -c $i sysbench --test=cpu --num-threads=1 --max-time=10 run | grep "total number of events:"; done total number of events: 1083 total number of events: 1085 total number of events: 1085 total number of events: 1085 total number of events: 454 total number of events: 454 total number of events: 454 total number of events: 454 The Cortex-A15 vs Cortex-A7 performance ratio is 2.39, i.e. very close to the one derived from the Dhrystone based one of the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (2.63). We don't aim for exact values for the cpu capacity values. Besides the CPI (Cycles Per Instruction), the instruction mix and whether the system runs cpu-bound or memory-bound has an impact on the cpu capacity values derived from these benchmark results. Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: Kukjin Kim Cc: Krzysztof Kozlowski Signed-off-by: Dietmar Eggemann --- arch/arm/boot/dts/exynos5420-cpus.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 5c052d7ff554..d7d703aa1699 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -36,6 +36,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu1: cpu@1 { @@ -48,6 +49,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -60,6 +62,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -72,6 +75,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -85,6 +89,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -97,6 +102,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -109,6 +115,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -121,6 +128,7 @@ cooling-min-level = <0>; cooling-max-level = <7>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; }; }; From patchwork Wed Aug 30 14:41:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dietmar Eggemann X-Patchwork-Id: 111317 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1039945qge; Wed, 30 Aug 2017 07:42:13 -0700 (PDT) X-Received: by 10.84.213.151 with SMTP id g23mr2178023pli.285.1504104133545; Wed, 30 Aug 2017 07:42:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504104133; cv=none; d=google.com; s=arc-20160816; b=txdxx55RsfyfkjOJyEtsGkPkn6ng2S5OifwwNmELPUY3C+LSWVHhHW5EB1iiIZwuQr HNwvTeq0p2XF3kdJ8kx4fC/L7/6P1A4/+SngnrZwAyKK3Edq9yfwNUDHm6gt87yAS70g Hld1nNWRu29AYczB6UUH/2XNjWzBfXGfcr35r5QOa64cKvKaxDgx+yQyZNI4jz5okwpi Job/eH9QkNp5dxErehhHC3+nw6Spfrl/xWuDtiOMhaPb3+bvvx66FpkAM2wHF7XjpLro 8SUTExbh8lFPN/DTAWFSzkHa6dqf48r9CBZBnZ8/x1C22Xcmw9tVlf5Z7MeVGqWBzNW3 P/Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=9Z8aL7dHxO1SS+hTJtsg7+tBbzgfsUfBdFb50v34jRQ=; b=ADakMU3u601kElnmDZXd7Nti3dnZ/VrI7wsA+BMxJyJuSzryFOK28j7DioeetCEHAP ZCrZphZ2iDrpXa6wB5f43pvGYz1Jt2Ht+WDMzcKYE0YdP/Qp8+ZWxvE7DjjRHE5BrRCC ZJnX+zW7oCXsGydOBgms2WTbAJuHFjykE37Y+8A0JcON1WyC4zwfZ+yDmGuUhkrA9Kp7 yKYpvAyDFRgtWjaPcSHoDeAgxUMIQp8OnFWELUxrfuq3GJw9pnERG/c711rJF0dDI1Sh ydq6osxhhPj1u+M95G1me0w4RDbyOj2+RvPAfrC+J9OCEeBncfeFjZCR8dGq/xnbIRFR juyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h7si4901363plk.616.2017.08.30.07.42.12; Wed, 30 Aug 2017 07:42:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751758AbdH3Oly (ORCPT + 26 others); Wed, 30 Aug 2017 10:41:54 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45556 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751716AbdH3Olu (ORCPT ); Wed, 30 Aug 2017 10:41:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 918DA1610; Wed, 30 Aug 2017 07:41:50 -0700 (PDT) Received: from e107985-lin.cambridge.arm.com (e107985-lin.cambridge.arm.com [10.1.210.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7C5273F483; Wed, 30 Aug 2017 07:41:48 -0700 (PDT) From: Dietmar Eggemann To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Russell King , Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , Vincent Guittot , Juri Lelli Subject: [PATCH 3/4] arm: dts: exynos: add exynos5422 cpu capacity-dmips-mhz information Date: Wed, 30 Aug 2017 15:41:19 +0100 Message-Id: <20170830144120.9312-4-dietmar.eggemann@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170830144120.9312-1-dietmar.eggemann@arm.com> References: <20170830144120.9312-1-dietmar.eggemann@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platforms are affected once cpu-invariant accounting support is re-connected to the task scheduler: odroidxu3, odroidxu3-lite, odroidxu4 Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: Kukjin Kim Cc: Krzysztof Kozlowski Signed-off-by: Dietmar Eggemann --- arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index bf3c6f1ec4ee..ec01d8020c2d 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -35,6 +35,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu1: cpu@101 { @@ -47,6 +48,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu2: cpu@102 { @@ -59,6 +61,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu3: cpu@103 { @@ -71,6 +74,7 @@ cooling-min-level = <0>; cooling-max-level = <11>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <539>; }; cpu4: cpu@0 { @@ -84,6 +88,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu5: cpu@1 { @@ -96,6 +101,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu6: cpu@2 { @@ -108,6 +114,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; cpu7: cpu@3 { @@ -120,6 +127,7 @@ cooling-min-level = <0>; cooling-max-level = <15>; #cooling-cells = <2>; /* min followed by max */ + capacity-dmips-mhz = <1024>; }; }; }; From patchwork Wed Aug 30 14:41:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dietmar Eggemann X-Patchwork-Id: 111316 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp1039578qge; Wed, 30 Aug 2017 07:41:57 -0700 (PDT) X-Received: by 10.84.194.131 with SMTP id h3mr2229177pld.68.1504104117580; Wed, 30 Aug 2017 07:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504104117; cv=none; d=google.com; s=arc-20160816; b=OK5MskfKnSqo/dgDxtfpJVzn91MgeiliMmIvgwWv4QRC5lfMRMFsnBFXzhSPhQlLM0 VVxg7/JRfuzU035YD+dohqsomyT+zFEMHBzowG2op55U1N2ecx2AzdDX58ZkypRiTsD9 sqZ1bWKy3hQOnfZpgfX1TPBmhWjGtF2K1M+0jEDSfTFTqFGM0gFUw+b6IlN/HSBFKA3b zrFTBTCAh6quLN2+FD7gsgA2o+BScS1Pd0Di9shi1IqPHifzWrn2tQiPYJdD2wvXTRAi A53sgSyCmm8muXyk9iMtCmeHRB3oyAZHr26/ykS/Nq1ngRoHRpDs1pSSfcfEeOEyjrMO nETg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=myAEr7jOpOI3tZ+eLxQCGPGIeu2ZS1hukaK3M3pHkoM=; b=vV41Yv9N7e0T0m8+OOhMIGJO0Ps3cf00GuuhgJQ3au99xYsorkW6pnYEq4oIJyg/nE nq49bQZ3xkMdQAQTJQSfiHOoYqnsHuNyw+Y2KIkw8BXId+JqKMuIm7rHw8rt+9LaREKb S1hrwbj2V3y+G18hOQjGmbD17ECToPyxG327Hw2DNIqaWctGuQbDqDS+5WwQ/Lrn9Ef0 JUCVV6J5C5TJHx6rgRxYLDwtQ6gVmKgvkweo0uPLATeXh64wyXeT91D6EEu3Y7c2jNtu HlOwAzFDCfNfPOKzYolN7xAOh5s0VvLcjQEplnWAt4UToOlnRnZfpB22V23n1ZrkjEFT 81Lw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x6si4595079pfj.167.2017.08.30.07.41.57; Wed, 30 Aug 2017 07:41:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751791AbdH3Olz (ORCPT + 26 others); Wed, 30 Aug 2017 10:41:55 -0400 Received: from foss.arm.com ([217.140.101.70]:45570 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751730AbdH3Olx (ORCPT ); Wed, 30 Aug 2017 10:41:53 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1FAD164F; Wed, 30 Aug 2017 07:41:52 -0700 (PDT) Received: from e107985-lin.cambridge.arm.com (e107985-lin.cambridge.arm.com [10.1.210.41]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CCEF83F483; Wed, 30 Aug 2017 07:41:50 -0700 (PDT) From: Dietmar Eggemann To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Russell King , Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , Vincent Guittot , Juri Lelli Subject: [PATCH 4/4] arm: dts: r8a7790: add cpu capacity-dmips-mhz information Date: Wed, 30 Aug 2017 15:41:20 +0100 Message-Id: <20170830144120.9312-5-dietmar.eggemann@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170830144120.9312-1-dietmar.eggemann@arm.com> References: <20170830144120.9312-1-dietmar.eggemann@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Signed-off-by: Dietmar Eggemann --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2805a8608d4b..a57c0e170d8b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -56,6 +56,7 @@ clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -73,6 +74,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -82,6 +84,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -91,6 +94,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -100,6 +104,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -109,6 +114,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -118,6 +124,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -127,6 +134,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 {