From patchwork Tue Jun 9 13:13:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 799ACC433E3 for ; Tue, 9 Jun 2020 13:19:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 582B62074B for ; Tue, 9 Jun 2020 13:19:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WubWCnlk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727920AbgFINOa (ORCPT ); Tue, 9 Jun 2020 09:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728425AbgFINO1 (ORCPT ); Tue, 9 Jun 2020 09:14:27 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 564A1C03E97C; Tue, 9 Jun 2020 06:14:27 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id x18so8494562lji.1; Tue, 09 Jun 2020 06:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o4M3bTUDA74h1lwoV4T2HnrphCh8yThUo/f/7p0LEJQ=; b=WubWCnlkgI26pfDVw0Ep1IhBhHdHzkVOBYEPckyx1O/SSzugmHx8umh0venYLUw/Ro mfDiF91/57n9ZKeX48nhhr3xmtVLkLmP8/aoMTjbmywRLYKaZeSd53ZXy9mqDLnhedCH S3lBChQtwGUrZlKCvD8arJfsrruaX7nvAAwH5PLSoA1mNy1OqZCTFKZxW6Zk37QKK3So yd3LTmHTyJXjSfb8Uc+4nUf1bGJUVgEGZJ7gr/nNpjwmINI2yKy2tVqq5QS43LkptZ8P wCbHInI+KPaGs9kvstdV2zsM+mECcDcGDHnppOC73x608s71jfurL6wgGky/aC7rcNm0 d4Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o4M3bTUDA74h1lwoV4T2HnrphCh8yThUo/f/7p0LEJQ=; b=IlpiRaF0OjBFV2/oAG4LsBTyA0bgqIrTf5asDSmpniO5nMh2OYAOb7MmgzLT60s6Q0 PAF9OjHE+RSlYM+VCz2QPq5e/rZ4P5RqWnLmn0dD5oyyviYvfdD371WEnDAQfAJ3U2Hb 7U6BDvfXFGYT0dgK3GkqfSndjhO9COWauWq2Mu1o+mtJnEg7PWhBlw5iDXLpY8jSvP3o H0690dOWVayrhoCJn0rg6ezRp7WhM6Q2oP5Kg/kBBvhfgywKekzUFEvhZOHsOQtsD4ut 1AaK0rDH+3zcipHcLy2cLY6Jh/felf+QPkSr3ohT0ar6yGVON+Or7pMPDMOSPqk7pjo+ RMKQ== X-Gm-Message-State: AOAM533NuJ6BMQ+V6jekdvCIdf6TddlhpLR0nhJtzS7huRqyRhmjviGc TqdCOI2Nq1c9rHQ+ELPzgDI= X-Google-Smtp-Source: ABdhPJz0i8282/FJQIGDuc8pcHuZXMNEm+kWgDf2nK40LNBw6s1gDJI5NwQ3Sx3CyiBJD1F+eVni3Q== X-Received: by 2002:a2e:961a:: with SMTP id v26mr3973130ljh.296.1591708465781; Tue, 09 Jun 2020 06:14:25 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:25 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 01/37] clk: Export clk_hw_reparent() Date: Tue, 9 Jun 2020 16:13:28 +0300 Message-Id: <20200609131404.17523-2-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We're going to turn Tegra124 Memory Controller driver into a loadable kernel module. The driver uses clk_hw_reparent(), which isn't an exported kernel symbol. Let's export that function in order to allow modularization of the Tegra driver. Signed-off-by: Dmitry Osipenko --- drivers/clk/clk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 3f588ed06ce3..2fa6394d9a1b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2439,6 +2439,7 @@ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent) clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core); } +EXPORT_SYMBOL_GPL(clk_hw_reparent); /** * clk_has_parent - check if a clock is a possible parent for another From patchwork Tue Jun 9 13:13:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 204A1C433E0 for ; Tue, 9 Jun 2020 13:19:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F327E2074B for ; Tue, 9 Jun 2020 13:19:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ffYgl05p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729810AbgFINS7 (ORCPT ); Tue, 9 Jun 2020 09:18:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728903AbgFINOb (ORCPT ); Tue, 9 Jun 2020 09:14:31 -0400 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42421C03E97C; Tue, 9 Jun 2020 06:14:30 -0700 (PDT) Received: by mail-lj1-x243.google.com with SMTP id s1so24995711ljo.0; Tue, 09 Jun 2020 06:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GpFtIVnKnNndfebpkGzqwkaxd/wyRN7pW9EKTYyaD+o=; b=ffYgl05pncbdubAvxWR63NSZaAmUmQNPcFogjQbb+PcGJRKuP8Iq/ynaiJSynit/xg keR+9mZfb+LT6ii5FdCO/lBy9nE/++3QDwTMdUwltsZ5pAKMoT9XYkt3z4nHItDpv3Ir 0qmVkGd6cqv+vkib9r0Xd+yR8tOef58QmS/0k4be7cUsNgxeZ/jn+0LFdn6PFu6n14nt q7hPh1Jugmrq4m4erOiKWDXBLb2SCJylG30nC61UA3EcVkxpjArkVw8FpOrzQRtlghtI rtLoYVULmY1s8AakiUWvvvk9Pcm179rk9SFjhpkTk6vQCIKeL6zHGKzo+Ek/dkRR2DNB JG/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GpFtIVnKnNndfebpkGzqwkaxd/wyRN7pW9EKTYyaD+o=; b=CnmUNTBg5f11AdYghJBW0VhvBzAG78EUtd7o9rlqTfpULa8/3AUHzYwqixnZ6sCxM/ 2s9YXHMix5UU34lzBAsfQ73jdAml8Nm0LMlxs9pq4b4AE03NiNVZFKD6vwmsDz40INIT Pz5F/1pO24wPz+2BEnF2JP+eQIeH8XR/hLRL2junD8vW9FMc5OFXnUy6rAUakiaCEQYT Rq7sUr/os1QlzJt10dcDRz0Wc8sjHd3rksCEirZ5ccH8BCh2C5wUIP8ZCu3Zvq9hqUF+ kLZcqLqjAUKlzf1m6ARtV0KJSr1bF7q4JNWlsar+/FpOF5X6njMUilGE5jMecCAW/qea CYaw== X-Gm-Message-State: AOAM5327B9gje5y+VMZXqW8GdQTXaxOUq4gg6FzG3PNPXw6WgHJa5N7v MRP/61Zo6OhJjT2AiyRSbGo= X-Google-Smtp-Source: ABdhPJxejwOTAdW+uqBjAbDKAokXmYlrwzxZ/NkKhjhobM21Hk8tYt+VAfsUsH4qHeMB+LmaIWHrgQ== X-Received: by 2002:a2e:b003:: with SMTP id y3mr13797412ljk.78.1591708468663; Tue, 09 Jun 2020 06:14:28 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:28 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 03/37] clk: tegra: Export Tegra20 EMC kernel symbols Date: Tue, 9 Jun 2020 16:13:30 +0300 Message-Id: <20200609131404.17523-4-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We're going to modularize Tegra EMC drivers and some of the EMC clk driver symbols need to be exported, let's export them. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/clk/tegra/clk-tegra20-emc.c index 03bf0009a33c..dd74b8543bf1 100644 --- a/drivers/clk/tegra/clk-tegra20-emc.c +++ b/drivers/clk/tegra/clk-tegra20-emc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -235,6 +236,7 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, emc->cb_arg = cb_arg; } } +EXPORT_SYMBOL_GPL(tegra20_clk_set_emc_round_callback); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw) { @@ -291,3 +293,4 @@ int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) return 0; } +EXPORT_SYMBOL_GPL(tegra20_clk_prepare_emc_mc_same_freq); From patchwork Tue Jun 9 13:13:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5786BC433E2 for ; Tue, 9 Jun 2020 13:18:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3669820774 for ; Tue, 9 Jun 2020 13:18:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nG0smshM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728834AbgFINSl (ORCPT ); Tue, 9 Jun 2020 09:18:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728934AbgFINOd (ORCPT ); Tue, 9 Jun 2020 09:14:33 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5DF6C08C5C3; Tue, 9 Jun 2020 06:14:32 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id a9so21429565ljn.6; Tue, 09 Jun 2020 06:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=inyU7uvEHXWNKdXjhZ+FWQ4T48QVySmS07lzlxMPA2A=; b=nG0smshMQaIEGwEl6n7reFqzXxM/XiBGrPpeUPtourd0l6otgnwUTjl9dqe6oNfhNf 0irvV2vMmxLa434Rf5krdH0owV9KrmNbNVKh+ep+r0c4F7zFUUilRCCkA8gxghoh6X/H BH8RsoJY1g+fMlK61IYak4x/WcCmZv6rlHNMY76o0uK/bIZtWA2GcrnsD5H21pOJGolV SPNVTz38VxE0tFWFecoqxLb0mWE3Uf49qhc29zOXjxzWjyFySISOQ/iBvbzowW3a0NEs 1TtvU/Qf4sFkmulR8FmrB0jL2xVBmdR2F2DC+GhpHt2c5n5jwbfNrRmoxF/f8+Cs1AI5 d+nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=inyU7uvEHXWNKdXjhZ+FWQ4T48QVySmS07lzlxMPA2A=; b=VJWdXXX59p3EMEKCSK9N4RVbpAKQPpp1F8hFF8JX5E/4H7x4TC6+2Ct8uGatfsRjGp w8LJT4FWa3HA1qHazyy1ujSyEbWxESn2y1mBRJ7XuhWlk0kRU2X3m5JY1X8w+X9VnI4p mBWgpWwoAILNk/7544zPfbarcHKc99k0Q7sG0lv76mkpVyiwlzxFQU1K72gYRpSMgc1K vn/Y0U5B5luKnX0q79lQbL4qbsG7f1mYd7fPtdkfoJGz9JboAAhEwH/OdMnW9w7QRbkb LzhuS640HKJnaMUP+34yFVpuBVOaXbvckg4lP48hwOTgSGmXNxMKK73/f4gf11aNNmef PZ0Q== X-Gm-Message-State: AOAM532XC+mvLskNEV/Xx6mrrKjYF1Vgl0gCYOczpRZ4tMuDgIhkH29H pOKOU6E7HZpyfcGsWDJ8jTY= X-Google-Smtp-Source: ABdhPJyfQR3AHMM02VrWkKJdD2eGKv+n+xnq4wTxBZfCahAOo3SI17Awu7cyUDHToJ/VFX+/EY7PAA== X-Received: by 2002:a2e:140a:: with SMTP id u10mr13836531ljd.56.1591708470988; Tue, 09 Jun 2020 06:14:30 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:30 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 05/37] memory: tegra30-emc: Make driver modular Date: Tue, 9 Jun 2020 16:13:32 +0300 Message-Id: <20200609131404.17523-6-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds modularization support to the Tegra30 EMC driver. Driver now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/tegra30-emc.c | 17 ++++++++++++----- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 7e0e1ef87763..bd453de9d446 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -18,7 +18,7 @@ config TEGRA20_EMC external memory. config TEGRA30_EMC - bool "NVIDIA Tegra30 External Memory Controller driver" + tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC help diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ec8403557ed4..772aa021b5f6 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -298,6 +299,7 @@ int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) return 0; } +EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) { @@ -309,6 +311,7 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) return dram_count; } +EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 055af0e08a2e..85d4effb8e6f 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1343,6 +1343,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -1393,6 +1400,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra30-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -1403,9 +1411,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Jun 9 13:13:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49E0FC433E1 for ; Tue, 9 Jun 2020 13:18:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A3022074B for ; Tue, 9 Jun 2020 13:18:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="vPjwrNMz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730117AbgFINSJ (ORCPT ); Tue, 9 Jun 2020 09:18:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728952AbgFINOf (ORCPT ); Tue, 9 Jun 2020 09:14:35 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D836C05BD1E; Tue, 9 Jun 2020 06:14:34 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id u16so12450345lfl.8; Tue, 09 Jun 2020 06:14:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1vUln8AxproOPeNXLIolgqG8AVmr4RfHd4/MHI9RYKI=; b=vPjwrNMzvyDdxGLwUgk+5pkQPxwiTKlzCL95HLqOGcODX1Oas80+mff9Eqo1eHzyBw d1GYYz0oljiQE/PgotaU3quFAfqNJtFzYrujp0kALUN1Gi2Y5l7O9rmMdgWjs/ZXbr2y xS8+0raoj+TsYc0XtoCI9JtRVrGlbj0ThFLjjT34XLrsNak6dLiBsZh6RY68uUoj953P 80XCuvo+oBArKXNI4bQ6czN4ovjGUkJwnovzwfRhkxSVt05ty3zfRa0umZPebOF3wZIb WHk9yRZD+KxZ2adbMJyl6HPmR+by3gBfyUbCsV6mdnqNcAZUYUyHnDj7MVKXOJ/6fnXp aQCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1vUln8AxproOPeNXLIolgqG8AVmr4RfHd4/MHI9RYKI=; b=gdVLAoGm49AG9PuxSe/BcMhgqun/3ouRYP7WmnJzn7I0b5Qb0BohjaHuli/TA8uK0l iodBA73JP2+NmmM9ks6Pkqxm40N8/94l9c4B4/+Ys4Kea7szAxWlTU4+2QsxN3bqtjKh 4/liENqANPBOMRtP653vXyrwxjmU/7UOAtV70fVpTeX2bKJeDkqpONNYX5xCJ9KP+3ng e2Gm2dKqTrAQ0GuE74XK0mzczqOpp8hiNRX/Uvla5FHtrO1Cf3mb4PYZju+fujjvdpnW /yZabc82KFS1elPDqHgBcKQYPvZ/NZcTID3XuQ9WV9oF7okMDv+B8wcB+RD3UWnSBrRb 7Ysg== X-Gm-Message-State: AOAM531NhtjIq1kk6JPoA+WiQ5JczY/qEOTQdhGxH9/SAnGm41zYnfZg qbEHJx3IS5adCSijn1amUcg= X-Google-Smtp-Source: ABdhPJzUyT6uGZ4IuBhtXAR+ModohioHr1mJdY8GoaguG6lSKXb8zjWC9hhIcPBRdbgl3qsWtO2bSw== X-Received: by 2002:a19:2358:: with SMTP id j85mr15647151lfj.182.1591708472341; Tue, 09 Jun 2020 06:14:32 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:31 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 06/37] memory: tegra124-emc: Make driver modular Date: Tue, 9 Jun 2020 16:13:33 +0300 Message-Id: <20200609131404.17523-7-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds modularization support to the Tegra124 EMC driver. Driver now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra124-emc.c | 63 +++++++++++++++++----------- drivers/clk/tegra/clk-tegra124.c | 3 +- drivers/clk/tegra/clk.h | 12 ------ drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra124-emc.c | 32 +++++++++----- include/linux/clk/tegra.h | 11 +++++ include/soc/tegra/emc.h | 16 ------- 7 files changed, 73 insertions(+), 66 deletions(-) delete mode 100644 include/soc/tegra/emc.h diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c index 745f9faa98d8..4d8b8f1ba7cd 100644 --- a/drivers/clk/tegra/clk-tegra124-emc.c +++ b/drivers/clk/tegra/clk-tegra124-emc.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -21,10 +23,10 @@ #include #include -#include #include "clk.h" +#define CLK_BASE 0x60006000 #define CLK_SOURCE_EMC 0x19c #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0 @@ -79,7 +81,9 @@ struct tegra_clk_emc { int num_timings; struct emc_timing *timings; - spinlock_t *lock; + + tegra124_emc_prepare_timing_change_cb *prepare_timing_change; + tegra124_emc_complete_timing_change_cb *complete_timing_change; }; /* Common clock framework callback implementations */ @@ -98,7 +102,7 @@ static unsigned long emc_recalc_rate(struct clk_hw *hw, */ parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); - val = readl(tegra->clk_regs + CLK_SOURCE_EMC); + val = readl(tegra->clk_regs); div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK; return parent_rate / (div + 2) * 2; @@ -163,7 +167,7 @@ static u8 emc_get_parent(struct clk_hw *hw) tegra = container_of(hw, struct tegra_clk_emc, hw); - val = readl(tegra->clk_regs + CLK_SOURCE_EMC); + val = readl(tegra->clk_regs); return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK; @@ -204,7 +208,6 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, int err; u8 div; u32 car_value; - unsigned long flags = 0; struct tegra_emc *emc = emc_ensure_emc_driver(tegra); if (!emc) @@ -241,13 +244,11 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, div = timing->parent_rate / (timing->rate / 2) - 2; - err = tegra_emc_prepare_timing_change(emc, timing->rate); + err = tegra->prepare_timing_change(emc, timing->rate); if (err) return err; - spin_lock_irqsave(tegra->lock, flags); - - car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC); + car_value = readl(tegra->clk_regs); car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0); car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index); @@ -255,11 +256,9 @@ static int emc_set_timing(struct tegra_clk_emc *tegra, car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0); car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div); - writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC); - - spin_unlock_irqrestore(tegra->lock, flags); + writel(car_value, tegra->clk_regs); - tegra_emc_complete_timing_change(emc, timing->rate); + tegra->complete_timing_change(emc, timing->rate); clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent)); clk_disable_unprepare(tegra->prev_parent); @@ -473,12 +472,15 @@ static const struct clk_ops tegra_clk_emc_ops = { .get_parent = emc_get_parent, }; -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock) +struct clk * +tegra124_clk_register_emc(struct device_node *emc_np, + tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) { struct tegra_clk_emc *tegra; struct clk_init_data init; struct device_node *node; + struct resource res; u32 node_ram_code; struct clk *clk; int err; @@ -487,12 +489,21 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, if (!tegra) return ERR_PTR(-ENOMEM); - tegra->clk_regs = base; - tegra->lock = lock; + res.start = CLK_BASE + CLK_SOURCE_EMC; + res.end = res.start + 3; + res.flags = IORESOURCE_MEM; - tegra->num_timings = 0; + tegra->clk_regs = ioremap(res.start, resource_size(&res)); + if (!tegra->clk_regs) { + pr_err("failed to map CLK_SOURCE_EMC\n"); + return ERR_PTR(-EINVAL); + } + + tegra->emc_node = emc_np; + tegra->prepare_timing_change = prep_cb; + tegra->complete_timing_change = complete_cb; - for_each_child_of_node(np, node) { + for_each_child_of_node(emc_np, node) { err = of_property_read_u32(node, "nvidia,ram-code", &node_ram_code); if (err) @@ -512,11 +523,6 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, if (tegra->num_timings == 0) pr_warn("%s: no memory timings registered\n", __func__); - tegra->emc_node = of_parse_phandle(np, - "nvidia,external-memory-controller", 0); - if (!tegra->emc_node) - pr_warn("%s: couldn't find node for EMC driver\n", __func__); - init.name = "emc"; init.ops = &tegra_clk_emc_ops; init.flags = CLK_IS_CRITICAL; @@ -536,5 +542,12 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, /* Allow debugging tools to see the EMC clock */ clk_register_clkdev(clk, "emc", "tegra-clk-debug"); + /* + * Don't allow the kernel module to be unloaded, unloading is not + * supported by the EMC driver. + */ + try_module_get(THIS_MODULE); + return clk; -}; +} +EXPORT_SYMBOL_GPL(tegra124_clk_register_emc); diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 0c956e14b9ca..228d87367ac6 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -928,6 +928,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, + [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = false }, }; static struct tegra_devclk devclks[] __initdata = { @@ -1516,8 +1517,6 @@ static void __init tegra124_132_clock_init_post(struct device_node *np) tegra124_reset_deassert); tegra_add_of_provider(np, of_clk_src_onecell_get); - clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, NULL); - tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); tegra_cpu_car_ops = &tegra124_cpu_car_ops; diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 5ed8b95d331c..11a8bbe650c5 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -881,18 +881,6 @@ void tegra_super_clk_gen5_init(void __iomem *clk_base, void __iomem *pmc_base, struct tegra_clk *tegra_clks, struct tegra_clk_pll_params *pll_params); -#ifdef CONFIG_TEGRA124_EMC -struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, - spinlock_t *lock); -#else -static inline struct clk *tegra_clk_register_emc(void __iomem *base, - struct device_node *np, - spinlock_t *lock) -{ - return NULL; -} -#endif - void tegra114_clock_tune_cpu_trimmers_high(void); void tegra114_clock_tune_cpu_trimmers_low(void); void tegra114_clock_tune_cpu_trimmers_init(void); diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index bd453de9d446..c1cad4ce6251 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -28,7 +28,7 @@ config TEGRA30_EMC external memory. config TEGRA124_EMC - bool "NVIDIA Tegra124 External Memory Controller driver" + tristate "NVIDIA Tegra124 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_124_SOC help diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index d19fb7ae230d..98d98d09b00c 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -9,16 +9,17 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include #include -#include #include #include @@ -562,8 +563,8 @@ static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, return timing; } -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate) +static int tegra_emc_prepare_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -790,8 +791,8 @@ int tegra_emc_prepare_timing_change(struct tegra_emc *emc, return 0; } -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate) +static void tegra_emc_complete_timing_change(struct tegra_emc *emc, + unsigned long rate) { struct emc_timing *timing = tegra_emc_find_timing(emc, rate); struct emc_timing *last = &emc->last_timing; @@ -986,6 +987,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra124-emc" }, {} }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct device_node * tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) @@ -1251,9 +1253,20 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); + tegra124_clk_register_emc(pdev->dev.of_node, + tegra_emc_prepare_timing_change, + tegra_emc_complete_timing_change); + if (IS_ENABLED(CONFIG_DEBUG_FS)) emc_debugfs_init(&pdev->dev, emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; }; @@ -1265,9 +1278,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Mikko Perttunen "); +MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 3f01d43f0598..797b8bde18de 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -136,6 +136,8 @@ extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); extern void tegra210_clk_emc_update_setting(u32 emc_src_value); struct clk; +struct device_node; +struct tegra_emc; typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, @@ -146,6 +148,15 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, void *cb_arg); int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); +typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +struct clk * +tegra124_clk_register_emc(struct device_node *emc_np, + tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb); + struct tegra210_clk_emc_config { unsigned long rate; bool same_freq; diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h deleted file mode 100644 index 05199a97ccf4..000000000000 --- a/include/soc/tegra/emc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 NVIDIA Corporation. All rights reserved. - */ - -#ifndef __SOC_TEGRA_EMC_H__ -#define __SOC_TEGRA_EMC_H__ - -struct tegra_emc; - -int tegra_emc_prepare_timing_change(struct tegra_emc *emc, - unsigned long rate); -void tegra_emc_complete_timing_change(struct tegra_emc *emc, - unsigned long rate); - -#endif /* __SOC_TEGRA_EMC_H__ */ From patchwork Tue Jun 9 13:13:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27623C433E2 for ; Tue, 9 Jun 2020 13:18:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 07C0E20737 for ; Tue, 9 Jun 2020 13:18:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VnryWu+a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730109AbgFINSJ (ORCPT ); Tue, 9 Jun 2020 09:18:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729023AbgFINOh (ORCPT ); Tue, 9 Jun 2020 09:14:37 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CA4AC08C5C2; Tue, 9 Jun 2020 06:14:36 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id 202so12459918lfe.5; Tue, 09 Jun 2020 06:14:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tzjWXOFJZUWh4EJTzInOXHHEbdt+siqMf/YejHURVDA=; b=VnryWu+aK7L0DcpiyL1N3EE7vSAAw1+NT32TBAV1tcBb/suSZax3CH7mFh6FHpLDM8 87OUFDzWVfo6qk3nbUEHkvI9kH21D+K6986gejHq+PeXGdN5AsW1CZIGo+SIbcMz7F0J +F4XLpJCSLPHX/BpmPlFdGd/Ur+gu3ozUYLTCQMGnaBERJYvYSNUL0bDKIG5DxlVBljg cqNlOz1kuqV60AHRNZuWl3kxJm78d4zTyXd1IFik28f9SlGmfBeovETkWgYl1dbbS1bf SHgzmt9BMXIUa+oqWX/w6adLSx8GqSkglDqU9Yg3+TnkUfxTPqvXnDhFQCIQs+Ujp11A YrbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tzjWXOFJZUWh4EJTzInOXHHEbdt+siqMf/YejHURVDA=; b=WZ982JHuvyTF76S+Cb+nlAILmp7lHMtMydJE7Mh2F8poRxbPg7V8ja5cB8iPyTb6z0 TcBdyRPZGJA6uP689vjg8zdAWbMOR7vmzlgm8K2Pt6kiQtPl3w6Mq/3cPAoeogvcBZPp 3TPDrfVzX49ymFaPU9PrRMv7GOcmA9EM7h4hUKzo3r8QzpAq2c5QqBsIjJFHGpFeOvLN 1ipX2bP1nARHy+6vT6Hwwk691PuowZlrOkAcno6/cFpGtz+DiQHi+9AU5kGoQwb/GsTL xoENl/SCzyk7404BHh8FkLpx+84WsFVsdqnpwPmUCv1MVnL87FQ9dopZ4KNvfF8+rfzU 5/2w== X-Gm-Message-State: AOAM531LAhms8rzrSXQ314nbOdMRKK7QZzNyDFB3WwlVAgmmgtbWEhoN N9NZlGw4q8naVBqvv39oZgw= X-Google-Smtp-Source: ABdhPJyeHIUP/pqKNcqji83du0vLJY5MSz/ENMwIxIYDajj/AC39DJqr1Xg3KQnU0hJWGNaSztmNng== X-Received: by 2002:a19:6914:: with SMTP id e20mr15497190lfc.27.1591708474918; Tue, 09 Jun 2020 06:14:34 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:34 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 08/37] soc/tegra: fuse: Export tegra_read_ram_code() Date: Tue, 9 Jun 2020 16:13:35 +0300 Message-Id: <20200609131404.17523-9-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The tegra_read_ram_code() is used by EMC drivers and we're going to make these driver modular, hence this function needs to be exported. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 3cdd69d1bd4d..b3c930b805c5 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -3,6 +3,7 @@ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include @@ -65,6 +66,7 @@ u32 tegra_read_ram_code(void) return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT; } +EXPORT_SYMBOL_GPL(tegra_read_ram_code); static const struct of_device_id apbmisc_match[] __initconst = { { .compatible = "nvidia,tegra20-apbmisc", }, From patchwork Tue Jun 9 13:13:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2070EC433E1 for ; Tue, 9 Jun 2020 13:14:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA8D4207C3 for ; Tue, 9 Jun 2020 13:14:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fF4O/Kp8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729052AbgFINOm (ORCPT ); Tue, 9 Jun 2020 09:14:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729027AbgFINOi (ORCPT ); Tue, 9 Jun 2020 09:14:38 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D36FC08C5C3; Tue, 9 Jun 2020 06:14:37 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id r125so12406803lff.13; Tue, 09 Jun 2020 06:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+95j4xiCVDnfcLUm7JOEhc1KRXPcYGWky6OtXHtOxdU=; b=fF4O/Kp8bp2aC6LDSu8w3J8POQSvK7tfBc+Vsw5T2WcWwfmbQ6NVsefHBdsQB29eJs TlVaBUvpMhtOTUa0Ryt/K4S360qhF8hawBijaQA2LyEHxtB3drfu3xuHIeiwQ4HThurd JbMox4nwo5vQiZbmK22cb87RRjayGYe0wDiumBsk23uvvHWZRvcNoSIShaatBtUFebG5 BOyWG5yULvspnDjwwor8tT3VYRd3h/3Fjqh9BS7GWbKL56VBuCZik1sri2B5R4uRE5pi eom4aqwxgZeERfio4absDUNrWcJsjJSpxX7iS4DiBWOpF220Mid9m682tpCxjLjlFLJz a4Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+95j4xiCVDnfcLUm7JOEhc1KRXPcYGWky6OtXHtOxdU=; b=c5wA7YmW3cVfrgnFeUHpoKuq3OCd5d47lB/Tcn8tjRRQdM3Wnxty+FB7WPBaxnOiFR g9C1CpAIR3zgSYf+MlfsWgvdNVThs6IcouGCMTExW0VV51rxU7sotbL+odWte/pzMe2N BaI0/s20z2I8UWGFhLvqjfZ7tTUshRUD6lL3QdqBsz4RDC7Z8iR3sgmBKazO+freo5jy BPVSNMvBcFGtvdFg20A4Wilg2Yw1T2Ho/pkjl2r5a/1unW17cf5q2NoiiGlPuCFlsxI3 nupxejNUBGrtPWcp109EScOSc4Lr77FzOhTINcGr1dOxIUjK9n8zpcVIEDyXol12k/5d XvFQ== X-Gm-Message-State: AOAM530+1lYR/ALgG6uav/rclh1b0sOONb4aJnZln2l0MpORmGOb0tFi kCs5RS/hZtzmYDexw8L9q1U= X-Google-Smtp-Source: ABdhPJwpOmAZQvJDK7Bkc7F/ZxxtIqqFVMtBeQh4BlWFAESl0Ak0kldnvP0J0H5rXh7Bfp+rXpSKTg== X-Received: by 2002:a19:be55:: with SMTP id o82mr15072927lff.168.1591708476142; Tue, 09 Jun 2020 06:14:36 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:35 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 09/37] memory: tegra20-emc: Initialize MC timings Date: Tue, 9 Jun 2020 16:13:36 +0300 Message-Id: <20200609131404.17523-10-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We're going to add interconnect support to the EMC driver. Once this support will be added, the Tegra20 devfreq driver will no longer be able to use clk_round_rate(emc) for building up OPP table. It's quite handy that struct tegra_mc contains memory timings which could be used by the devfreq drivers instead of the clk rate-rounding. The tegra_mc timings are populated by the MC driver only for Tegra30+ SoCs, hence the Tegra20 EMC could populate timings by itself. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 47 ++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index c1cad4ce6251..5bf75b316a2f 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -10,7 +10,7 @@ config TEGRA_MC config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on ARCH_TEGRA_2x_SOC + depends on TEGRA_MC && ARCH_TEGRA_2x_SOC help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 0baa6590adea..2e310c51c599 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -15,12 +15,15 @@ #include #include #include +#include #include #include #include #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -650,6 +653,38 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static int tegra_emc_init_mc_timings(struct tegra_emc *emc) +{ + struct tegra_mc_timing *timing; + struct platform_device *pdev; + struct device_node *np; + struct tegra_mc *mc; + unsigned int i; + + np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart"); + if (!np) + return -ENOENT; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return -ENOENT; + + mc = platform_get_drvdata(pdev); + if (!mc) + return -EPROBE_DEFER; + + mc->timings = devm_kcalloc(mc->dev, emc->num_timings, sizeof(*timing), + GFP_KERNEL); + if (!mc->timings) + return -ENOMEM; + + for (i = 0; i < emc->num_timings; i++) + mc->timings[mc->num_timings++].rate = emc->timings[i].rate; + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -705,6 +740,18 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; } + /* + * Only Tegra30+ SoCs are having Memory Controller timings initialized + * by the MC driver. For Tegra20 we need to populate the MC timings + * from here. The MC timings will be used by the Tegra20 devfreq driver. + */ + err = tegra_emc_init_mc_timings(emc); + if (err) { + dev_err(&pdev->dev, "failed to initialize mc timings: %d\n", + err); + return err; + } + tegra20_clk_set_emc_round_callback(emc_round_rate, emc); emc->clk = devm_clk_get(&pdev->dev, "emc"); From patchwork Tue Jun 9 13:13:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC813C433E1 for ; Tue, 9 Jun 2020 13:18:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9BAA20737 for ; Tue, 9 Jun 2020 13:18:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fqZ0bjYi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728850AbgFINSG (ORCPT ); Tue, 9 Jun 2020 09:18:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729041AbgFINOl (ORCPT ); Tue, 9 Jun 2020 09:14:41 -0400 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38ACBC08C5C5; Tue, 9 Jun 2020 06:14:40 -0700 (PDT) Received: by mail-lf1-x143.google.com with SMTP id d7so12448130lfi.12; Tue, 09 Jun 2020 06:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=psA+m6s/YQ71wfUHabJ5pnZ0YjIiMWnkB+97bmL+R4g=; b=fqZ0bjYiV00boOxgS6onhvxlQ9S9CyK3l7dXy0+pQya1ipNEALmG2AE+b0GtFfTX0E vBjEsRnSHwVAdypxjN9AQ2RE4tkQZ0t+9Hf3LaX9zHdNqdEe1Qg1A/U2ia5X0z6CcRGi t0J+k/aYVe6Txy1mcz9mZWMRvJePE5u3/N7uCD4keohE5idEl7dR/6UzGLoOYPglryhL wkGjmcYEZKZc8ooE6EYKNJe1/Kpg1wIVDBWoOTPec9spYFSBMXwBElXLXFDP7fRDLtTr q7piTUsA/Wc5Fp/zWhFf9Ysp/qLz0okGyK9WdMN6ZXG5+iG3Bhm44n25wTIvyX0f69GI 7Wzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=psA+m6s/YQ71wfUHabJ5pnZ0YjIiMWnkB+97bmL+R4g=; b=jJH9BnKv4g+Z3HYeZD27IMd697N10vR8aflgtMfPE1Vr7PHlrTSclrOVwn1khdZRRd Z3ZigveK3nfF9gb8VVJNWXcC9TS3DdfhT2S5tExUcLbvh8Ii9HNaOjphmNQbJuJpRetH kYdwEMPY1ZXS4mTlgKV6PXq8Q9Xv05dZylRhPAqjBav8YXTFBYlR+C4qfSyPyRjuEgJV yb/VTsHOLOWfl4nlo0uoIhcZNo0mlgOYN2XZlXJO4AFyKZJYM0wd0pQ1d5QoOLqieCqF OVJIzCtu1297VMAFVaJbiqIDbh/PBcf/5pJptFObN5cHJIJKhkEGbcE6Gcg7YzkssRQp 1txw== X-Gm-Message-State: AOAM533e7OidFP7c8m19TSeVh1sSbivn4Sj8ngKQ387x9J7sKsnRYV49 INaVPVNIoLZ0PEly8e3h/ac= X-Google-Smtp-Source: ABdhPJw/wnzx53uI16yvdGqHv0RalaBGuElHs69YM/FEdoHZHRzNhx+369sS1v+B+hNO8kRF0AeYRw== X-Received: by 2002:a19:f813:: with SMTP id a19mr15271550lff.212.1591708478731; Tue, 09 Jun 2020 06:14:38 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:38 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 11/37] PM / devfreq: tegra30: Silence deferred probe error Date: Tue, 9 Jun 2020 16:13:38 +0300 Message-Id: <20200609131404.17523-12-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tegra EMC driver was turned into a regular kernel driver, it also could be compiled as a loadable kernel module now. Hence EMC clock isn't guaranteed to be available and clk_get("emc") may return -EPROBE_DEFER and there is no good reason to spam KMSG with a error about missing EMC clock in this case, so let's silence the deferred probe error. Signed-off-by: Dmitry Osipenko --- drivers/devfreq/tegra30-devfreq.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c index e94a27804c20..423dd35c95b3 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -801,9 +801,12 @@ static int tegra_devfreq_probe(struct platform_device *pdev) } tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); - if (IS_ERR(tegra->emc_clock)) { - dev_err(&pdev->dev, "Failed to get emc clock\n"); - return PTR_ERR(tegra->emc_clock); + err = PTR_ERR_OR_ZERO(tegra->emc_clock); + if (err) { + if (err != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get emc clock: %d\n", + err); + return err; } err = platform_get_irq(pdev, 0); From patchwork Tue Jun 9 13:13:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6622C433E2 for ; Tue, 9 Jun 2020 13:17:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4DDD20737 for ; Tue, 9 Jun 2020 13:17:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SEopFD6W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730042AbgFINRc (ORCPT ); Tue, 9 Jun 2020 09:17:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729090AbgFINOp (ORCPT ); Tue, 9 Jun 2020 09:14:45 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3064C03E97C; Tue, 9 Jun 2020 06:14:43 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id 9so24988181ljc.8; Tue, 09 Jun 2020 06:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AmHb/qTFiuR6DXvA/ffC/nHLs0yGE7r571S6zKct1lc=; b=SEopFD6WA6X0oE0yMZuxwxvYBQFHQJCCJua3OwUoX/QqrQlqZ3M+GzRG9yCFrFseZP KZ+VpLlPociuyizoUcEgoYDc2D/f2f8RlMbG1zK/GokjMg4umvEjcEmwl8hkk4TLK6IM tF61xjPihOqkZaHBYYLssFhno8KgX92dIUtIiLfVbo7+JTImobm6iXLX6gfB3RtJ5DyG XKkEb75lI/cBFh6PztCCh/B2uQerDExyOHECRoi7sA+VgHSYD7KRAvCeDqt0GOgOcVFJ 6NtBgNT9LVFusNmYz3wZSuJN11UhTRhKjbre8gvBXoW09blWoxZd16ni/P2Vt7/5xtgS eQmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AmHb/qTFiuR6DXvA/ffC/nHLs0yGE7r571S6zKct1lc=; b=enai5aiH/umStV/4nIXur0XZZ9zZZNy4nVnmXSNnOcu6ED0VSObU6m49KHr6wUnnRO 7f8o0R0qhYtR4bx7ubcdnRrIw2+KfV3bjBwpGTYPOorrlfiWWTRJv/fGzUaIPPiNw2e0 Ab0aT1X/p4Jw+W07WoQ1mvsMw3FPlhyborGsLHJdI0kv/6k6wwv6Q31Qf8gAqolw4CdR 4zNpqf7DeCtmlNjnOfjNkK2+B8Z9W0o0k6eLklkfE9DGKUsMxZUj3IyZwUwIlU5FWxRh Mv9C4mTGGu41BV8pqYCCLH9SOC3chfYvv4Wm3d+mGleE3BsXmOBRSNC8r92BOxfS1XSv WpCg== X-Gm-Message-State: AOAM531s+pa3ppgtUltTW/2dKlxHrAmj7ZsfiVIM7GYunfbcOMZIgxys e/ObTY2QUHnQQ6wO8tm8Y6A= X-Google-Smtp-Source: ABdhPJyyEojgVqUPpi4CNo4lhcaSGa8eRgXbgLQjT8AsOnF95049pCzOGKyIKTvZUwaIiCa8veiYMQ== X-Received: by 2002:a2e:9f57:: with SMTP id v23mr11785142ljk.324.1591708482389; Tue, 09 Jun 2020 06:14:42 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:41 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 14/37] PM / devfreq: tegra20: Add error messages to tegra_devfreq_target() Date: Tue, 9 Jun 2020 16:13:41 +0300 Message-Id: <20200609131404.17523-15-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org It's useful to now when something goes wrong instead of failing silently, so let's add error messages to tegra_devfreq_target() to prevent situation where it fails silently. Signed-off-by: Dmitry Osipenko --- drivers/devfreq/tegra20-devfreq.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c index bf504ca4dea2..249d0dc44f6c 100644 --- a/drivers/devfreq/tegra20-devfreq.c +++ b/drivers/devfreq/tegra20-devfreq.c @@ -44,19 +44,25 @@ static int tegra_devfreq_target(struct device *dev, unsigned long *freq, int err; opp = devfreq_recommended_opp(dev, freq, flags); - if (IS_ERR(opp)) + if (IS_ERR(opp)) { + dev_err(dev, "failed to find opp for %lu Hz\n", *freq); return PTR_ERR(opp); + } rate = dev_pm_opp_get_freq(opp); dev_pm_opp_put(opp); err = clk_set_min_rate(tegra->emc_clock, rate); - if (err) + if (err) { + dev_err(dev, "failed to set min rate: %d\n", err); return err; + } err = clk_set_rate(tegra->emc_clock, 0); - if (err) + if (err) { + dev_err(dev, "failed to set rate: %d\n", err); goto restore_min_rate; + } return 0; From patchwork Tue Jun 9 13:13:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6AC9C433E0 for ; Tue, 9 Jun 2020 13:15:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BCF4920801 for ; Tue, 9 Jun 2020 13:15:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="axZSjAne" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729259AbgFINO5 (ORCPT ); Tue, 9 Jun 2020 09:14:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729097AbgFINOq (ORCPT ); Tue, 9 Jun 2020 09:14:46 -0400 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4206EC08C5C3; Tue, 9 Jun 2020 06:14:46 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id x18so8496014lji.1; Tue, 09 Jun 2020 06:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=061hlrRfunwkyZki3oWiaKmN7ev2U21u3B6yt3cimTc=; b=axZSjAneUL42duObpUbjthqYAX09o70VhMiVjh8mLUewcbETS1bIjcyYywet8A7b1z shfyFgjs0qHecOJRZElkTka5Op0ww6i0Ro/YCmC5GwNWA37Iiw4Awd8ExzkwjMs/Ht6V J65nyAt9LZl3xQDeLvEs+u41oNK1R9JQkJpZEXQRCQ7rcakNP6pwk+SXDd6c/IFR/ujn +wk9B97Dwfr0UmQs2VuARV2mueB1bWmirTeZjxOZLJSQ2iVf6dWm5NSooVgtBNAAJiAz gAoPgEB24t/PNPO719An12piy22azY0O4+hgxKfbMLGC9AQazSLGQO8AANPw3W+2iNiW QG8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=061hlrRfunwkyZki3oWiaKmN7ev2U21u3B6yt3cimTc=; b=EGtHYSHjUDvp10sPKdWlUJRcj2eJp2PEnj/7rsPou1S7MtLSwd3LWMZata9xgroNqS z0p+d2cEfcJLEhFwIs5JZhVdw2cYp150/othA/8jUHpQkMNtv0j1pl+1RwewA54BRRUb qfXzCZo2uusfF0dFIx1mvuUMICMfNQb2FS+BaIcUk+CCnyW/dFKCIr9ZAriTZt2BVHAn hTXUXn2s4Om5hzRlWUTdvKWuqn/RLCdJQUAVCXZFUZ/cwcnxhyG53jiOCXdWs7RwOlru gnUpiej6LwvZEvPngI0mHV0sXN+mtVkWbG6tdd4KK/j/50wAGVXdzu4s9WSPrHcBuKEF cntQ== X-Gm-Message-State: AOAM533p4s9sjDzezZAm9hYB7hnoKxaonQbZ5q7+JWX60VIxvdNgJhir avCe3KkCMKeDED9DXC+TcCs= X-Google-Smtp-Source: ABdhPJwmd7mQIA1zlol7FDcTPL+eVrsqyXZIVfZNkLkmHPGjO5Ho3fGM+DIMTGsL+TWXXlRInKK/VQ== X-Received: by 2002:a2e:8809:: with SMTP id x9mr12288313ljh.442.1591708484744; Tue, 09 Jun 2020 06:14:44 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:44 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 16/37] PM / devfreq: tegra20: Adjust clocks conversion ratio and polling interval Date: Tue, 9 Jun 2020 16:13:43 +0300 Message-Id: <20200609131404.17523-17-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The current conversion ratio results in a higher frequency than needed, that is not very actual now since the Display Controller driver got support for memory bandwidth management and hence memory frequency can go lower now without bad consequences. Since memory freq now goes to a lower rates, the responsiveness of interactive applications become worse due to a quite high polling interval value that is currently set to 500ms. Changing polling interval to 30ms results in a good responsiveness of the system. Signed-off-by: Dmitry Osipenko --- drivers/devfreq/tegra20-devfreq.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c index 249d0dc44f6c..7cdea4ba38f7 100644 --- a/drivers/devfreq/tegra20-devfreq.c +++ b/drivers/devfreq/tegra20-devfreq.c @@ -79,16 +79,12 @@ static int tegra_devfreq_get_dev_status(struct device *dev, /* * EMC_COUNT returns number of memory events, that number is lower - * than the number of clocks. Conversion ratio of 1/8 results in a - * bit higher bandwidth than actually needed, it is good enough for - * the time being because drivers don't support requesting minimum - * needed memory bandwidth yet. - * - * TODO: adjust the ratio value once relevant drivers will support - * memory bandwidth management. + * than the number of total EMC clocks over the sampling period. + * The clocks number is converted to maximum possible number of + * memory events using the ratio of 1/4. */ stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT); - stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8; + stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 4; stat->current_frequency = clk_get_rate(tegra->emc_clock); writel_relaxed(EMC_GATHER_CLEAR, tegra->regs + MC_STAT_CONTROL); @@ -98,7 +94,7 @@ static int tegra_devfreq_get_dev_status(struct device *dev, } static struct devfreq_dev_profile tegra_devfreq_profile = { - .polling_ms = 500, + .polling_ms = 30, .target = tegra_devfreq_target, .get_dev_status = tegra_devfreq_get_dev_status, }; From patchwork Tue Jun 9 13:13:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C7FC433E2 for ; Tue, 9 Jun 2020 13:17:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6291D20801 for ; Tue, 9 Jun 2020 13:17:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Q3BU6gEN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730032AbgFINRb (ORCPT ); Tue, 9 Jun 2020 09:17:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729217AbgFINOv (ORCPT ); Tue, 9 Jun 2020 09:14:51 -0400 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F6F3C03E97C; Tue, 9 Jun 2020 06:14:51 -0700 (PDT) Received: by mail-lf1-x144.google.com with SMTP id u16so12451003lfl.8; Tue, 09 Jun 2020 06:14:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cD6QbvUalU2rLnxp32Ky1as2vyVdkG0FzQ7kZtLukL0=; b=Q3BU6gEN8cA0NMpF2QMR7/ASta55aBJk7I1MDLK4koAixnvzP0ayWGZf3TbVJLF+65 vId8KuOWkM8U5/Iu7EFpk85VTkAI1Oehc5+09VHXeLIo+3cVsuJq4oGVwhxOfGNsuvbD NY1D4HQAhEREDBvmx8hAhNZ0GxixaeV++zeo7LJMnNn7h/CFhkHfaAgF7SCKO1XsKJJY 0ZyzEXamv8Ak+eCx/bhJHanQn+avSJOXU6PU4tk+eh+cUe2i6S0A4Jt1tYo88dL8dYJC s5eTYYMCyCjEBFckuvK4gbtaaU0Yeq9B1wPNhczvvoYJBXYoJl7pPyfH9SzzMzxPj2yF LUag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cD6QbvUalU2rLnxp32Ky1as2vyVdkG0FzQ7kZtLukL0=; b=fhOqmMaU3lhgZeA0kzxjATepFWHp6msRMorZA/1N1nuF2UMWuX7ShUBEh80M6QahxI 7F1Fl9x0xHXaNQvuyK+2nOlxtmNy9co2PRw6h+ZrbKJzR3M+5PTkxlMgAByWiVdw+bGk hA/1cnAq0yJnQHSIXqIyz/5WbDKOseVq+CaNo1KSCwH3N5Fzdze0ojkZC8TLe7+vGOLb l6M9MH4I63lIOTCdeTSXZUlLZZlJp+UP1Q3lCIOnZB1X08yjFuDcTvQuIwwXjEnJ6GVf WFYTPfrnd7Pk2rCT08l+vXRYWCNw7bHR+FitgwTJCsYwFswEkcFOb9/49DdkxtizF6U7 1xDg== X-Gm-Message-State: AOAM533rIxf86hceLB34YOypewxC6xZOkrydje/uiYaXE81YwPNB4vvt MBvECA9ULcBiw0p/0YA6l9o= X-Google-Smtp-Source: ABdhPJy+RmOWQqGmO4euFmKISnOZyzVw/14wPtNZKhpxrmxeb6HuV6Wq/6xWdmnG+KQ6p+Izt7lD/w== X-Received: by 2002:a19:6a09:: with SMTP id u9mr15434868lfu.65.1591708489649; Tue, 09 Jun 2020 06:14:49 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 20/37] dt-bindings: memory: tegra30: mc: Document new interconnect property Date: Tue, 9 Jun 2020 16:13:47 +0300 Message-Id: <20200609131404.17523-21-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Memory controller is interconnected with memory clients and with the external memory controller. Document new interconnect property which turns memory controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 84fd57bcf0dc..5436e6d420bc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -57,6 +57,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -120,6 +123,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -135,6 +139,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-1 { nvidia,ram-code = <1>; From patchwork Tue Jun 9 13:13:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6647AC433E1 for ; Tue, 9 Jun 2020 13:17:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C8DD20737 for ; Tue, 9 Jun 2020 13:17:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gQsq5vBy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730002AbgFINRH (ORCPT ); Tue, 9 Jun 2020 09:17:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729046AbgFINOz (ORCPT ); Tue, 9 Jun 2020 09:14:55 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5721C08C5C2; Tue, 9 Jun 2020 06:14:54 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id s1so24997670ljo.0; Tue, 09 Jun 2020 06:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x2QRKqDUU0r/i8wziU3TXmY7UhU4qCj9qlLs6iymsj0=; b=gQsq5vBy8IMDNM7+/Hfn/bhMeqsi2iCjjxQlxV1JQhTM1m6V30gMaUBnz/vpZja6wO S55KLZd3Wis60vgftP7nDWU9z8JgXKCjao8yE1waCStrPvIj+bN+C9p4scu1CH9rc9J5 dJrAf9EmD8Mm32fNtZVAkVZxdUK66ICAXOP+C022YfiCplk+1myjzRQUa3FdINFcGejR +57zmNnzxTqWEhEc2+q7C5GSal0kE4rv/EYedfQbPGuR8TDod0EXDWFjYT/GwsYT/Yby OzMLjEn39Hxv5doWaSaWEbVyONb3cvBIOpDudHSdFi5DQkJdD70FT1FaU4nIeV7NQqQo oe7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x2QRKqDUU0r/i8wziU3TXmY7UhU4qCj9qlLs6iymsj0=; b=ttBh9XhEDjJxXc+a2l3ybj93EytxmnTT9XX5DBU+DPf5hYl7Cl0M9VV8oVPaJEJovm uDBNkNg1DQhG0o7J1fd8ky68XcCPRbrRwcTgx7ZH/Uze7on9S4Kdcq4A6Lp+uzupNTvP b7PWsLHAdIIyVDMu+s2Hllk6Jtg3EE3Y8du09gpynOoAbqYBKVkg1c/fTjdvx7sLKB6Z ZT45w1kuoCAlheX1zYnwqbn7/Qz2QDUWxlym6+/m8lQ32ZVsohzbhy8I9JrYYpqgeq/o nNMrKNxP1I1zJ84K1bW+juyV8mkmdPmgzVxhj/1GPj/2p4vokxa0NAWkmidA/uKGhidM ruKA== X-Gm-Message-State: AOAM532vFWU5Z5PkI0LU/rO0WwDqwFNhT6aoI6RBDCAV/dwooNLpT4xA XHwr22524ku88WByHxLsjAc= X-Google-Smtp-Source: ABdhPJyQE9qsPGOsbzMKIh/U4DMx/XoZxWr7S9/konUveZqAp3LB0samhhDoimM8Q0Gt5Dnrb95gMw== X-Received: by 2002:a2e:6c12:: with SMTP id h18mr14744081ljc.62.1591708493227; Tue, 09 Jun 2020 06:14:53 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:52 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 23/37] dt-bindings: memory: tegra20: Add memory client IDs Date: Tue, 9 Jun 2020 16:13:50 +0300 Message-Id: <20200609131404.17523-24-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h index 35e131eee198..6f8829508ad0 100644 --- a/include/dt-bindings/memory/tegra20-mc.h +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 +#define TEGRA20_MC_DISPLAY0A 0 +#define TEGRA20_MC_DISPLAY0AB 1 +#define TEGRA20_MC_DISPLAY0B 2 +#define TEGRA20_MC_DISPLAY0BB 3 +#define TEGRA20_MC_DISPLAY0C 4 +#define TEGRA20_MC_DISPLAY0CB 5 +#define TEGRA20_MC_DISPLAY1B 6 +#define TEGRA20_MC_DISPLAY1BB 7 +#define TEGRA20_MC_EPPUP 8 +#define TEGRA20_MC_G2PR 9 +#define TEGRA20_MC_G2SR 10 +#define TEGRA20_MC_MPEUNIFBR 11 +#define TEGRA20_MC_VIRUV 12 +#define TEGRA20_MC_AVPCARM7R 13 +#define TEGRA20_MC_DISPLAYHC 14 +#define TEGRA20_MC_DISPLAYHCB 15 +#define TEGRA20_MC_FDCDRD 16 +#define TEGRA20_MC_G2DR 17 +#define TEGRA20_MC_HOST1XDMAR 18 +#define TEGRA20_MC_HOST1XR 19 +#define TEGRA20_MC_IDXSRD 20 +#define TEGRA20_MC_MPCORER 21 +#define TEGRA20_MC_MPE_IPRED 22 +#define TEGRA20_MC_MPEAMEMRD 23 +#define TEGRA20_MC_MPECSRD 24 +#define TEGRA20_MC_PPCSAHBDMAR 25 +#define TEGRA20_MC_PPCSAHBSLVR 26 +#define TEGRA20_MC_TEXSRD 27 +#define TEGRA20_MC_VDEBSEVR 28 +#define TEGRA20_MC_VDEMBER 29 +#define TEGRA20_MC_VDEMCER 30 +#define TEGRA20_MC_VDETPER 31 +#define TEGRA20_MC_EPPU 32 +#define TEGRA20_MC_EPPV 33 +#define TEGRA20_MC_EPPY 34 +#define TEGRA20_MC_MPEUNIFBW 35 +#define TEGRA20_MC_VIWSB 36 +#define TEGRA20_MC_VIWU 37 +#define TEGRA20_MC_VIWV 38 +#define TEGRA20_MC_VIWY 39 +#define TEGRA20_MC_G2DW 40 +#define TEGRA20_MC_AVPCARM7W 41 +#define TEGRA20_MC_FDCDWR 42 +#define TEGRA20_MC_HOST1XW 43 +#define TEGRA20_MC_ISPW 44 +#define TEGRA20_MC_MPCOREW 45 +#define TEGRA20_MC_MPECSWR 46 +#define TEGRA20_MC_PPCSAHBDMAW 47 +#define TEGRA20_MC_PPCSAHBSLVW 48 +#define TEGRA20_MC_VDEBSEVW 49 +#define TEGRA20_MC_VDEMBEW 50 +#define TEGRA20_MC_VDETPMW 51 + #endif From patchwork Tue Jun 9 13:13:51 2020 Content-Type: text/plain; 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[79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:53 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 24/37] dt-bindings: memory: tegra30: Add memory client IDs Date: Tue, 9 Jun 2020 16:13:51 +0300 Message-Id: <20200609131404.17523-25-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Each memory client have a unique hardware ID, this patch adds these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif From patchwork Tue Jun 9 13:13:52 2020 Content-Type: text/plain; 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[79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 25/37] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Tue, 9 Jun 2020 16:13:52 +0300 Message-Id: <20200609131404.17523-26-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c3b8ad53b967..974048e83541 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -109,6 +109,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -126,6 +135,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -626,15 +644,17 @@ mc: memory-controller@7000f000 { interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Tue Jun 9 13:13:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92312C433DF for ; Tue, 9 Jun 2020 13:16:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71FF1207C3 for ; Tue, 9 Jun 2020 13:16:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EiGhSOh1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729898AbgFINQa (ORCPT ); Tue, 9 Jun 2020 09:16:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729332AbgFINPA (ORCPT ); Tue, 9 Jun 2020 09:15:00 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67931C08C5C5; Tue, 9 Jun 2020 06:14:58 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id c17so24952690lji.11; Tue, 09 Jun 2020 06:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AG+TQmILbbrHUh9/3fg4pGtkuDKOX+TOZbe0Aj0MBf0=; b=EiGhSOh1ZZPDLaZRrYIeHCwKkcNsouIcTJjk0UxCLEePd/J+r5pwQyDnLWuIeTo8cq gV/ci5m3Vqo4aYx143Z/Mzz9uozgdSH6gSl1TK3z0y/3VP1U3hPVMHRWHoYj6C5KYwda HroGQYKYI0+uAe1cm29/AeJ07m8HZKzojXdxbRujvQUuOgVxLWrHXRtSHD9IQVEaBMuE CJJOTef/97J7HEvFO6iicAJq/7/e8AY3fuCvYSQ2AsdLNPDDOCCHQMNqYh/yRrxCSjnF 2TpuG2F+JIqqL6kTkzDfCZ448ytMSV92/cOS2dmdXZer+G85yg9YyWrjGVr4Fabt2XoN UiLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AG+TQmILbbrHUh9/3fg4pGtkuDKOX+TOZbe0Aj0MBf0=; b=RE0eBTe4JpaVmIWYU8YJedzwLfGGT7mKRHikO7G2j4zoDU32bLBcpFhBlOQGenucuD hDwBFkZBJQxQWBavx3Ezld3BLEsAe4zauSvbBoJoY/noI+lZUR3k9dkccDQVgqAfu/oN 09T57/11wPN8g+dfE3Lpjb0XpqBGdYAMS7GzSFV1sNxQjTVunhm1LgFRa9oDMNkgxqR0 crJN+aKmbp25UjTqkhoCESixMnZZM9eSsj4xAjNHHF/8qMGNcIk9LUNBorOCBYW0JxbM 0/jhCcFBVnPG6IDUY0MjYc79haoYqnuOjFi0iKZd47F0IuZ2CJJtLQlbqvWd82IvBCRG Ps5g== X-Gm-Message-State: AOAM530as8/6XzaNPnmqqo6cFoUOcfNXRYnRGbDhBZtou8iZlP6eABGp rutQAfuHj6B2O0dRe3Y+yXI= X-Google-Smtp-Source: ABdhPJyiYfbTzP2nZhf3fgnnkhVUB7Ysq7mpxP+V8W5Yvzw4oCoUQgYrSVYyt565zMhI60iILUnTfQ== X-Received: by 2002:a2e:89da:: with SMTP id c26mr13060673ljk.447.1591708496791; Tue, 09 Jun 2020 06:14:56 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:56 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 26/37] ARM: tegra: Add interconnect properties to Tegra30 device-tree Date: Tue, 9 Jun 2020 16:13:53 +0300 Message-Id: <20200609131404.17523-27-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect properties to the memory controller, external memory controller and the display controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d2d05f1da274..2b183025629f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -208,6 +208,15 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, + <&mc TEGRA30_MC_DISPLAY0B &emc>, + <&mc TEGRA30_MC_DISPLAY0C &emc>, + <&mc TEGRA30_MC_DISPLAY1B &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -227,6 +236,15 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, + <&mc TEGRA30_MC_DISPLAY0BB &emc>, + <&mc TEGRA30_MC_DISPLAY0CB &emc>, + <&mc TEGRA30_MC_DISPLAY1BB &emc>; + interconnect-names = "display0a", + "display0b", + "display0c", + "display1b"; + rgb { status = "disabled"; }; @@ -733,15 +751,18 @@ mc: memory-controller@7000f000 { #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra30-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; nvidia,memory-controller = <&mc>; + + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Tue Jun 9 13:13:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A0DFC433DF for ; Tue, 9 Jun 2020 13:15:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D34AA20734 for ; Tue, 9 Jun 2020 13:15:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aC4glVDh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729047AbgFINPJ (ORCPT ); Tue, 9 Jun 2020 09:15:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729318AbgFINPA (ORCPT ); Tue, 9 Jun 2020 09:15:00 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0C04C05BD1E; Tue, 9 Jun 2020 06:14:59 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id z9so24953565ljh.13; Tue, 09 Jun 2020 06:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IaLwBgEJHAnRll2My7iiWFVAnwuWkHTJFbXmtwzd9MY=; b=aC4glVDhDS6ajEjF584IuzsxAMYQt4toyxqZK52jEcvULo8RhpSOxNphdBVi8P4OLv DLLzp/QJx/rbgkC6qG1/ST9kv+T/ES4KUlqW2rPtOO0Wph6Hs0Z1qgNv0uIgYfPZyEQI llyWxvYfnUXdL6kWcoCuZ/oZ4mbaCS7kAtLPhwpKjUcOfRUx/4ITmOaJcOV6P2sDgKD1 iU/pzZsNOp5pZLqWuj4uY2KzElystLbeKXihgwOOzUnCcTr5/E5sjMPqhFPjtwPOwYxv SylCskYpcyi9T2zgRF0lQBRLmg5udBC3dmOTS4p3B+WxlFyFBszPy/gE4DMm2ero/0pK 9nlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IaLwBgEJHAnRll2My7iiWFVAnwuWkHTJFbXmtwzd9MY=; b=M3jjeQU+sdjzohaLGHLHgwV0A4cRkZ0SAV0QAAFI9AgfwE7gGhn/nY8QM3RzvB868H LDW1nvN2GX8vPNxFTbNOLjvvuAfMuWffqFtmHNLYvIou3KYGmVdarz0jpmR5N2q3IqUL z1CJCAbzxbULNRuqXSmq0lpTGRooY7Yl2cTyJR1zThLrkhvg++xWh7EC6wX4HjaZ0B3D WHE8lOYj3tme0FGAQpWIjigDSfLTKDV8qY5pVe/LuRd4P45JemojH86O+wMXMVOEGCKa FEWh1QCAXoBrbDfpC5+2hgnL5se+jGRTLoP1QEIh8pt5I3tPBbGMIikkjXHIuVUCzRg1 dRvw== X-Gm-Message-State: AOAM530jliYBkttLeXl7ZlABUJ5aL4j4fYA1TF7l2xIdinC/4QoPSgjE Wvt7JI7KCiTezNYPebAUK4s7o4cy X-Google-Smtp-Source: ABdhPJwqzjarfix9XEE4prNh4Lc0nEjZ80Nvozu6vayHIphT+WuI7ooDdLSLgKJLy9OUPp/ATKnKnA== X-Received: by 2002:a2e:b4b3:: with SMTP id q19mr13086844ljm.90.1591708498010; Tue, 09 Jun 2020 06:14:58 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 27/37] interconnect: Relax requirement in of_icc_get_from_provider() Date: Tue, 9 Jun 2020 16:13:54 +0300 Message-Id: <20200609131404.17523-28-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Artur Świgoń This patch relaxes the condition in of_icc_get_from_provider() so that it is no longer required to set #interconnect-cells = <1> in the DT. In case of the devfreq driver for exynos-bus, #interconnect-cells is always zero. Signed-off-by: Artur Świgoń [digetx@gmail.com: added cells_num checking for of_icc_xlate_onecell()] Signed-off-by: Dmitry Osipenko --- drivers/interconnect/core.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index e5f998744501..cb143421ca67 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -339,7 +339,7 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) struct icc_node *node = ERR_PTR(-EPROBE_DEFER); struct icc_provider *provider; - if (!spec || spec->args_count != 1) + if (!spec) return ERR_PTR(-EINVAL); mutex_lock(&icc_lock); @@ -967,6 +967,15 @@ EXPORT_SYMBOL_GPL(icc_nodes_remove); */ int icc_provider_add(struct icc_provider *provider) { + struct device_node *np = provider->dev->of_node; + u32 cells_num; + int err; + + err = of_property_read_u32(np, "#interconnect-cells", &cells_num); + if (WARN_ON(err)) + return err; + if (WARN_ON(provider->xlate == of_icc_xlate_onecell && cells_num != 1)) + return -EINVAL; if (WARN_ON(!provider->set)) return -EINVAL; if (WARN_ON(!provider->xlate)) From patchwork Tue Jun 9 13:13:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC3B7C433E0 for ; Tue, 9 Jun 2020 13:16:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B395B20737 for ; Tue, 9 Jun 2020 13:16:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="q/Q3279A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729880AbgFINQ2 (ORCPT ); Tue, 9 Jun 2020 09:16:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729351AbgFINPC (ORCPT ); Tue, 9 Jun 2020 09:15:02 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDD71C03E97C; Tue, 9 Jun 2020 06:15:00 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id y11so23350788ljm.9; Tue, 09 Jun 2020 06:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZdqfFhous9LJ7xyXzWsP8eFwuiJA//aWLNwZ1NRylHU=; b=q/Q3279A8T1Aa8w1vceSd1gO393TTmCcEgws0BzThqIByXo/vuPlcJOPFWhCU0saMZ jv+ecsre/4BafUS4kfZlE10Zt6QK0Q1cI8tN2VfESJ3kly6ym3umTUd+LaLSZnNN6l1B RlL8EPg2JzZIsQbR+LInObnijGxqL+lY0er+vKCtenTFayHxRRhXYtZbRcp0aYkIVhNo qUdtEViVrn7vHLnD8qdQjY+4MJmcjIJN2lCYLkZ+ILmMwz7kJYvXbtjEGGOR9OVjwrp3 AAWGtqXxFDPyn0GKioovqBw7eDiL1oet5XNnBZwHcj8Vawu1Kpc4Gsny/0tTfY6+sa/e 7j0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZdqfFhous9LJ7xyXzWsP8eFwuiJA//aWLNwZ1NRylHU=; b=sBv0VIInHirLR4BOEfC8nbDNvtOfgZhH/FDxWFetFDXYcDW3DIi6mGaIx30YfRAis0 /mx2isaDg3CPXFS/9F1YgrdB1JSJVe9id5Q/jwVyfBl2B9+gXSgV5z14MMG683ZuuTM/ vboy8OZ4ymhtCnjvdXxN9xNHbsUvlvugwgWR+XAHoFcCOwu/5HqZHNphWIgXac6zfdJY EDkzhYA9wJykvCPbdx5zCOzYvfffYeQutITuUx6YJOUDhqZj//rubdwk/9Hk2LBNI9C+ hXG+rcGRbrJ08wA6BGq3KAaPWXIln1Qnv6gZBGBLTF/v90wMphEU3Edd6g1voS3UsTQn G0Pw== X-Gm-Message-State: AOAM532FXJ+SuBAu7zmWe2qn9AZNI9Q+4jGupV4GZ4rJMkpqzJZkQVV/ 7MigjsfjAfeA1qR9d+8NTQQ= X-Google-Smtp-Source: ABdhPJxjCGqibKAhYqx6jWx/A2rwQ6iUlJAF96095Hdmp5JKgJSYQXIyGUkLftZy5G4Cb3bXJazPAg== X-Received: by 2002:a05:651c:1044:: with SMTP id x4mr9579067ljm.409.1591708499227; Tue, 09 Jun 2020 06:14:59 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:14:58 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 28/37] memory: tegra: Register as interconnect provider Date: Tue, 9 Jun 2020 16:13:55 +0300 Message-Id: <20200609131404.17523-29-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Now memory controller is a memory interconnection provider. This allows us to use interconnect API in order to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/mc.c | 114 +++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 8 +++ include/soc/tegra/mc.h | 3 + 4 files changed, 126 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 5bf75b316a2f..7055fdef2c32 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -3,6 +3,7 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y depends on ARCH_TEGRA + select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 772aa021b5f6..7ef7ac9e103e 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -594,6 +594,118 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + return 0; +} + +static int tegra_mc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_onecell_data *data; + struct icc_node *node; + unsigned int num_nodes; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(mc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + num_nodes = mc->soc->num_clients; + + data = devm_kzalloc(mc->dev, struct_size(data, nodes, num_nodes), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + mc->provider.dev = mc->dev; + mc->provider.set = tegra_mc_icc_set; + mc->provider.data = data; + mc->provider.xlate = of_icc_xlate_onecell; + mc->provider.aggregate = tegra_mc_icc_aggregate; + + err = icc_provider_add(&mc->provider); + if (err) + goto err_msg; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < num_nodes; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); +del_provider: + icc_provider_del(&mc->provider); +err_msg: + dev_err(mc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -702,6 +814,8 @@ static int tegra_mc_probe(struct platform_device *pdev) } } + tegra_mc_interconnect_setup(mc); + return 0; } diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index afa3ba45c9e6..abeb6a2cc36a 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -115,4 +115,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra's ICC, the values are chosen + * such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_EMC 1000 +#define TEGRA_ICC_EMEM 2000 +#define TEGRA_ICC_MC 3000 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1238e35653d1..71de023f9f47 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -7,6 +7,7 @@ #define __SOC_TEGRA_MC_H__ #include +#include #include #include @@ -178,6 +179,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; From patchwork Tue Jun 9 13:13:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8222AC433E1 for ; Tue, 9 Jun 2020 13:15:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D14D2074B for ; Tue, 9 Jun 2020 13:15:53 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:15:02 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 31/37] memory: tegra20-emc: Register as interconnect provider Date: Tue, 9 Jun 2020 16:13:58 +0300 Message-Id: <20200609131404.17523-32-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Now memory controller is a memory interconnection provider. This allows us to use interconnect API in order to change memory configuration. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 110 +++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 6cd3d50145dc..ef0f5a69f24b 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -148,6 +149,7 @@ struct emc_timing { struct tegra_emc { struct device *dev; struct notifier_block clk_nb; + struct icc_provider provider; struct clk *clk; void __iomem *regs; @@ -661,6 +663,113 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node * +emc_of_icc_xlate(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id == TEGRA_ICC_EMEM) + return node; + } + + return ERR_PTR(-EINVAL); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long rate = icc_units_to_bps(dst->avg_bw); + unsigned int dram_data_bus_width_bytes = 4; + unsigned int ddr = 2; + int err; + + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = clk_set_min_rate(emc->clk, rate); + if (err) + return err; + + err = clk_set_rate(emc->clk, rate); + if (err) + return err; + + return 0; +} + +static int emc_icc_aggregate(struct icc_node *node, + u32 tag, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg = min((u64)avg_bw + (*agg_avg), (u64)U32_MAX); + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + struct icc_node *node; + int err; + + /* older device-trees don't have interconnect properties */ + if (!of_find_property(emc->dev->of_node, "#interconnect-cells", NULL)) + return 0; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.xlate = emc_of_icc_xlate; + emc->provider.aggregate = emc_icc_aggregate; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto del_provider; + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + err = PTR_ERR_OR_ZERO(node); + if (err) + goto remove_nodes; + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + static int tegra_emc_init_mc_timings(struct tegra_emc *emc) { struct tegra_mc_timing *timing; @@ -766,6 +875,7 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some From patchwork Tue Jun 9 13:14:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1770BC433DF for ; Tue, 9 Jun 2020 13:15:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7E5C207ED for ; Tue, 9 Jun 2020 13:15:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YfdrmR8+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729636AbgFINPq (ORCPT ); Tue, 9 Jun 2020 09:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729097AbgFINPH (ORCPT ); Tue, 9 Jun 2020 09:15:07 -0400 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8555C08C5C4; Tue, 9 Jun 2020 06:15:06 -0700 (PDT) Received: by mail-lj1-x243.google.com with SMTP id a9so21432232ljn.6; Tue, 09 Jun 2020 06:15:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tBJCplGhLIr24UMQ5QWC+yX2Aq7GS8Qdhh51vOCv+Fo=; b=YfdrmR8+bDHqkjeC4uKTJ5SfBXCYYq9tKkjD6LLQ/KWTgLvccoblWEZvVMmOJgNUQW yhna0ZQ2wTmP0zb72B313sOCkye+v8ngFV0ACPv63pDPymxM9EV1I/BB6XAk+jw4AEnw 8ziPfrb3maHCNCLZvCIoaYXpoXwGdKWtdvk7L3fA69n+mdFZIxDzNI4RQ+NlbTiZyLLY zgdGFkpK0LFJlAh6+kHzsloU/uiyQn/7vSdehhWuN6CHy/8D59reGUo7szSdY2d9NymF BnT//xnb6SwkF9pQHNC+8H/6MQuaRKC0T/qUPu9WuJZ4UDx2Q7XpwQCjYYx/U/FbRcHj KWTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tBJCplGhLIr24UMQ5QWC+yX2Aq7GS8Qdhh51vOCv+Fo=; b=RWGxIf49HThndNskARaAum4CZnQekNNPzsxUeX0gRjpb12Xtyw0IbYQL+JBqfPXGei gvUL6yUdoVMe/FXYNuf91XhNrwEcC0JEgHdItPlIQUM+511K5ftxMtCICVXuw9BHeYy/ HQhCvuh2m3zJpPTMSwGz65A3GlTCmYMdxSk4av5yFhWUmyPKGpWr6jRVev7b+Gq6vFTn R2MLczeaAd0qr+ZiEt5Rj545gegFGO7c/EYoIXpSVqw1MOTlx1Z/evB2W2a6PFyr6/6z 2Rk15RsiNWzvoB7deCoX0QaQOkpJ7bLwueXC4TRyJcU7WMSnIpeheRVPLnpMxzUn0E4u o1ug== X-Gm-Message-State: AOAM5306SXrRF8FrrDOPAy1ZIh4+88bz2ynHKSfimzD0p2+oP1lkuRPx a4YF9VvYbvFOy26lg39Lo9s= X-Google-Smtp-Source: ABdhPJzNyecHovhlUVhrBdJOpBTvH0mJxqq/5f5UqhaEKubxRG53/Ij7m4LrZV7osBBZOUCPJsDegQ== X-Received: by 2002:a2e:1311:: with SMTP id 17mr13650703ljt.122.1591708505387; Tue, 09 Jun 2020 06:15:05 -0700 (PDT) Received: from localhost.localdomain (79-139-237-54.dynamic.spd-mgts.ru. [79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:15:04 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 33/37] memory: tegra30-emc: Continue probing if timings are missing in device-tree Date: Tue, 9 Jun 2020 16:14:00 +0300 Message-Id: <20200609131404.17523-34-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30-emc.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 85d4effb8e6f..f6c688bfe41f 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -988,6 +988,11 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + ram_code = tegra_read_ram_code(); for_each_child_of_node(dev->of_node, np) { @@ -1057,6 +1062,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -1263,12 +1271,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int err; - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "device-tree node doesn't have memory timings\n"); - return -ENODEV; - } - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); if (!np) { dev_err(&pdev->dev, "could not get memory controller node\n"); @@ -1280,10 +1282,6 @@ static int tegra_emc_probe(struct platform_device *pdev) if (!mc) return -ENOENT; - np = emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); if (!emc) { of_node_put(np); @@ -1297,10 +1295,13 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; - err = emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) From patchwork Tue Jun 9 13:14:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B22AC433E1 for ; Tue, 9 Jun 2020 13:15:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E82BA2074B for ; Tue, 9 Jun 2020 13:15:45 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:15:07 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 35/37] drm/tegra: dc: Support memory bandwidth management Date: Tue, 9 Jun 2020 16:14:02 +0300 Message-Id: <20200609131404.17523-36-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. This patch wires up the interconnect API support to the DC driver. Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/Kconfig | 1 + drivers/gpu/drm/tegra/dc.c | 271 +++++++++++++++++++++++++++++++++- drivers/gpu/drm/tegra/dc.h | 8 + drivers/gpu/drm/tegra/drm.c | 19 +++ drivers/gpu/drm/tegra/plane.c | 1 + drivers/gpu/drm/tegra/plane.h | 4 +- 6 files changed, 300 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig index 5043dcaf1cf9..1650a448eabd 100644 --- a/drivers/gpu/drm/tegra/Kconfig +++ b/drivers/gpu/drm/tegra/Kconfig @@ -9,6 +9,7 @@ config DRM_TEGRA select DRM_MIPI_DSI select DRM_PANEL select TEGRA_HOST1X + select INTERCONNECT select IOMMU_IOVA select CEC_CORE if CEC_NOTIFIER help diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 83f31c6e891c..12b318bb8475 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -519,6 +519,136 @@ static void tegra_dc_setup_window(struct tegra_plane *plane, tegra_plane_setup_blending(plane, window); } +static unsigned long +tegra_plane_memory_bandwidth(struct drm_plane_state *state, + struct tegra_dc_window *window, + unsigned int num, + unsigned int denum) +{ + struct tegra_plane_state *tegra_state; + struct drm_crtc_state *crtc_state; + const struct drm_format_info *fmt; + struct tegra_dc_window win; + unsigned long long bandwidth; + unsigned int bpp_plane; + unsigned int bpp; + unsigned int mul; + unsigned int i; + + if (!state->fb || !state->visible) + return 0; + + crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); + tegra_state = to_tegra_plane_state(state); + + if (!window) + window = &win; + + window->src.w = drm_rect_width(&state->src) >> 16; + window->src.h = drm_rect_height(&state->src) >> 16; + window->dst.w = drm_rect_width(&state->dst); + window->dst.h = drm_rect_height(&state->dst); + window->tiling = tegra_state->tiling; + + fmt = state->fb->format; + + /* + * Note that real memory bandwidth vary depending on format and + * memory layout, we are not taking that into account because small + * estimation error isn't important since bandwidth is rounded up + * anyway. + */ + for (i = 0, bpp = 0; i < fmt->num_planes; i++) { + bpp_plane = fmt->cpp[i] * 8; + + /* + * Sub-sampling is relevant for chroma planes only and vertical + * readouts are not cached, hence only horizontal sub-sampling + * matters. + */ + if (i > 0) + bpp_plane /= fmt->hsub; + + bpp += bpp_plane; + } + + /* + * Horizontal downscale takes extra bandwidth which roughly depends + * on the scaled width. + */ + if (window->src.w > window->dst.w) + mul = (window->src.w - window->dst.w) * bpp / 2048 + 1; + else + mul = 1; + + /* + * Ignore cursor window if its width is small enough such that + * data-prefetch FIFO will easily help to overcome temporal memory + * pressure. + * + * Window A has a 128bit x 128 deep read FIFO, while windows B/C + * have a 128bit x 64 deep read FIFO. + * + * This allows us to not overestimate memory frequency requirement. + * Even if it will happen that cursor gets a temporal underflow, this + * won't be fatal. + */ + if (state->plane->type == DRM_PLANE_TYPE_CURSOR && + mul == 1 && window->src.w * bpp <= 128 * 16) + return 0; + + /* mode.clock in kHz, bandwidth in kbit/s */ + bandwidth = kbps_to_icc(crtc_state->mode.clock * bpp * mul); + + /* the requested bandwidth should be higher than required */ + bandwidth *= num; + do_div(bandwidth, denum); + + return min_t(u64, bandwidth, ULONG_MAX); +} + +static unsigned long +tegra20_plane_memory_bandwidth(struct drm_plane_state *state) +{ + return tegra_plane_memory_bandwidth(state, NULL, 29, 10); +} + +static unsigned long +tegra30_plane_memory_bandwidth(struct drm_plane_state *state) +{ + struct tegra_dc_window window; + unsigned long bandwidth; + + bandwidth = tegra_plane_memory_bandwidth(state, &window, 29, 10); + + /* x2: memory overfetch for tiled framebuffer and DDR3 */ + if (window.tiling.mode == TEGRA_BO_TILING_MODE_TILED) + bandwidth *= 2; + + return bandwidth; +} + +static unsigned long +tegra114_plane_memory_bandwidth(struct drm_plane_state *state) +{ + struct tegra_dc_window window; + unsigned long bandwidth; + + bandwidth = tegra_plane_memory_bandwidth(state, &window, 12, 10); + + /* x2: memory overfetch for tiled framebuffer and DDR3 */ + if (window.tiling.mode == TEGRA_BO_TILING_MODE_TILED) + bandwidth *= 2; + + return bandwidth; +} + +static unsigned long +tegra124_plane_memory_bandwidth(struct drm_plane_state *state) +{ + return tegra_plane_memory_bandwidth(state, NULL, 12, 10); +} + static const u32 tegra20_primary_formats[] = { DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB1555, @@ -608,8 +738,10 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, int err; /* no need for further checks if the plane is being disabled */ - if (!state->crtc) + if (!state->crtc) { + plane_state->memory_bandwidth = 0; return 0; + } err = tegra_plane_format(state->fb->format->format, &plane_state->format, @@ -662,6 +794,8 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, if (err < 0) return err; + plane_state->memory_bandwidth = dc->soc->plane_memory_bandwidth(state); + return 0; } @@ -1186,6 +1320,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) copy->pclk = state->pclk; copy->div = state->div; copy->planes = state->planes; + copy->memory_bandwidth = state->memory_bandwidth; return ©->base; } @@ -1768,6 +1903,8 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, err = host1x_client_suspend(&dc->client); if (err < 0) dev_err(dc->dev, "failed to suspend: %d\n", err); + + icc_set_bw(dc->icc_bandwidth, 0, 0); } static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, @@ -1779,6 +1916,9 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, u32 value; int err; + icc_set_bw(dc->icc_bandwidth, state->memory_bandwidth, + state->memory_bandwidth); + err = host1x_client_resume(&dc->client); if (err < 0) { dev_err(dc->dev, "failed to resume: %d\n", err); @@ -1892,6 +2032,9 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { + struct tegra_dc_state *dc_old_state = to_dc_state(old_crtc_state); + struct tegra_dc_state *dc_state = to_dc_state(crtc->state); + struct tegra_dc *dc = to_tegra_dc(crtc); unsigned long flags; if (crtc->state->event) { @@ -1906,6 +2049,25 @@ static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, crtc->state->event = NULL; } + + if (old_crtc_state && old_crtc_state->active) { + /* + * Raise memory bandwidth before changes take effect if it + * goes from low to high. + */ + if (dc_old_state->memory_bandwidth < dc_state->memory_bandwidth) + icc_set_bw(dc->icc_bandwidth, + dc_state->memory_bandwidth, + dc_state->memory_bandwidth); + } else { + /* + * Raise memory bandwidth before changes take effect if + * CRTC is turning on. + */ + icc_set_bw(dc->icc_bandwidth, + dc_state->memory_bandwidth, + dc_state->memory_bandwidth); + } } static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, @@ -1924,7 +2086,80 @@ static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); } +static bool +tegra_plane_overlaps_other_plane(struct drm_crtc_state *state, + const struct drm_plane_state *plane_state) +{ + const struct drm_plane_state *other_state; + struct drm_plane *plane; + struct drm_rect rect; + + drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { + rect = plane_state->dst; + + if (other_state == plane_state) + continue; + + if (!other_state->visible || !other_state->fb) + continue; + + if (drm_rect_intersect(&rect, &other_state->dst)) + return true; + } + + return false; +} + +static int tegra_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct tegra_dc_state *dc_state = to_dc_state(state); + const struct drm_plane_state *plane_state; + const struct tegra_plane_state *tegra; + unsigned long long bandwidth = 0; + struct drm_plane *plane; + + /* + * For overlapping planes pixel's data is fetched for each plane at + * the same time, hence bandwidth is accumulated in this case. + */ + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) { + tegra = to_tegra_plane_state(plane_state); + + if (tegra_plane_overlaps_other_plane(state, plane_state)) + bandwidth += tegra->memory_bandwidth; + else + bandwidth = max_t(u64, bandwidth, + tegra->memory_bandwidth); + } + + dc_state->memory_bandwidth = min_t(u64, bandwidth, U32_MAX); + + return 0; +} + +void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) +{ + struct tegra_dc_state *dc_old_state = to_dc_state(old_crtc_state); + struct tegra_dc_state *dc_state = to_dc_state(crtc->state); + struct tegra_dc *dc = to_tegra_dc(crtc); + + if (!dc_old_state) + return; + + /* + * Drop memory bandwidth after changes take effect if it goes from + * high to low. + */ + if (dc_old_state->memory_bandwidth > dc_state->memory_bandwidth) + icc_set_bw(dc->icc_bandwidth, + dc_state->memory_bandwidth, + dc_state->memory_bandwidth); +} + static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { + .atomic_check = tegra_crtc_atomic_check, .atomic_begin = tegra_crtc_atomic_begin, .atomic_flush = tegra_crtc_atomic_flush, .atomic_enable = tegra_crtc_atomic_enable, @@ -2216,6 +2451,7 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { .modifiers = tegra20_modifiers, .has_win_a_without_filters = true, .has_win_c_without_vert_filter = true, + .plane_memory_bandwidth = tegra20_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra30_dc_soc_info = { @@ -2235,6 +2471,7 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { .modifiers = tegra20_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra30_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra114_dc_soc_info = { @@ -2254,6 +2491,7 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { .modifiers = tegra20_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra114_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra124_dc_soc_info = { @@ -2273,6 +2511,7 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { .modifiers = tegra124_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct tegra_dc_soc_info tegra210_dc_soc_info = { @@ -2292,6 +2531,7 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { .modifiers = tegra124_modifiers, .has_win_a_without_filters = false, .has_win_c_without_vert_filter = false, + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { @@ -2340,6 +2580,7 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { .has_nvdisplay = true, .wgrps = tegra186_dc_wgrps, .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { @@ -2388,6 +2629,7 @@ static const struct tegra_dc_soc_info tegra194_dc_soc_info = { .has_nvdisplay = true, .wgrps = tegra194_dc_wgrps, .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), + .plane_memory_bandwidth = tegra124_plane_memory_bandwidth, }; static const struct of_device_id tegra_dc_of_match[] = { @@ -2494,6 +2736,7 @@ static int tegra_dc_couple(struct tegra_dc *dc) static int tegra_dc_probe(struct platform_device *pdev) { + const char *level = KERN_ERR; struct tegra_dc *dc; int err; @@ -2562,8 +2805,6 @@ static int tegra_dc_probe(struct platform_device *pdev) err = tegra_dc_rgb_probe(dc); if (err < 0 && err != -ENODEV) { - const char *level = KERN_ERR; - if (err == -EPROBE_DEFER) level = KERN_DEBUG; @@ -2572,6 +2813,25 @@ static int tegra_dc_probe(struct platform_device *pdev) return err; } + /* + * The display controller memory bandwidth management isn't trivial + * because it requires the knowledge about the DC hardware state + * in order to make a proper decisions. It's not easy to convey + * that information to the ICC provider, so we will just use the + * first interconnect path for the memory bandwidth management and + * make all the decisions within the DC driver, for simplicity. + */ + dc->icc_bandwidth = of_icc_get(dc->dev, "display0a"); + err = PTR_ERR_OR_ZERO(dc->icc_bandwidth); + if (err) { + if (err == -EPROBE_DEFER) + level = KERN_DEBUG; + + dev_printk(level, dc->dev, + "failed to get display0a interconnect: %d\n", err); + goto remove_rgb; + } + platform_set_drvdata(pdev, dc); pm_runtime_enable(&pdev->dev); @@ -2590,6 +2850,9 @@ static int tegra_dc_probe(struct platform_device *pdev) disable_pm: pm_runtime_disable(&pdev->dev); + icc_put(dc->icc_bandwidth); + +remove_rgb: tegra_dc_rgb_remove(dc); return err; @@ -2607,6 +2870,8 @@ static int tegra_dc_remove(struct platform_device *pdev) return err; } + icc_put(dc->icc_bandwidth); + err = tegra_dc_rgb_remove(dc); if (err < 0) { dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 3d8ddccd758f..3a0ff57c5169 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -8,6 +8,7 @@ #define TEGRA_DC_H 1 #include +#include #include @@ -23,6 +24,8 @@ struct tegra_dc_state { unsigned int div; u32 planes; + + unsigned long memory_bandwidth; }; static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) @@ -66,6 +69,7 @@ struct tegra_dc_soc_info { const u64 *modifiers; bool has_win_a_without_filters; bool has_win_c_without_vert_filter; + unsigned long (*plane_memory_bandwidth)(struct drm_plane_state *state); }; struct tegra_dc { @@ -90,6 +94,8 @@ struct tegra_dc { struct drm_info_list *debugfs_files; const struct tegra_dc_soc_info *soc; + + struct icc_path *icc_bandwidth; }; static inline struct tegra_dc * @@ -150,6 +156,8 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, struct drm_crtc_state *crtc_state, struct clk *clk, unsigned long pclk, unsigned int div); +void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state); /* from rgb.c */ int tegra_dc_rgb_probe(struct tegra_dc *dc); diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 211906347f3f..81e58f90f5c9 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -20,6 +20,7 @@ #include #include +#include "dc.h" #include "drm.h" #include "gem.h" @@ -59,6 +60,22 @@ static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { .atomic_commit = drm_atomic_helper_commit, }; +static void tegra_atomic_post_commit(struct drm_device *drm, + struct drm_atomic_state *old_state) +{ + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct drm_crtc *crtc; + unsigned int i; + + for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, + new_crtc_state, i) { + if (!new_crtc_state->active) + continue; + + tegra_crtc_atomic_post_commit(crtc, old_crtc_state); + } +} + static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *drm = old_state->dev; @@ -75,6 +92,8 @@ static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) } else { drm_atomic_helper_commit_tail_rpm(old_state); } + + tegra_atomic_post_commit(drm, old_state); } static const struct drm_mode_config_helper_funcs diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 9ccfb56e9b01..f94925744105 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -63,6 +63,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) copy->swap = state->swap; copy->bottom_up = state->bottom_up; copy->opaque = state->opaque; + copy->memory_bandwidth = state->memory_bandwidth; for (i = 0; i < 2; i++) copy->blending[i] = state->blending[i]; diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h index a158a915109a..5227c7a9ad8b 100644 --- a/drivers/gpu/drm/tegra/plane.h +++ b/drivers/gpu/drm/tegra/plane.h @@ -51,10 +51,12 @@ struct tegra_plane_state { /* used for legacy blending support only */ struct tegra_plane_legacy_blending_state blending[2]; bool opaque; + + unsigned long memory_bandwidth; }; static inline struct tegra_plane_state * -to_tegra_plane_state(struct drm_plane_state *state) +to_tegra_plane_state(const struct drm_plane_state *state) { if (state) return container_of(state, struct tegra_plane_state, base); From patchwork Tue Jun 9 13:14:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 211845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88E85C433E0 for ; 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[79.139.237.54]) by smtp.gmail.com with ESMTPSA id l22sm4323522lji.120.2020.06.09.06.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2020 06:15:08 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen Cc: =?utf-8?b?QXJ0dXIgxZp3aWdvxYQ=?= , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v4 36/37] drm/tegra: dc: Tune up high priority request controls for Tegra20 Date: Tue, 9 Jun 2020 16:14:03 +0300 Message-Id: <20200609131404.17523-37-digetx@gmail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200609131404.17523-1-digetx@gmail.com> References: <20200609131404.17523-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tegra20 has a high-priority-request control that allows to configure when display's memory client should perform read requests with a higher priority (Tegra30+ uses other means like Latency Allowance). This patch changes the controls configuration in order to get a more aggressive memory prefetching, which allows to reliably avoid FIFO underflow when running on a lower memory frequency. This allow us safely drop the memory bandwidth requirement by about two times in a most popular use-cases (only one display active, video overlay inactive, no scaling is done). Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/dc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 12b318bb8475..48dad375b470 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1971,12 +1971,12 @@ static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); /* initialize timer */ - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | - WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x70) | + WINDOW_B_THRESHOLD(0x30) | WINDOW_C_THRESHOLD(0x70); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); - value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | - WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); + value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0) | + WINDOW_B_THRESHOLD(0) | WINDOW_C_THRESHOLD(0); tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |