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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:41 -0700 Message-Id: <20170906160612.22769-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PULL 01/32] tcg: Add generic DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This will allow some amount of cleanup to happen before switching the backends over to enum DisasJumpType. Reviewed-by: Emilio G. Cota Reviewed-by: Lluís Vilanova Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 1 + 1 file changed, 1 insertion(+) -- 2.13.5 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 440fc31b37..b434988979 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -63,6 +63,7 @@ typedef ram_addr_t tb_page_addr_t; #define DISAS_JUMP 1 /* only pc was modified dynamically */ #define DISAS_TB_JUMP 2 /* only pc was modified statically */ #define DISAS_UPDATE 3 /* cpu state was modified dynamically */ +#define DISAS_NORETURN 4 /* the tb has already been exited */ #include "qemu/log.h" From patchwork Wed Sep 6 16:05:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111799 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1113898qge; Wed, 6 Sep 2017 09:06:51 -0700 (PDT) X-Received: by 10.237.60.239 with SMTP id e44mr4452797qtf.310.1504714011406; Wed, 06 Sep 2017 09:06:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714011; cv=none; d=google.com; s=arc-20160816; b=QCC/pizmlG6mTwdXE9igP3fInCWKdYpXNlAyDC/VxySCs3nBPCBnpD38uuBBOUVHM2 Flz14ZgK3M6N3FE1XbLchEvrIo0k0dudAck97gs4qiUFKn0v7UuXVMT1/r0Q1cl1QTsa 9xt4oitn+BJzn6fdyuSeFPmLrbdCLqjyPGwNcQ6RzGkGya1vrKVugWL/GL0IKLYzNnsm Z4VqJqHndRC5AygznVAevyv7R4/ttkkfAo7RZ6fg/sUd4aqlUJOkEcyuijOJ8pNPeg5i EVhYbkfVCZMsZrMVQdhGfQYX6K2Ht/UpFqh5dq/Z5A48fKN4N2QoQx3YVfCIhULolpB7 gZFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oktER+wQnBzv+YFYPe9eDSwDzOT9j+VLlJ0DA6KaCfc=; b=Mi+WjglGM2URt8oQLgDu9cyLZf0reQvKyvIQ2j1j3/Bhzu2fPh7awnQ8hmyUxca34Y p3CBfFnP3QCwgFeppwCcmCCGhd/cwCf2o/4ztnUcl4MtFITXBOmbPWeZ+e+P2KCIDECf a+83Jq2OHWjbvYiij6QP9uwQnLUIKXt3LJej0tCSYhYOUj3lPXrfGN35FGq/e3kAJfy6 i2Jt4hK54HkTUi6MROCAyc7pjwf4kt6ejsEOwDkdelTXauMVmFAXIMGaaCK1v/FHYho8 ZtagcboV3/vt3JX+tdY8dqzuGIkhOjePeTEfR+sbLO0dFLUDLA9mF+Io+SaUjYJ5p+ue Dxvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QP4/mR22; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:42 -0700 Message-Id: <20170906160612.22769-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL 02/32] target/i386: Use generic DISAS_* enumerators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This target is not sophisticated in its use of cleanups at the end of the translation loop. For the most part, any condition that exits the TB is dealt with by emitting the exiting opcode right then and there. Therefore the only is_jmp indicator that is needed is DISAS_NORETURN. For two stack segment modifying cases, we have not yet exited the TB (therefore DISAS_NORETURN feels wrong), but intend to exit. The caller of gen_movl_seg_T0 currently checks for any non-zero value, therefore DISAS_TOO_MANY seems acceptable for that usage. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/i386/translate.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index 5fdadf98cf..26e8002433 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -31,6 +31,7 @@ #include "trace-tcg.h" #include "exec/log.h" +#define DISAS_TOO_MANY 5 #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 @@ -2153,6 +2154,7 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + s->is_jmp = DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2173,7 +2175,6 @@ static inline void gen_jcc(DisasContext *s, int b, gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp = DISAS_TB_JUMP; } else { l1 = gen_new_label(); l2 = gen_new_label(); @@ -2243,12 +2244,14 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) - s->is_jmp = DISAS_TB_JUMP; + if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) { + s->is_jmp = DISAS_TOO_MANY; + } } else { gen_op_movl_seg_T0_vm(seg_reg); - if (seg_reg == R_SS) - s->is_jmp = DISAS_TB_JUMP; + if (seg_reg == R_SS) { + s->is_jmp = DISAS_TOO_MANY; + } } } @@ -2420,7 +2423,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } /* Generate #UD for the current instruction. The assumption here is that @@ -2458,7 +2461,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2466,7 +2469,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2541,7 +2544,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } static inline void @@ -2580,7 +2583,6 @@ static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) set_cc_op(s, CC_OP_DYNAMIC); if (s->jmp_opt) { gen_goto_tb(s, tb_num, eip); - s->is_jmp = DISAS_TB_JUMP; } else { gen_jmp_im(eip); gen_eob(s); @@ -6943,7 +6945,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7188,7 +7190,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } break; case 0x100: @@ -7371,7 +7373,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; break; case 0xd9: /* VMMCALL */ From patchwork Wed Sep 6 16:05:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111806 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1119085qge; Wed, 6 Sep 2017 09:09:58 -0700 (PDT) X-Received: by 10.200.8.225 with SMTP id y30mr4176848qth.233.1504714198953; Wed, 06 Sep 2017 09:09:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714198; cv=none; d=google.com; s=arc-20160816; b=RgqqID12Yxl9Rd0jVuaVyPVeRgcflwndydXttY9/idkmqhUCAJgcuR5leyc/oamzjV Uwza0jDwVKV+EhcdqCzzjfxaKmSxAieJc72zflGhTymeAfwwr7AnttiimWz9+DYk+dg+ p2P7bnUXescVfZbLvlBJRZYY9gzoviwOSzN7LcE6xDOh1z8yKDbJD57O2W7N4aMPQywS jXPuzv7nK2T/ilK4p2sZZC/FRNOm6UUg/Od+fsg42ELsne8NbzmAo3tRTwIdB7X0nflU A8WRYeSIrBtksm1eleoq4yjS4X4NKykbet0u7huXSZH7GL2t29Rhn881G3+th5TNgQWV ol5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=l+8GeftkxPUaXtKmP8H3x4UyaNFhwhYJYRyE/2Xhemc=; b=wjDRkOFF74w5h3NzvrDzJLat31rKa5HgKG6Dw4+GSVZuenEXZOAu/hUsDxUzzgDj7A YZv8C/Y7d2vIrRAs3210EDdlzgkiTXnffOUzWFFEBqLZpWxECRrmGJm26fWuR4FVlDuX 59hHLA6V0ifyaZb6xyANuTd78RtIpmqA+kt00QIat/QN1gWlIXimAlxFNUUJB63pDy8b Ah2JUjFWkhA13BjAE6rNFszUKbQrA4iK+PZZ3DeB9Le/7IE/x/ZxKEBZ7j80p41Yagm4 pwKMgBg11FAyxRE3XSPanAyoVqqwcGz1bQCsAAZ8EclDdfwcgPaka+F6UXe1zMQrFBjd nqaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=J/SiTef0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:43 -0700 Message-Id: <20170906160612.22769-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL 03/32] target/arm: Use DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 ++------ target/arm/translate-a64.c | 37 ++++++++++++++++++++----------------- target/arm/translate.c | 14 ++++++++------ 3 files changed, 30 insertions(+), 29 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.h b/target/arm/translate.h index 2fe144baa9..90f64d9716 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,12 +124,8 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 4 -#define DISAS_SWI 5 -/* For instructions which unconditionally cause an exception we can skip - * emitting unreachable code at the end of the TB in the A64 decoder - */ -#define DISAS_EXC 6 +#define DISAS_WFI 5 +#define DISAS_SWI 6 /* WFE */ #define DISAS_WFE 7 #define DISAS_HVC 8 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cb44632d16..881d3c0cbb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp = DISAS_EXC; + s->is_jmp = DISAS_NORETURN; } static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp = DISAS_EXC; + s->is_jmp = DISAS_NORETURN; } static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp = DISAS_EXC; + s->is_jmp = DISAS_NORETURN; } static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -371,7 +371,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { @@ -380,7 +380,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } } } @@ -11326,7 +11326,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) assert(num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp = DISAS_EXC; + dc->is_jmp = DISAS_NORETURN; break; } @@ -11353,21 +11353,25 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) gen_io_end(); } - if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->is_jmp != DISAS_EXC) { + if (unlikely(cs->singlestep_enabled || dc->ss_active)) { /* Note that this means single stepping WFI doesn't halt the CPU. * For conditional branch insns this is harmless unreachable code as * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - assert(dc->is_jmp != DISAS_TB_JUMP); - if (dc->is_jmp != DISAS_JUMP) { + switch (dc->is_jmp) { + default: gen_a64_set_pc_im(dc->pc); - } - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); + /* fall through */ + case DISAS_JUMP: + if (cs->singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; } } else { switch (dc->is_jmp) { @@ -11377,8 +11381,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(cpu_pc); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: case DISAS_SWI: break; case DISAS_WFE: diff --git a/target/arm/translate.c b/target/arm/translate.c index e52a6d7622..b14329dc27 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp = DISAS_EXC; + s->is_jmp = DISAS_NORETURN; } static void gen_singlestep_exception(DisasContext *s) @@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp = DISAS_EXC; + s->is_jmp = DISAS_NORETURN; } static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1193,7 +1193,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp = DISAS_EXC; + s->is_jmp = DISAS_NORETURN; } /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -11974,7 +11974,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp = DISAS_EXC; + dc->is_jmp = DISAS_NORETURN; break; } #endif @@ -12119,6 +12119,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ gen_singlestep_exception(dc); + break; + case DISAS_NORETURN: + break; } } else { /* While branches must always occur at the end of an IT block, @@ -12143,8 +12146,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) /* indicate that the hash table must be used to find the next TB */ tcg_gen_exit_tb(0); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: /* nothing more to generate */ break; case DISAS_WFI: From patchwork Wed Sep 6 16:05:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111801 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1114332qge; Wed, 6 Sep 2017 09:07:06 -0700 (PDT) X-Received: by 10.200.28.123 with SMTP id j56mr4160291qtk.299.1504714026135; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:44 -0700 Message-Id: <20170906160612.22769-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 04/32] target: [tcg] Use a generic enum for DISAS_ values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 30 ------------------------------ include/exec/translator.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/arm/translate.h | 23 ++++++++++++++--------- target/arm/translate.c | 2 +- target/cris/translate.c | 7 ++++++- target/i386/translate.c | 3 +-- target/lm32/translate.c | 6 ++++++ target/m68k/translate.c | 7 ++++++- target/microblaze/translate.c | 6 ++++++ target/nios2/translate.c | 6 ++++++ target/openrisc/translate.c | 6 ++++++ target/s390x/translate.c | 3 ++- target/unicore32/translate.c | 7 ++++++- target/xtensa/translate.c | 4 ++++ 14 files changed, 104 insertions(+), 46 deletions(-) create mode 100644 include/exec/translator.h -- 2.13.5 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b434988979..ff8fbe423d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -35,36 +35,6 @@ typedef abi_ulong tb_page_addr_t; typedef ram_addr_t tb_page_addr_t; #endif -/* DisasContext is_jmp field values - * - * is_jmp starts as DISAS_NEXT. The translator will keep processing - * instructions until an exit condition is reached. If we reach the - * exit condition and is_jmp is still DISAS_NEXT (because of some - * other condition) we simply "jump" to the next address. - * The remaining exit cases are: - * - * DISAS_JUMP - Only the PC was modified dynamically (e.g computed) - * DISAS_TB_JUMP - Only the PC was modified statically (e.g. branch) - * - * In these cases as long as the PC is updated we can chain to the - * next TB either by exiting the loop or looking up the next TB via - * the loookup helper. - * - * DISAS_UPDATE - CPU State was modified dynamically - * - * This covers any other CPU state which necessities us exiting the - * TCG code to the main run-loop. Typically this includes anything - * that might change the interrupt state. - * - * Individual translators may define additional exit cases to deal - * with per-target special conditions. - */ -#define DISAS_NEXT 0 /* next instruction can be analyzed */ -#define DISAS_JUMP 1 /* only pc was modified dynamically */ -#define DISAS_TB_JUMP 2 /* only pc was modified statically */ -#define DISAS_UPDATE 3 /* cpu state was modified dynamically */ -#define DISAS_NORETURN 4 /* the tb has already been exited */ - #include "qemu/log.h" void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); diff --git a/include/exec/translator.h b/include/exec/translator.h new file mode 100644 index 0000000000..b51b8f8a4e --- /dev/null +++ b/include/exec/translator.h @@ -0,0 +1,40 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Lluís Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC__TRANSLATOR_H +#define EXEC__TRANSLATOR_H + +/** + * DisasJumpType: + * @DISAS_NEXT: Next instruction in program order. + * @DISAS_TOO_MANY: Too many instructions translated. + * @DISAS_NORETURN: Following code is dead. + * @DISAS_TARGET_*: Start of target-specific conditions. + * + * What instruction to disassemble next. + */ +typedef enum DisasJumpType { + DISAS_NEXT, + DISAS_TOO_MANY, + DISAS_NORETURN, + DISAS_TARGET_0, + DISAS_TARGET_1, + DISAS_TARGET_2, + DISAS_TARGET_3, + DISAS_TARGET_4, + DISAS_TARGET_5, + DISAS_TARGET_6, + DISAS_TARGET_7, + DISAS_TARGET_8, + DISAS_TARGET_9, + DISAS_TARGET_10, + DISAS_TARGET_11, +} DisasJumpType; + +#endif /* EXEC__TRANSLATOR_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 90f64d9716..1eb432dc2c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H +#include "exec/translator.h" + + /* internal defines */ typedef struct DisasContext { target_ulong pc; @@ -119,29 +122,31 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) s->insn_start_idx = 0; } -/* target-specific extra values for is_jmp */ +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 5 -#define DISAS_SWI 6 +#define DISAS_WFI DISAS_TARGET_2 +#define DISAS_SWI DISAS_TARGET_3 /* WFE */ -#define DISAS_WFE 7 -#define DISAS_HVC 8 -#define DISAS_SMC 9 -#define DISAS_YIELD 10 +#define DISAS_WFE DISAS_TARGET_4 +#define DISAS_HVC DISAS_TARGET_5 +#define DISAS_SMC DISAS_TARGET_6 +#define DISAS_YIELD DISAS_TARGET_7 /* M profile branch which might be an exception return (and so needs * custom end-of-TB code) */ -#define DISAS_BX_EXCRET 11 +#define DISAS_BX_EXCRET DISAS_TARGET_8 /* For instructions which want an immediate exit to the main loop, * as opposed to attempting to use lookup_and_goto_ptr. Unlike * DISAS_UPDATE this doesn't write the PC on exiting the translation * loop so you need to ensure something (gen_a64_set_pc_im or runtime * helper) has done so before we reach return from cpu_tb_exec. */ -#define DISAS_EXIT 12 +#define DISAS_EXIT DISAS_TARGET_9 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target/arm/translate.c b/target/arm/translate.c index b14329dc27..0c39c2b996 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4174,7 +4174,7 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp = DISAS_TB_JUMP; + s->is_jmp = DISAS_NORETURN; } static inline void gen_jmp (DisasContext *s, uint32_t dest) diff --git a/target/cris/translate.c b/target/cris/translate.c index 12b96eb68f..38a999e6f1 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "crisv32-decode.h" #include "exec/helper-gen.h" @@ -50,7 +51,11 @@ #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) #define BUG_ON(x) ({if (x) BUG();}) -#define DISAS_SWI 5 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_SWI DISAS_TARGET_3 /* Used by the decoder. */ #define EXTRACT_FIELD(src, start, end) \ diff --git a/target/i386/translate.c b/target/i386/translate.c index 26e8002433..a0d8788c57 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -31,8 +32,6 @@ #include "trace-tcg.h" #include "exec/log.h" -#define DISAS_TOO_MANY 5 - #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target/lm32/translate.c b/target/lm32/translate.c index f68f372f15..65bc9c0bf6 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translator.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" @@ -47,6 +48,11 @@ #define MEM_INDEX 0 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index be24355080..d738f32f9c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,6 +25,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -173,7 +174,11 @@ static void do_writebacks(DisasContext *s) } } -#define DISAS_JUMP_NEXT 4 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_JUMP_NEXT DISAS_TARGET_3 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 83e2ef4960..067b0878d6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" +#include "exec/translator.h" #include "trace-tcg.h" #include "exec/log.h" @@ -46,6 +47,11 @@ #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv env_debug; static TCGv_env cpu_env; static TCGv cpu_R[32]; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8b97d6585f..6b0961837d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" + +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ #define INSTRUCTION_FLG(func, flags) { (func), (flags) } #define INSTRUCTION(func) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a01413113b..112db1ad0f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -37,6 +38,11 @@ #define LOG_DIS(str, ...) \ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + typedef struct DisasContext { TranslationBlock *tb; target_ulong pc; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4b0db7b7bd..909b12818d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -77,7 +77,8 @@ typedef struct { } u; } DisasCompare; -#define DISAS_EXCP 4 +/* is_jmp field values */ +#define DISAS_EXCP DISAS_TARGET_0 #ifdef DEBUG_INLINE_BRANCHES static uint64_t inline_branch_hit[CC_OP_MAX]; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 8f30cff932..6c094d59d7 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -16,6 +16,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -45,9 +46,13 @@ typedef struct DisasContext { #define IS_USER(s) 1 #endif +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ -#define DISAS_SYSCALL 5 +#define DISAS_SYSCALL DISAS_TARGET_3 static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f3f0ff589c..d7bf07e8e6 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -38,6 +38,7 @@ #include "sysemu/sysemu.h" #include "exec/cpu_ldst.h" #include "exec/semihost.h" +#include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -46,6 +47,9 @@ #include "exec/log.h" +/* is_jmp field values */ +#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */ + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; From patchwork Wed Sep 6 16:05:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111813 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1126847qge; Wed, 6 Sep 2017 09:14:57 -0700 (PDT) X-Received: by 10.237.34.145 with SMTP id p17mr4477356qtc.61.1504714497691; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:45 -0700 Message-Id: <20170906160612.22769-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PULL 05/32] target/arm: Delay check for magic kernel page X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson There's nothing magic about the exception that we generate in order to execute the magic kernel page. We can and should allow gdb to set a breakpoint at this location. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 0c39c2b996..746193eebc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11968,17 +11968,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) 0); num_insns++; -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp = DISAS_NORETURN; - break; - } -#endif - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { @@ -12010,6 +11999,17 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_start(); } +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->is_jmp = DISAS_NORETURN; + break; + } +#endif + if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either From patchwork Wed Sep 6 16:05:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111805 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1118623qge; Wed, 6 Sep 2017 09:09:41 -0700 (PDT) X-Received: by 10.55.201.155 with SMTP id m27mr4351513qkl.57.1504714180976; Wed, 06 Sep 2017 09:09:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714180; cv=none; d=google.com; s=arc-20160816; b=tAihiV6Cddjh9b8hALzmEzYfySXXwCG0BKqtY9bDL0GDo+XP0M6i8nYn2LtW250v4D cUYFNCP35248+IjmTF/A4HtkbGOjpvAV02Cb5G44Zv5cHtEZP+x86/Ns4ljjy1mJXrPO 6yCo+W8VZYYS5nFlcHQqR9h8T+2Ohtaw+fRxGUGrS5NBBRD3lDQ4GtHPpU5XlAA5i9WG jEfZYop1gtMUUts2nFy3QOqecnBP12uhUpNz2NE7OoPe0zA3HmIaaGgzZUTjD30qQzPg bzBaRe1wnJ0q9xN9g80d/ClvkPjWwYkPvu7Zr15yt84jss/8UU8XuoneYIkDOh7WToKv ld3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=R62/TouQaAsAwTFblPipbaD9zB1SKMXzhPWYt2bTtDQ=; b=XdptQEB6jWUXAJbWSgc32VU47guaJ3LtOQa/eo87EBjTjLMX/TqUa5n+8Ge/VwvnSH 3HeCQFzaoYoLK0FEN5zMsWW9KwA4Jo1xfo9YkON7fVKqI6YO82MUmxYZ00kvGi/v0Gu9 D4nxA7F2dG0xV91MOOvPPFwkq36AKJLuii7ex60Tf1K6AoCnd17S23DZUi6ZArUhGEgS pRwy6yLzyXURvvTPxc+o5xfT0rmje2f6GPpb7r28D37bfChLCUKNJN9kBM/1zx27RDwR yD74MfD5wX1ZFEl+DNDARnwV5rtZQByjM1uOHi6su8dTS/aUcTgRwX2HwOKqxOOyVEGs WctA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aabH3fkf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:46 -0700 Message-Id: <20170906160612.22769-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PULL 06/32] tcg: Add generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002073981.22386.9870422422367410100.stgit@frigg.lan> [rth: Moved max_insns adjustment from tb_start to init_disas_context. Removed pc_next return from translate_insn. Removed tcg_check_temp_count from generic loop. Moved gen_io_end to exactly match gen_io_start. Use qemu_log instead of error_report for temporary leaks. Moved TB size/icount assignments before disas_log.] Signed-off-by: Richard Henderson --- include/exec/translator.h | 104 ++++++++++++++++++++++++++++++++++ accel/tcg/translator.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++ accel/tcg/Makefile.objs | 1 + 3 files changed, 243 insertions(+) create mode 100644 accel/tcg/translator.c -- 2.13.5 diff --git a/include/exec/translator.h b/include/exec/translator.h index b51b8f8a4e..e2dc2a04ae 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -10,6 +10,19 @@ #ifndef EXEC__TRANSLATOR_H #define EXEC__TRANSLATOR_H +/* + * Include this header from a target-specific file, and add a + * + * DisasContextBase base; + * + * member in your target-specific DisasContext. + */ + + +#include "exec/exec-all.h" +#include "tcg/tcg.h" + + /** * DisasJumpType: * @DISAS_NEXT: Next instruction in program order. @@ -37,4 +50,95 @@ typedef enum DisasJumpType { DISAS_TARGET_11, } DisasJumpType; +/** + * DisasContextBase: + * @tb: Translation block for this disassembly. + * @pc_first: Address of first guest instruction in this TB. + * @pc_next: Address of next guest instruction in this TB (current during + * disassembly). + * @is_jmp: What instruction to disassemble next. + * @num_insns: Number of translated instructions (including current). + * @singlestep_enabled: "Hardware" single stepping enabled. + * + * Architecture-agnostic disassembly context. + */ +typedef struct DisasContextBase { + TranslationBlock *tb; + target_ulong pc_first; + target_ulong pc_next; + DisasJumpType is_jmp; + unsigned int num_insns; + bool singlestep_enabled; +} DisasContextBase; + +/** + * TranslatorOps: + * @init_disas_context: + * Initialize the target-specific portions of DisasContext struct. + * The generic DisasContextBase has already been initialized. + * Return max_insns, modified as necessary by db->tb->flags. + * + * @tb_start: + * Emit any code required before the start of the main loop, + * after the generic gen_tb_start(). + * + * @insn_start: + * Emit the tcg_gen_insn_start opcode. + * + * @breakpoint_check: + * When called, the breakpoint has already been checked to match the PC, + * but the target may decide the breakpoint missed the address + * (e.g., due to conditions encoded in their flags). Return true to + * indicate that the breakpoint did hit, in which case no more breakpoints + * are checked. If the breakpoint did hit, emit any code required to + * signal the exception, and set db->is_jmp as necessary to terminate + * the main loop. + * + * @translate_insn: + * Disassemble one instruction and set db->pc_next for the start + * of the following instruction. Set db->is_jmp as necessary to + * terminate the main loop. + * + * @tb_stop: + * Emit any opcodes required to exit the TB, based on db->is_jmp. + * + * @disas_log: + * Print instruction disassembly to log. + */ +typedef struct TranslatorOps { + int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, + int max_insns); + void (*tb_start)(DisasContextBase *db, CPUState *cpu); + void (*insn_start)(DisasContextBase *db, CPUState *cpu); + bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, + const CPUBreakpoint *bp); + void (*translate_insn)(DisasContextBase *db, CPUState *cpu); + void (*tb_stop)(DisasContextBase *db, CPUState *cpu); + void (*disas_log)(const DisasContextBase *db, CPUState *cpu); +} TranslatorOps; + +/** + * translator_loop: + * @ops: Target-specific operations. + * @db: Disassembly context. + * @cpu: Target vCPU. + * @tb: Translation block. + * + * Generic translator loop. + * + * Translation will stop in the following cases (in order): + * - When is_jmp set by #TranslatorOps::breakpoint_check. + * - set to DISAS_TOO_MANY exits after translating one more insn + * - set to any other value than DISAS_NEXT exits immediately. + * - When is_jmp set by #TranslatorOps::translate_insn. + * - set to any value other than DISAS_NEXT exits immediately. + * - When the TCG operation buffer is full. + * - When single-stepping is enabled (system-wide or on the current vCPU). + * - When too many instructions have been translated. + */ +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb); + +void translator_loop_temp_check(DisasContextBase *db); + #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c new file mode 100644 index 0000000000..afa3af478a --- /dev/null +++ b/accel/tcg/translator.c @@ -0,0 +1,138 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Lluís Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "exec/log.h" +#include "exec/translator.h" + +/* Pairs with tcg_clear_temp_count. + To be called by #TranslatorOps.{translate_insn,tb_stop} if + (1) the target is sufficiently clean to support reporting, + (2) as and when all temporaries are known to be consumed. + For most targets, (2) is at the end of translate_insn. */ +void translator_loop_temp_check(DisasContextBase *db) +{ + if (tcg_check_temp_count()) { + qemu_log("warning: TCG temporary leaks before " + TARGET_FMT_lx "\n", db->pc_next); + } +} + +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb) +{ + int max_insns; + + /* Initialize DisasContext */ + db->tb = tb; + db->pc_first = tb->pc; + db->pc_next = db->pc_first; + db->is_jmp = DISAS_NEXT; + db->num_insns = 0; + db->singlestep_enabled = cpu->singlestep_enabled; + + /* Instruction counting */ + max_insns = db->tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + if (db->singlestep_enabled || singlestep) { + max_insns = 1; + } + + max_insns = ops->init_disas_context(db, cpu, max_insns); + tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ + + /* Reset the temp count so that we can identify leaks */ + tcg_clear_temp_count(); + + /* Start translating. */ + gen_tb_start(db->tb); + ops->tb_start(db, cpu); + tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ + + while (true) { + db->num_insns++; + ops->insn_start(db, cpu); + tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ + + /* Pass breakpoint hits to target for further processing */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc == db->pc_next) { + if (ops->breakpoint_check(db, cpu, bp)) { + break; + } + } + } + /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate + that only one more instruction is to be executed. Otherwise + it should use DISAS_NORETURN when generating an exception, + but may use a DISAS_TARGET_* value for Something Else. */ + if (db->is_jmp > DISAS_TOO_MANY) { + break; + } + } + + /* Disassemble one instruction. The translate_insn hook should + update db->pc_next and db->is_jmp to indicate what should be + done next -- either exiting this loop or locate the start of + the next instruction. */ + if (db->num_insns == max_insns && (db->tb->cflags & CF_LAST_IO)) { + /* Accept I/O on the last instruction. */ + gen_io_start(); + ops->translate_insn(db, cpu); + gen_io_end(); + } else { + ops->translate_insn(db, cpu); + } + + /* Stop translation if translate_insn so indicated. */ + if (db->is_jmp != DISAS_NEXT) { + break; + } + + /* Stop translation if the output buffer is full, + or we have executed all of the allowed instructions. */ + if (tcg_op_buf_full() || db->num_insns >= max_insns) { + db->is_jmp = DISAS_TOO_MANY; + break; + } + } + + /* Emit code to exit the TB, as indicated by db->is_jmp. */ + ops->tb_stop(db, cpu); + gen_tb_end(db->tb, db->num_insns); + + /* The disas_log hook may use these values rather than recompute. */ + db->tb->size = db->pc_next - db->pc_first; + db->tb->icount = db->num_insns; + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) + && qemu_log_in_addr_range(db->pc_first)) { + qemu_log_lock(); + qemu_log("----------------\n"); + ops->disas_log(db, cpu); + qemu_log("\n"); + qemu_log_unlock(); + } +#endif +} diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index 70cd474c01..22642e6f75 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) += tcg-all.o obj-$(CONFIG_SOFTMMU) += cputlb.o obj-y += cpu-exec.o cpu-exec-common.o translate-all.o +obj-y += translator.o From patchwork Wed Sep 6 16:05:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111814 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1127365qge; Wed, 6 Sep 2017 09:15:15 -0700 (PDT) X-Received: by 10.55.122.7 with SMTP id v7mr3945924qkc.86.1504714515521; Wed, 06 Sep 2017 09:15:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714515; cv=none; d=google.com; s=arc-20160816; b=C4Ip2pkm5y7aYY9mPL2aOWIZ1ChqcCYInMqXeUtkr9mIFCgD6eH1nN169X1zQniu8N 976mvz66RPXJmqhkCdIpS9u5cL9OXXDypm8YsT2HyzCNLE+oyKjOqaQEVvmqvXlmuDUS +VW31cwjaE3slJnqoJxFr3a/woO3BaUBBWfK5sIfWPiHAFB3bLRKE2mo9SwChHbkcpIh IW5tSNXZNgnRBAksm6g4yjbyufl+gZhTFj8Gu6FHHJT6buKIWvckB27JB2eqTm6OaJ5U hEWrflqa0xOuJlJdk96D6EnGUcVRMK1LF43J/XHDY+aq5K6fvgXh3Q+6GznCJVgqtXF4 8S9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=cXA05z5fG9qfN0kUotbukGjmdFLQPzYcmOBDIAbbPvM=; b=sP1dc8ZWiC6jYnsjP8SXH9BxYJdGXhv0xk5BQbYFVfF4jFtBFffuuXWr0LlJlUFtyq M0Xnn1z16TqBA4xe7ljMkJLEBsYUSpHw2mQ/u7HZpSfyacrP05p8U2YczgVYI5/UIRAW CPL+g+ZJriO8nS9lEbcZdLwiJ4R+vWiWiCDESwIzIycI3NX6GYUZy2//Qy2aWeX+lRpV 1OzQg8D5TOOaTHtopt9zWiOS7mM2dqwFiy44tdF6RYzae6x/XSeeys/rTWO0LaXmtG9l LVzmvyRkRI8Y5rjEhfkMFDsHdi2mPXqjnmPtuHBPPCZi37+A86PVZ1M9NVwtarykLqBH j+Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D5kqiBHk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:47 -0700 Message-Id: <20170906160612.22769-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 07/32] target/i386: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002098212.22386.17313318023406046314.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 140 ++++++++++++++++++++++++------------------------ 1 file changed, 69 insertions(+), 71 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index a0d8788c57..3a3d91c4d7 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -95,6 +95,8 @@ static int x86_64_hregs; #endif typedef struct DisasContext { + DisasContextBase base; + /* current insn context */ int override; /* -1 if no override */ int prefix; @@ -102,8 +104,6 @@ typedef struct DisasContext { TCGMemOp dflag; target_ulong pc_start; target_ulong pc; /* pc = eip + cs_base */ - int is_jmp; /* 1 = means jump (stop translation), 2 means CPU - static state change (stop translation) */ /* current block context */ target_ulong cs_base; /* base of CS segment */ int pe; /* protected mode */ @@ -124,12 +124,10 @@ typedef struct DisasContext { int cpl; int iopl; int tf; /* TF cpu flag */ - int singlestep_enabled; /* "hardware" single step enabled */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint64_t flags; /* all execution flags */ - struct TranslationBlock *tb; int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; @@ -1119,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot) static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1134,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1154,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -2137,7 +2135,7 @@ static inline int insn_const_size(TCGMemOp ot) static inline bool use_goto_tb(DisasContext *s, target_ulong pc) { #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) || + return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) || (pc & TARGET_PAGE_MASK) == (s->pc_start & TARGET_PAGE_MASK); #else return true; @@ -2152,8 +2150,8 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); - s->is_jmp = DISAS_NORETURN; + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); + s->base.is_jmp = DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2244,12 +2242,12 @@ static void gen_movl_seg_T0(DisasContext *s, int seg_reg) stop as a special handling must be done to disable hardware interrupts for the next instruction */ if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) { - s->is_jmp = DISAS_TOO_MANY; + s->base.is_jmp = DISAS_TOO_MANY; } } else { gen_op_movl_seg_T0_vm(seg_reg); if (seg_reg == R_SS) { - s->is_jmp = DISAS_TOO_MANY; + s->base.is_jmp = DISAS_TOO_MANY; } } } @@ -2422,7 +2420,7 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } /* Generate #UD for the current instruction. The assumption here is that @@ -2460,7 +2458,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2468,7 +2466,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2524,10 +2522,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); } - if (s->tb->flags & HF_RF_MASK) { + if (s->base.tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } - if (s->singlestep_enabled) { + if (s->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -2543,7 +2541,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static inline void @@ -4417,7 +4415,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } } -/* convert one instruction. s->is_jmp is set if the translation must +/* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, target_ulong pc_start) @@ -5377,7 +5375,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg == R_SS) { s->tf = 0; @@ -5392,7 +5390,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -5443,7 +5441,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg == R_SS) { s->tf = 0; @@ -5652,7 +5650,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(ot, reg, cpu_T1); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6308,7 +6306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6323,7 +6321,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6339,14 +6337,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6360,14 +6358,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6378,14 +6376,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6398,14 +6396,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6944,7 +6942,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7113,11 +7111,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7189,7 +7187,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } break; case 0x100: @@ -7372,7 +7370,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; break; case 0xd9: /* VMMCALL */ @@ -7572,11 +7570,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7941,24 +7939,24 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg)); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8384,15 +8382,13 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { CPUX86State *env = cs->env_ptr; DisasContext dc1, *dc = &dc1; - target_ulong pc_ptr; uint32_t flags; - target_ulong pc_start; target_ulong cs_base; int num_insns; int max_insns; /* generate intermediate code */ - pc_start = tb->pc; + dc->base.pc_first = tb->pc; cs_base = tb->cs_base; flags = tb->flags; @@ -8405,11 +8401,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->base.singlestep_enabled = cs->singlestep_enabled; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->cs_base = cs_base; - dc->tb = tb; + dc->base.tb = tb; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8459,8 +8455,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_ptr1 = tcg_temp_new_ptr(); cpu_cc_srcT = tcg_temp_local_new(); - dc->is_jmp = DISAS_NEXT; - pc_ptr = pc_start; + dc->base.is_jmp = DISAS_NEXT; + dc->base.pc_next = dc->base.pc_first; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { @@ -8472,37 +8468,38 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(pc_ptr, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); num_insns++; /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { - gen_debug(dc, pc_ptr - dc->cs_base); + gen_debug(dc, dc->base.pc_next - dc->cs_base); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - pc_ptr += 1; + dc->base.pc_next += 1; goto done_generating; } if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } - pc_ptr = disas_insn(env, dc, pc_ptr); + dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next); /* stop translation if indicated */ - if (dc->is_jmp) + if (dc->base.is_jmp) { break; + } /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a change to be happen */ - if (dc->tf || dc->singlestep_enabled || + if (dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8513,23 +8510,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) because an exception hasn't stopped this code. */ if ((tb->cflags & CF_USE_ICOUNT) - && ((pc_ptr & TARGET_PAGE_MASK) - != ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) - || (pc_ptr & ~TARGET_PAGE_MASK) == 0)) { - gen_jmp_im(pc_ptr - dc->cs_base); + && ((dc->base.pc_next & TARGET_PAGE_MASK) + != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) || + (dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) || num_insns >= max_insns) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } if (singlestep) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8541,24 +8538,25 @@ done_generating: #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); #ifdef TARGET_X86_64 if (dc->code64) disas_flags = 2; else #endif disas_flags = !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->base.pc_first, + disas_flags); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size = pc_ptr - pc_start; + tb->size = dc->base.pc_next - dc->base.pc_first; tb->icount = num_insns; } From patchwork Wed Sep 6 16:05:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111809 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1121317qge; Wed, 6 Sep 2017 09:11:22 -0700 (PDT) X-Received: by 10.55.25.150 with SMTP id 22mr4345154qkz.91.1504714282187; Wed, 06 Sep 2017 09:11:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714282; cv=none; d=google.com; s=arc-20160816; b=rm8CApp1AVaYkaCYR7I5if1BJOOzHwTygWioWwgMBIzRBQj5kHlDvHwThYXlLj90sN Nf8nwlbI3pmoq+iKAwN30w35mwvoCzO0PNdhe0K2MNOvCKSuZDjFBeDwLCnCroT/YeQ4 Ujwam+9HvsIGlFgrJfGXF0bW4v6WwSueCBxRj2QO5GYi0Hb6ZzVpokBtJGJm6t4EtqVD 71p2C9nfVGPeUvagscxIdMa2Pj6wr+39ypk0JoEs2p/sNnTgtTxzCYo86rdK8HwlCKVX qRcVRW6c5zBCUVzm8FNe+tPFp6srq6V2gST7Z7R/Ei3syYDYS1lB9aVNoXfPa/MpFoC/ Mz9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0yLW7ctcPD/DWG7PrJMW3lLrukj18jAqXKN1J9zeHP8=; b=DFwhR0HeyGYvOuWAd96hmLod0VAxbWquzRfTRCw5Q3l6w2gYobJv3rCvAvx8Eq5lOH l+xQ+E/3lvXZSXqbzihEeGH+9Qgo6S3davEjCJt4HldAYAGgbeE4W7NGEnuIdVLXkkwZ P7z0PZZXSuTit6EeghMsgk1I8KMDqcD+nP4ix9U9e1sBf1d590pKHS+NSPT84NPF+Hsf 6vefqTr+F9V7UYgD1h4JOT3ji6upZpL2RZec4IKL2HBedVskaoCaOjHV7xrzLBZWemGg +bDePl2O/mQ6Bt8uQcfSMfVjm0lUzx7J4IWu4T4KVz1CxOZrFItjlpcE3EMKbdH4e1x9 lIug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=j6epNIpB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:48 -0700 Message-Id: <20170906160612.22769-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PULL 08/32] target/i386: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Signed-off-by: Lluís Vilanova Message-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index 3a3d91c4d7..4281e9bc56 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8377,20 +8377,13 @@ void tcg_x86_init(void) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu, + int max_insns) { - CPUX86State *env = cs->env_ptr; - DisasContext dc1, *dc = &dc1; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.pc_first = tb->pc; - cs_base = tb->cs_base; - flags = tb->flags; + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUX86State *env = cpu->env_ptr; + uint32_t flags = dc->base.tb->flags; + target_ulong cs_base = dc->base.tb->cs_base; dc->pe = (flags >> HF_PE_SHIFT) & 1; dc->code32 = (flags >> HF_CS32_SHIFT) & 1; @@ -8401,11 +8394,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; - dc->base.singlestep_enabled = cs->singlestep_enabled; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->cs_base = cs_base; - dc->base.tb = tb; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8423,7 +8414,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags = flags; - dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8435,7 +8426,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) record/replay modes and there will always be an additional step for ecx=0 when icount is enabled. */ - dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt = !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8455,9 +8446,24 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_ptr1 = tcg_temp_new_ptr(); cpu_cc_srcT = tcg_temp_local_new(); + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUX86State *env = cs->env_ptr; + DisasContext dc1, *dc = &dc1; + int num_insns; + int max_insns; + + /* generate intermediate code */ + dc->base.singlestep_enabled = cs->singlestep_enabled; + dc->base.tb = tb; dc->base.is_jmp = DISAS_NEXT; + dc->base.pc_first = tb->pc; dc->base.pc_next = dc->base.pc_first; - num_insns = 0; + max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -8465,7 +8471,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns = TCG_MAX_INSNS; } + max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns); + num_insns = 0; gen_tb_start(tb); for(;;) { tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); @@ -8498,7 +8506,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; From patchwork Wed Sep 6 16:05:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111817 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1129363qge; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:49 -0700 Message-Id: <20170906160612.22769-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PULL 09/32] target/i386: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002146647.22386.13380064201042141261.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index 4281e9bc56..b7e5854513 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8449,6 +8449,13 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu, return max_insns; } +static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8476,7 +8483,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) num_insns = 0; gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + i386_tr_insn_start(&dc->base, cs); num_insns++; /* If RF is set, suppress an internally generated breakpoint. */ From patchwork Wed Sep 6 16:05:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111811 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1123240qge; Wed, 6 Sep 2017 09:12:40 -0700 (PDT) X-Received: by 10.55.144.196 with SMTP id s187mr4361288qkd.13.1504714360298; Wed, 06 Sep 2017 09:12:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714360; cv=none; d=google.com; s=arc-20160816; b=Df8P+bKZWxJ4hrnp0xwMltQaPcy4+iEohK8Qlvk21jNQEqKqNCiRlWvEdlck1WAJcL AKOxqejMUQGoibHATAYRz85O2QpP+69qcTnwd2K8CcbzEsv0CA5DiNIxN3a1s2XBtfPM w+RjyuXlzXPunL8zDeCCS5KzF8yYpWd3CCmJO6kUyLfZvoK/RuhaBPt40s9BdthNzs+Y qaD4nNtfU8tQ+Z8ZiRoVVkG55CDeb3mJ98MOZyyGUPDiWmXVqPQgiOmadl5DTEnosrD8 mz+x/OHUtIrBqrA6biGw+tYWuLqp4V8x3Wv3eIb9RMwmotxMSTmN5f4RXDKgs5OQorAT 22WQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=JBnESfPgluCNjUoEQc0wVDgPrUzhAwV+Ja6vru/3p1M=; b=so4iYUJM9t570sCNsSZTiKZ3YcRYI/45HhJ2zRMjXjFoQLrg4fY6y1mQTIINZBKYH9 3i9TUO35fEDQ/roIY+jKiv5sVdJNCuvclPmAAQL0vylHJ4/3GtGJmeQL5s6m24gn12gf 8DPQggIBCthFi5e8OKIhmW1cpFNwGslljuWII/pHqb0Edyz9BMAlhxEuJxOgFWJZiIeG wFT/FLTvjQbARdSptDf3tJomW+/Of/2Wg+SPmeoDawCDLH81jAN4U2n82xwG8fkHUv6e 3RjOLKTIEAXXyzXId3UHkcflDLWN53yo8i7xjD2wBa+q6ZhLQFicHmimOwt2r3L+h8jD p/Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kicp4aic; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:50 -0700 Message-Id: <20170906160612.22769-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL 10/32] target/i386: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 12 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index b7e5854513..4d4083fe30 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8456,6 +8456,26 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp = DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next += 1; + return true; + } else { + return false; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8486,18 +8506,21 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) i386_tr_insn_start(&dc->base, cs); num_insns++; - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next += 1; - goto done_generating; + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc == dc->base.pc_next) { + if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + + if (dc->base.is_jmp == DISAS_NORETURN) { + break; + } } + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -8548,7 +8571,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); -done_generating: gen_tb_end(tb, num_insns); #ifdef DEBUG_DISAS From patchwork Wed Sep 6 16:05:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111812 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1125216qge; Wed, 6 Sep 2017 09:13:58 -0700 (PDT) X-Received: by 10.55.148.3 with SMTP id w3mr4437287qkd.26.1504714438835; Wed, 06 Sep 2017 09:13:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714438; cv=none; d=google.com; s=arc-20160816; b=eo+OOW0oZYhhieH8Y2ypnjwSM/iinjVmTxfDKDl4S0kgWNFCl4SHEZwqN1vlCCeQ66 bDNHLy0aEpL+VbxH/7EPi5EbgFYJ4g+WFdO/ygGoFOAgayTjkAAr+ysS2jP82uzEnLCS 8pD9kcqQ9ZGPk3NIu5/w5nCdYhCFHvkCmhNIVywDbrr1jhRDzk/0BiIDdSYU7vEPlqQv KJWHlsENXKAfymqqOBpu1ArzhnL4jRysow7Ib1SbDfcCFHxfo5fZi/wAt2z4UXqMMsJB 2mfPQbhgJ8ODqHv0krZrInkVexV6QF00oDSGVVptx6/m235xdmz0kZ7hJji9oX7rV9Z9 qGsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=WCabe7Hfc5O/Az0W5815T3bKK8UwqfKSOQYFvQwn+WM=; b=xHX4ZJmiWLTyGIlic2+3Uz72L4s54bUI7UWYznTo+2PrpuYc6r4eZcaH63jih+LQ+V xyUfmjYMR4L9tpn/z1D+SvcyPfmwwr99NKdJtG7ewQ8d+mPYfupeLrAXiRc0X1IdQqu+ dRr3BcCzbhXa85jNvi3CeLjpRseij7hZTfx1ZbUyeOM4TcEuVsEpcF/aFk3361iz3VQi XPOhdfOY3xYaaCG38srW+toqRowm4seA79D3J6QbAXJPHmaR5BBxGVCfCJNHlGb9ZUNx HAQFMP3BaN8BiFRvMR7jU0uclzOuqJqpUImPe+3B//0nWSpiEhyftsGbeF02G9OpTjCz gY0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jenYaFh2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:51 -0700 Message-Id: <20170906160612.22769-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PULL 11/32] target/i386: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 66 +++++++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 24 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index 4d4083fe30..0f38896f17 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4417,15 +4417,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { + CPUX86State *env = cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; prefixes = 0; @@ -8476,10 +8477,46 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, } } +static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_next = disas_insn(dc, cpu); + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + chance to happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; + } + + dc->base.pc_next = pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUX86State *env = cs->env_ptr; DisasContext dc1, *dc = &dc1; int num_insns; int max_insns; @@ -8525,39 +8562,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_start(); } - dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next); + i386_tr_translate_insn(&dc->base, cs); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) || num_insns >= max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); From patchwork Wed Sep 6 16:05:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111810 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1122709qge; Wed, 6 Sep 2017 09:12:19 -0700 (PDT) X-Received: by 10.55.159.81 with SMTP id i78mr4344831qke.81.1504714339017; Wed, 06 Sep 2017 09:12:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714339; cv=none; d=google.com; s=arc-20160816; b=odrm6iatzLg6QITCfXII0NFNVsw9MOyyhWxtmcEPLLbfpuM9Q6ACEFhyZF783LLuGI 3N8YbiFc4nVbdhr4J8dpp6eo1riuvujNmJdHManHKBqRdE2VSvIweeIc8NGE3AanHabB yGzOqgjyK4aqTdfWJ2kxzMI6u9Wg8bIjjiuwudIh1vKrvkXW3T3TMY690em4WaWxpfui hl5V1yB4TOpZGJDkThP92AIeSNqoZMAGabUYh3cyNdNx0IBYh1vxWpz7rnq1CUth3ZKo nZmkjBB1LWqPNdNzSY1qYKgaPRlnil61Fu8bcL1j/iWXiTELzrwqUPDT/mkHChHVQ8V6 jDJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/hs5DJ5ZOYzeGcPj2CaJWFBYCthdShVyhxl4UMKX3/s=; b=g1XVgnievyFxThs/Mu+T+Wn9S0j9SWxYYMM9Gu515o40r9C2tyiLqpnaHdr/rCy20E U2nbSH1vgTh0a+n036tzrmkL+mHQ4yopNLCpbQuLTASkUGutZx8fQrNf2we6gGJr3i4P CJK2BJ4pmTOLCRIBBY6+F6lZLf4LV9XicTkdCrl1dG7bdvCYG/EW/UQjmmDMngMPZGmm a5Rmmh3pH5zJVJYDIvMZ4lbPffqJB3e7iHXdDh1aIKq3Gr4VUVAwNLB9FczCt/6rO4Vu Qrflb5dqJXSbJ3NDVu/O4RkgN4lbfWYeW1QUSvyCsVZVUYQNSFiFjdnZBhMJCY/3H/2g 8Wfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VTv20rXA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:52 -0700 Message-Id: <20170906160612.22769-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PULL 12/32] target/i386: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002219289.22386.17959138704858928730.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index 0f38896f17..9872f84a03 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8488,8 +8488,6 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a chance to happen */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp = DISAS_TOO_MANY; } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) && ((dc->base.pc_next & TARGET_PAGE_MASK) @@ -8502,18 +8500,24 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp = DISAS_TOO_MANY; } else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) { - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp = DISAS_TOO_MANY; } dc->base.pc_next = pc_next; } +static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (dc->base.is_jmp == DISAS_TOO_MANY) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); + gen_eob(dc); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8570,23 +8574,21 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) /* if single step mode, we generate only one instruction and generate an exception */ if (dc->base.singlestep_enabled) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || num_insns >= max_insns) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; break; } if (singlestep) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; break; } } + i386_tr_tb_stop(&dc->base, cs); if (tb->cflags & CF_LAST_IO) gen_io_end(); gen_tb_end(tb, num_insns); From patchwork Wed Sep 6 16:05:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111822 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1135319qge; Wed, 6 Sep 2017 09:20:31 -0700 (PDT) X-Received: by 10.200.42.98 with SMTP id l31mr4724687qtl.80.1504714831188; Wed, 06 Sep 2017 09:20:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714831; cv=none; d=google.com; s=arc-20160816; b=cG5YkzlfWM+3isXS2tn5jpk3vRgmJ38qm6W4EJQUPJ6KRrA8tuf3q+d2eofEsCvL5u 68FODdrXJx6J6HKBIC7etwLP+bdo2zILKU3mnR13v3NilirUbxOM/8AuWfQZ0BHbu7wK xAqAyG3Y2reboEMB8THn6TpuxDH5jNVCw8taQ/aaCMk4OVviDLLS3bBNZ72Q7D5lKYWC DsRgevxKUwg88pNezD2ngyxuE2w8HtXfAhGu4BCgra3OjTfH7t5i+ZvCxmOXR4slIoCY CVyI2wc3EcXKSsK4jPkoYrN0CRjSlR5k7QoM5bbYa6dL1KLUjtOALSWz1HQkuFwJ4UR9 xNuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eB0FH3t+OZuRMiq5J2cNC7DQkRCrEPN4sXzCTB1u54o=; b=B2u+yZcdtdbq1LsE4H3DF11q18M5wBAjvM1RDEOzQjIEdt3x9nzmTVdMbmdcsQ1ixn qlftHI1yO3jVsKbFh//uOq46SrFIAJ6WaBzY7TxvqVhWwPiwq1Ir8PUBF8nehEfFtf61 eSR46GEFwJ+sg9AXapA3kHgtUJdun1olOIuAAa6v91vDkDxI1TH/uCWQDgRPA9aMIxNh x4iLCBOTm2AZEGjFgCXTLjWADAfvg+qk8P4D+Tk1jkCYEBvo5FtIYEUI17oYeWFHKPVo dLFRPDOJMP9fUwjt6B1UquGsKuarE7VIYk+TxS2eZp4wblTrzDsBWU+ZFKdFwZbeEqki o/kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P+VhubcS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:53 -0700 Message-Id: <20170906160612.22769-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 13/32] target/i386: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002243497.22386.8888053391875656102.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index 9872f84a03..ad4b2735f4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8518,6 +8518,21 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) } } +static void i386_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + int disas_flags = !dc->code32; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); +#ifdef TARGET_X86_64 + if (dc->code64) { + disas_flags = 2; + } +#endif + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8593,28 +8608,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_end(); gen_tb_end(tb, num_insns); + tb->size = dc->base.pc_next - dc->base.pc_first; + tb->icount = num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { - int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -#ifdef TARGET_X86_64 - if (dc->code64) - disas_flags = 2; - else -#endif - disas_flags = !dc->code32; - log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->base.pc_first, - disas_flags); + i386_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - - tb->size = dc->base.pc_next - dc->base.pc_first; - tb->icount = num_insns; } void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, From patchwork Wed Sep 6 16:05:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111818 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1131093qge; Wed, 6 Sep 2017 09:17:40 -0700 (PDT) X-Received: by 10.200.3.195 with SMTP id z3mr4605115qtg.259.1504714660799; Wed, 06 Sep 2017 09:17:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714660; cv=none; d=google.com; s=arc-20160816; b=qJk2KtJkS3sFQ3P1ERGupXs4/f73j70PF5I4yfP996aUUDWnYl8IVPJ+ISeS5oEeut dgxISUpNWiF+Weqp1F5rQKR6V8pJHMnF6L8HasyDBVNbNBGXZuFoCrdXBJqeeUcxHp+8 Ed/2xNJr0zLy6pzuMb+d39TJBfcjRHhjz9fbXvj/HrzcHhBKaqoMtjMrb+sJldUNjGoc DRHhb+xwX47guBVdfEtXnjzyv5yZd5bZWANnXvLBZsXD2dN0WxdL3PdWTvKO9WXJWbe6 1PGj41uvWx9BlCOWz4Nmp96QCDcZD4Nh4JUcEwUkmyqYBWZZk306wrp+fxlSJiSXF2jh cCJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4K6BNYHQcpNHFmj0sguQnGWsFAoO7efRcTcbeP5LdLw=; b=gP7eb77tMxoMGgdIny/QpW3p9lsc0WXQx3Npbt1kvMRwj9Zg23r/QqHiV4ykjtOfOm tdHpiBd4OHa9X8s0PtxeovK7I7U/N/WZCqelklAIZRsN9MzsasxqG1puFJ48GLWM2uqF dB47wZWRG44A6tE8LoqkZLuOhuRuo4g5/d+5Gs7aSHX0FHlLj+ygh7/CjFqkT/vnVe3E mTXAVPKm0ZSX1E0q0SUMpd5HEUCOjsBRHrv/Ge5QW/js45SgfSiyez7sV4zRwA8xoBEG Wb8jcAdKQoZuvweSj+L4mjCndjirgRMUj0OHK32Y7bYgU4MHeKT2E+EoywNLgVXeSV+m 0QwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i9pEc6uj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:54 -0700 Message-Id: <20170906160612.22769-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL 14/32] target/i386: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota Message-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 106 +++++++++--------------------------------------- 1 file changed, 19 insertions(+), 87 deletions(-) -- 2.13.5 diff --git a/target/i386/translate.c b/target/i386/translate.c index ad4b2735f4..de0c989763 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8450,6 +8450,10 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu, return max_insns; } +static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -8469,7 +8473,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ + the generic logic setting tb->size later does the right thing. */ dc->base.pc_next += 1; return true; } else { @@ -8533,94 +8537,22 @@ static void i386_tr_disas_log(const DisasContextBase *dcbase, log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags); } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) -{ - DisasContext dc1, *dc = &dc1; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.singlestep_enabled = cs->singlestep_enabled; - dc->base.tb = tb; - dc->base.is_jmp = DISAS_NEXT; - dc->base.pc_first = tb->pc; - dc->base.pc_next = dc->base.pc_first; - - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns); - - num_insns = 0; - gen_tb_start(tb); - for(;;) { - i386_tr_insn_start(&dc->base, cs); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - - if (dc->base.is_jmp == DISAS_NORETURN) { - break; - } - } - - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - i386_tr_translate_insn(&dc->base, cs); - /* stop translation if indicated */ - if (dc->base.is_jmp) { - break; - } - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - dc->base.is_jmp = DISAS_TOO_MANY; - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - num_insns >= max_insns) { - dc->base.is_jmp = DISAS_TOO_MANY; - break; - } - if (singlestep) { - dc->base.is_jmp = DISAS_TOO_MANY; - break; - } - } - i386_tr_tb_stop(&dc->base, cs); - if (tb->cflags & CF_LAST_IO) - gen_io_end(); - gen_tb_end(tb, num_insns); +static const TranslatorOps i386_tr_ops = { + .init_disas_context = i386_tr_init_disas_context, + .tb_start = i386_tr_tb_start, + .insn_start = i386_tr_insn_start, + .breakpoint_check = i386_tr_breakpoint_check, + .translate_insn = i386_tr_translate_insn, + .tb_stop = i386_tr_tb_stop, + .disas_log = i386_tr_disas_log, +}; - tb->size = dc->base.pc_next - dc->base.pc_first; - tb->icount = num_insns; +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - i386_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + translator_loop(&i386_tr_ops, &dc.base, cpu, tb); } void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, From patchwork Wed Sep 6 16:05:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111828 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1143658qge; Wed, 6 Sep 2017 09:26:13 -0700 (PDT) X-Received: by 10.200.50.125 with SMTP id y58mr2436455qta.266.1504715173212; Wed, 06 Sep 2017 09:26:13 -0700 (PDT) ARC-Seal: i=1; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:55 -0700 Message-Id: <20170906160612.22769-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 15/32] target/arm: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002291931.22386.11441154993010495674.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 11 +++-- target/arm/translate-a64.c | 113 ++++++++++++++++++++++--------------------- target/arm/translate.c | 117 ++++++++++++++++++++++----------------------- 3 files changed, 120 insertions(+), 121 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.h b/target/arm/translate.h index 1eb432dc2c..a804ff65ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -6,9 +6,10 @@ /* internal defines */ typedef struct DisasContext { + DisasContextBase base; + target_ulong pc; uint32_t insn; - int is_jmp; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. */ @@ -16,8 +17,6 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; int thumb; int sctlr_b; TCGMemOp be_data; @@ -150,7 +149,8 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, + TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -159,7 +159,8 @@ static inline void a64_translate_init(void) { } -static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb) +static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, + TranslationBlock *tb) { } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 881d3c0cbb..f5c678ef25 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) { + if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags & CF_LAST_IO)) { return false; } #ifndef CONFIG_USER_ONLY /* Only link tbs from inside the same guest page */ - if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { + if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { return false; } #endif @@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) { TranslationBlock *tb; - tb = s->tb; + tb = s->base.tb; if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { gen_step_complete_exception(s); - } else if (s->singlestep_enabled) { + } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } } } @@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t insn, case 0: /* NOP */ return; case 3: /* WFI */ - s->is_jmp = DISAS_WFI; + s->base.is_jmp = DISAS_WFI; return; case 1: /* YIELD */ if (!parallel_cpus) { - s->is_jmp = DISAS_YIELD; + s->base.is_jmp = DISAS_YIELD; } return; case 2: /* WFE */ if (!parallel_cpus) { - s->is_jmp = DISAS_WFE; + s->base.is_jmp = DISAS_WFE; } return; case 4: /* SEV */ @@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, tcg_temp_free_i32(tcg_op); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ gen_a64_set_pc_im(s->pc); - s->is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); + s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); break; } default: @@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, break; } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, } } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } } @@ -1789,7 +1789,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } gen_helper_exception_return(cpu_env); /* Must exit loop to check un-masked IRQs */ - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; return; case 5: /* DRPS */ if (rn != 0x1f) { @@ -1803,7 +1803,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) return; } - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; } /* C3.2 Branches, exception generating and system instructions */ @@ -11200,23 +11200,23 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) { CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); - DisasContext dc1, *dc = &dc1; - target_ulong pc_start; + DisasContext *dc = container_of(dcbase, DisasContext, base); target_ulong next_page_start; - int num_insns; int max_insns; - pc_start = tb->pc; + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; - dc->tb = tb; - - dc->is_jmp = DISAS_NEXT; - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->pc = dc->base.pc_first; dc->condjmp = 0; dc->aarch64 = 1; @@ -11227,17 +11227,17 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 = ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 = ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); + dc->tbi0 = ARM_TBFLAG_TBI0(dc->base.tb->flags); + dc->tbi1 = ARM_TBFLAG_TBI1(dc->base.tb->flags); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = cpu->cp_regs; @@ -11258,16 +11258,15 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); - next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; + next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + max_insns = dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; } @@ -11280,9 +11279,9 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) tcg_clear_temp_count(); do { + dc->base.num_insns++; dc->insn_start_idx = tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, 0, 0); - num_insns++; if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11292,14 +11291,14 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) gen_a64_set_pc_im(dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order + included in [dc->base.tb->pc, dc->base.tb->pc + dc->base.tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting - tb->size below does the right thing. */ + dc->base.tb->size below does the right thing. */ dc->pc += 4; goto done_generating; } @@ -11308,7 +11307,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) } } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -11323,10 +11322,10 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 1); + assert(dc->base.num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; break; } @@ -11342,14 +11341,14 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && !dc->ss_active && dc->pc < next_page_start && - num_insns < max_insns); + dc->base.num_insns < max_insns); - if (tb->cflags & CF_LAST_IO) { + if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); } @@ -11359,7 +11358,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { default: gen_a64_set_pc_im(dc->pc); /* fall through */ @@ -11374,7 +11373,7 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) break; } } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -11414,20 +11413,20 @@ void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) } done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size = dc->pc - pc_start; - tb->icount = num_insns; + dc->base.tb->size = dc->pc - dc->base.pc_first; + dc->base.tb->icount = dc->base.num_insns; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 746193eebc..4db8978a93 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i32 var) * We choose to ignore [1:0] in ARM mode for all architecture versions. */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); tcg_temp_free_i32(var); @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static void gen_singlestep_exception(DisasContext *s) @@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s) * misnamed as it only means "one instruction per TB" and doesn't * affect the code we generate. */ - return s->singlestep_enabled || s->ss_active; + return s->base.singlestep_enabled || s->ss_active; } static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) @@ -930,7 +930,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr) { TCGv_i32 tmp; - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; if (s->thumb != (addr & 1)) { tmp = tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); @@ -943,7 +943,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr) /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { - s->is_jmp = DISAS_JUMP; + s->base.is_jmp = DISAS_JUMP; tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); @@ -957,11 +957,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var) static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { /* Generate the same code here as for a simple bx, but flag via - * s->is_jmp that we need to do the rest of the work later. + * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { - s->is_jmp = DISAS_BX_EXCRET; + s->base.is_jmp = DISAS_BX_EXCRET; } } @@ -1161,7 +1161,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) */ s->svc_imm = imm16; gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_HVC; + s->base.is_jmp = DISAS_HVC; } static inline void gen_smc(DisasContext *s) @@ -1176,7 +1176,7 @@ static inline void gen_smc(DisasContext *s) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_SMC; + s->base.is_jmp = DISAS_SMC; } static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) @@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1193,14 +1193,14 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } static inline void gen_hlt(DisasContext *s, int imm) @@ -4145,7 +4145,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || + return (s->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || ((s->pc - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); #else return true; @@ -4169,12 +4169,12 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); - tcg_gen_exit_tb((uintptr_t)s->tb + n); + tcg_gen_exit_tb((uintptr_t)s->base.tb + n); } else { gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; } static inline void gen_jmp (DisasContext *s, uint32_t dest) @@ -4436,7 +4436,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -4458,7 +4458,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } /* Store value to PC as for an exception return (ie don't @@ -4482,7 +4482,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } /* Generate an old-style exception return. Marks pc as dead. */ @@ -4505,17 +4505,17 @@ static void gen_nop_hint(DisasContext *s, int val) case 1: /* yield */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_YIELD; + s->base.is_jmp = DISAS_YIELD; } break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_WFI; + s->base.is_jmp = DISAS_WFI; break; case 2: /* wfe */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_WFE; + s->base.is_jmp = DISAS_WFE; } break; case 4: /* sev */ @@ -7654,13 +7654,13 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) return 1; } gen_set_pc_im(s, s->pc); - s->is_jmp = DISAS_WFI; + s->base.is_jmp = DISAS_WFI; return 0; default: break; } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } @@ -7751,7 +7751,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); gen_lookup_tb(s); @@ -8065,7 +8065,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -8153,7 +8153,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* setend */ if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } return; } else if ((insn & 0x0fffff00) == 0x057ff000) { @@ -9527,7 +9527,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ - s->is_jmp = DISAS_EXIT; + s->base.is_jmp = DISAS_EXIT; } } break; @@ -9565,7 +9565,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm = extract32(insn, 0, 24); - s->is_jmp = DISAS_SWI; + s->base.is_jmp = DISAS_SWI; break; default: illegal_op: @@ -11657,7 +11657,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) ARCH(6); if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp = DISAS_UPDATE; + s->base.is_jmp = DISAS_UPDATE; } break; case 3: @@ -11751,7 +11751,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm = extract32(insn, 0, 8); - s->is_jmp = DISAS_SWI; + s->base.is_jmp = DISAS_SWI; break; } /* generate a conditional jump to next instruction */ @@ -11830,9 +11830,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); DisasContext dc1, *dc = &dc1; - target_ulong pc_start; target_ulong next_page_start; - int num_insns; int max_insns; bool end_of_page; @@ -11842,17 +11840,18 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/etc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cs, tb); + gen_intermediate_code_a64(&dc->base, cs, tb); return; } - pc_start = tb->pc; + dc->base.tb = tb; + dc->base.pc_first = tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; - dc->tb = tb; - - dc->is_jmp = DISAS_NEXT; - dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->pc = dc->base.pc_first; dc->condjmp = 0; dc->aarch64 = 0; @@ -11909,8 +11908,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_V1 = cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 = tcg_temp_new_i64(); - next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns = 0; + next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -11962,11 +11960,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) store_cpu_field(tmp, condexec_bits); } do { + dc->base.num_insns++; dc->insn_start_idx = tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), 0); - num_insns++; if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11977,7 +11975,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_set_pc_im(dc, dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it's likely not going to be executed */ - dc->is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be @@ -11995,7 +11993,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) } } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -12005,7 +12003,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; break; } #endif @@ -12021,10 +12019,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 1); + assert(dc->base.num_insns == 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - goto done_generating; + dc->base.is_jmp = DISAS_NORETURN; + break; } if (dc->thumb) { @@ -12043,7 +12042,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) disas_arm_insn(dc, insn); } - if (dc->condjmp && !dc->is_jmp) { + if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp = 0; } @@ -12070,11 +12069,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) end_of_page = (dc->pc >= next_page_start) || ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc)); - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !is_singlestepping(dc) && !singlestep && !end_of_page && - num_insns < max_insns); + dc->base.num_insns < max_insns); if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { @@ -12089,7 +12088,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) instruction was a conditional branch or trap, and the PC has already been written. */ gen_set_condexec(dc); - if (dc->is_jmp == DISAS_BX_EXCRET) { + if (dc->base.is_jmp == DISAS_BX_EXCRET) { /* Exception return branches need some special case code at the * end of the TB, which is complex enough that it has to * handle the single-step vs not and the condition-failed @@ -12098,7 +12097,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_bx_excret_final_code(dc); } else if (unlikely(is_singlestepping(dc))) { /* Unconditional and "condition passed" instruction codepath. */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), @@ -12132,7 +12131,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) - Hardware watchpoints. Hardware breakpoints have already been handled and skip this code. */ - switch(dc->is_jmp) { + switch(dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -12188,22 +12187,22 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) } done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size = dc->pc - pc_start; - tb->icount = num_insns; + tb->size = dc->pc - dc->base.pc_first; + tb->icount = dc->base.num_insns; } static const char *cpu_mode_names[16] = { From patchwork Wed Sep 6 16:05:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111829 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1148747qge; Wed, 6 Sep 2017 09:29:51 -0700 (PDT) X-Received: by 10.55.10.76 with SMTP id 73mr4007760qkk.205.1504715391262; Wed, 06 Sep 2017 09:29:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715391; cv=none; d=google.com; s=arc-20160816; b=flWCoCDNiVJGWQ+BV7jSG1+PtE34NpmEbLPMxIU4PdLfBwWQvI8jLNnFPofWrwG6TJ mxUuwgtiOtc/vhrF9VlEkhSmOUYfdEdDFe6ee2d3SY7Z6nuyhohTd83gvgG/+yVlI4mS KtSK1ACYc2ebQxoIM1/heMwNm09Gss0DQP/LTVfqsQuRujwdDk0zcr6qf4q0Qakp3nQv CwxrJFVfCIAUjOBWOZWqpTFWhZYpDidv+x67ILHVkkZwMz52cP9oIdwDbTUu023LNbOb 9A61pT4ziMxykmHpW+VcyGzvMEDAYGrDaypeBIuN6+E95YjX6gpQtwLLhp641htxJ2kl UOwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Nw/N7XFADUQ4cz+yLiuI9eEsEgwzSGmakMAgbO2x7d4=; b=kY60O0+hc8FYJTI73z6EfQt2uuchrVJrZOnt9M9ixr/EUpzWbcFAlvnDVpqA30QOMN IyfxLi4QU+triJ6lebCk+cS6C3ytxG0QkczSwXvJGnKCbjkDxHHYVHPtxKi0tgwYS8xx f0PUXJ26hHWgkGsZJfDedwhmGd8q/l0dFtOfxu5fqabvu9vxlTYqNli6M5z5/h28Thnf NTcNZObGtwT6TRnhqbPciSUT4ONmEKCcd+NGHDNNff2vn13H+3iDAErF8GQjQngMN3jZ NTWFXCCiFuU74nMzliaWVPzfXHGE3PpAEJiMsW2my7E0zNXBW5F7AIBfYJIeXc0aGFzf m89g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dceGHqUz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:56 -0700 Message-Id: <20170906160612.22769-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PULL 16/32] target/arm: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002316201.22386.12115078843605656029.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 88 ++++++++++++++++++++++++++++---------------------- 1 file changed, 50 insertions(+), 38 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 4db8978a93..a95c183cee 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11824,32 +11824,12 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) return false; } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int arm_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); - DisasContext dc1, *dc = &dc1; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb = tb; - dc->base.pc_first = tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11860,23 +11840,23 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb = ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b = ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) << 1; + dc->condexec_cond = ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->ns = ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags); + dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->cp_regs = cpu->cp_regs; dc->features = env->features; @@ -11895,11 +11875,12 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ + cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); @@ -11908,6 +11889,36 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) cpu_V1 = cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 = tcg_temp_new_i64(); + + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUARMState *env = cs->env_ptr; + DisasContext dc1, *dc = &dc1; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/etc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { @@ -11916,6 +11927,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns = TCG_MAX_INSNS; } + max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns); gen_tb_start(tb); From patchwork Wed Sep 6 16:05:57 2017 Content-Type: text/plain; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:57 -0700 Message-Id: <20170906160612.22769-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PULL 17/32] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f5c678ef25..e8dc96c28a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUARMState *env = cs->env_ptr; - ARMCPU *cpu = arm_env_get_cpu(env); DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, init_tmp_a64_array(dc); + return max_insns; +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env = cs->env_ptr; + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { @@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, if (max_insns > TCG_MAX_INSNS) { max_insns = TCG_MAX_INSNS; } + max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns); gen_tb_start(tb); From patchwork Wed Sep 6 16:05:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111821 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1134307qge; Wed, 6 Sep 2017 09:19:49 -0700 (PDT) X-Received: by 10.55.156.79 with SMTP id f76mr4354595qke.298.1504714789729; Wed, 06 Sep 2017 09:19:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714789; cv=none; d=google.com; s=arc-20160816; b=nKrJAMRj70aGm91O1vRsT6xm/Fd45SIxNIOgSkbBob58cevhcjwQd1yBYMNiqkI7+M mJfaBQhd2pHAxuMvUp1dgHdfEf8M5CssfW+YmnA00BqNw4dxRkUt3EfInSZu3EohWF56 WKwSvTugfMzs0yuDoj33i6Yq/e8XIPMYJT4gK/rRDUGzlZk3VwXCV21zwAfHRKDpjaEF 6TeZ+LHWWfEmmp8mJrPbYzyU4oc4+GPJWojeR6XOG6eWRwZ9mzPVHYsZpiUSjEANBSeX BBnukzlz1rFJGTxV4yPxCqQ58pBnuWxY54sQg7u2/MhNLP4e3594IWyVpvfuPydDbtLu hENQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=; b=Ap02a//rQDNtoJeaJF7zxSEP1VPiAxCJGsn6Qu2iaEK0Ah7BnI5HGkplaaMXR1KiPA nRNEL/vOy67visvkaOK3v6BtJs5iAv8w2mrTp/5eSKXzpLLopWXNkuxep6UPWHDgrlKB dnOk3ckzABBPolqzeQLYLHd7VDBiIRCgpo4KI7A9cZWkqvBf68cstZneCftEuhHWMXSh swUutVWDPSMI57HrIkA8699lpe2tlbLyMb2CzBxpUzAkXjMwZVeilps0nNfBzoT0InTk RXZhm+SZzXwLEd1TbjDuejhn/Otrl4TDO6h4GMCeOE4kRFjEiFyuKksZLNlEs0CCih7d DHEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kWQ1BaLl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:58 -0700 Message-Id: <20170906160612.22769-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 18/32] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 82 +++++++++++++++++++++++++++----------------------- 1 file changed, 44 insertions(+), 38 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index a95c183cee..3138a23e0c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11893,6 +11893,49 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, return max_insns; } +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condexec + * bits back to the CPUARMState for every instruction in an IT block. So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wrong. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11932,45 +11975,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_tb_start(tb); tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condexec - * bits back to the CPUARMState for every instruction in an IT block. So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wrong. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx = tcg_op_buf_count(); From patchwork Wed Sep 6 16:05:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111825 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1139591qge; Wed, 6 Sep 2017 09:23:27 -0700 (PDT) X-Received: by 10.55.118.3 with SMTP id r3mr4065198qkc.8.1504715006664; Wed, 06 Sep 2017 09:23:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715006; cv=none; d=google.com; s=arc-20160816; b=Yhc2I9nDJhEnj59pcYzxMSrmwyc3SQjpvMk3tsR8eYatgMnLAnK/bT7gmQubVZwQ3T aBHF8ZlSFfVdlR+EJBkZjG4ED1pYI6JM4AINkzZS72F5X7Wxg3XtznLOVyQw0UEsTYAK DeUi+79dCZDpIfsPmKSpDCOHdqkcMlrOpP6ciRYY9WB/OYIUc2/fGFxJovs3KXirrXpf scjXPG3Gxks0OhE4oxCtQc7Mw0rskGPDPVkdT6tiWD6mHMFss65viZLQyJR7ro/eFC6W wMBs8RT+sXh5W1Tz3d0NZhrI96KUAExCh6SQzvryqF4+vRcSU9nmTZ7TpLscaTEoXY/R vchQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mV9q2OZFA8DKM3HzKR5SvCdCSSgw5pdh1P+rBA4ZOSE=; b=QPusmwnInIP6d10WPaUJRgY8IUgd1/UkY/Yc9z+8xU95m0ZrCde7pKgygsl9HqMcZl HMPPr1HxcymEfAtXqYz1tw4fZE/yF0Dd8yLFLBrtE7yrfhzrxeC2gUfYnukKgNR+/4Ir 9xITKu1We6F6W+i2x7kBDsZ/g/Od5kYoYbwvz3yEpgjvpFBlZ6v1aiUaAhLb3KhvbSLS KyWSd//4ynd0IFxTcnu7096hPiViyZNW5RNNYkfZK2I/cwYqxyCQjGJRScUBoEJTo4Dj vhLipVsMEpMVoeQzqpXRUujwQJPqQQY08HfhJMUAJ79Kime5aYN5sHdN+sBZ3v2Y2r2g VyWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cilY5cuq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:59 -0700 Message-Id: <20170906160612.22769-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL 19/32] target/arm: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3138a23e0c..005157225c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11936,6 +11936,16 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11979,10 +11989,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + arm_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; From patchwork Wed Sep 6 16:06:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111808 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1120679qge; Wed, 6 Sep 2017 09:10:56 -0700 (PDT) X-Received: by 10.237.35.238 with SMTP id k43mr2793893qtc.214.1504714256819; Wed, 06 Sep 2017 09:10:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714256; cv=none; d=google.com; s=arc-20160816; b=KzjmOW4nZqw2roEPOwrQhtVCizNIZQg7tuymlcXnHluK5+e2x0vqWauYwSanNKHzy2 wJ6nWKV8FLcgfGisvrrzOOTnZX9j83vEat1jE7UqVniYOEy9lA/7G5fdOTVPZastCx91 aZlcWrgf9FK8kGNBn0WrB/xY+Pb6m0Hv17rcHX0qQUE9T5CDUiNVxN8GW9/Ub8iz/Tgv jZ8Gxm1ODXvUHOF1QE7l5dXjr0o1qxp+KRaSZXNj0nGLUvsBhbDLq7evBngbw4dKcPmO 3xNiX0aM834e/NVjnocNwPaDR+t/rh6+pq/2b2nYgpt2OmqG+2iKrV2Enhj8P4MVK5Hi 4Abg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=rK5vcMmer/3Wux+HRmWMOMZFIkyWPjSSJlQhe5ZOLqw=; b=kJT6Mkm/FSkoWVR9+TM1Mx2Z8TZD9gTbktraGrZgKIA7A66w89joQ1BSSzwhNXAAAj S3TKQLhBaPMYBSFwpza55QgMtf+dT6urU+n+tYU60UTNFbF22rWILg7XJIy0kkfaWpzT 3Gy3kDj7tEQJdWTykBkTp6OfAwY1jU7kf/b28dMInqHuFsMskJblxZ7BWukyt8Jba4qc uWXuA7I1IkgS2AM7mKbMSvXFxMIkZV5dMGKKp6/XUhR93dFfP9ix9B5vbsBEn18IPFgD M3JQySpRD9JoiHw0lCv0eW/SfOETDWQ2dFm7jHxjivUoQEOoF1g2jdbwIcyfO0pBa5H1 9Xhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DvCXQqsu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:00 -0700 Message-Id: <20170906160612.22769-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL 20/32] target/arm: [tcg, a64] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 ++++++++-- target/arm/translate.c | 55 +++++++++++++++++++++++++++++----------------- 2 files changed, 44 insertions(+), 22 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e8dc96c28a..1eab10696c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11259,6 +11259,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, return max_insns; } +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11290,8 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 005157225c..2f5f65310d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11946,6 +11946,33 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 0); } +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc += 2; + dc->base.is_jmp = DISAS_NORETURN; + } + + return true; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11994,28 +12021,15 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be executed */ - dc->base.is_jmp = DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->pc += 2; - goto done_generating; + if (bp->pc == dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { @@ -12137,6 +12151,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ @@ -12158,6 +12173,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) */ switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -12211,7 +12227,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) } } -done_generating: gen_tb_end(tb, dc->base.num_insns); #ifdef DEBUG_DISAS From patchwork Wed Sep 6 16:06:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111831 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1154572qge; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:01 -0700 Message-Id: <20170906160612.22769-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 21/32] target/arm: [tcg, a64] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Lluís Vilanova Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 17 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1eab10696c..e94198280d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11267,6 +11267,30 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc += 4; + dc->base.is_jmp = DISAS_NORETURN; + } + + return true; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11303,25 +11327,15 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp = DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc + dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. */ - dc->pc += 4; - goto done_generating; + if (bp->pc == dc->base.pc_next) { + if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) { @@ -11392,6 +11406,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -11429,7 +11444,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, } } -done_generating: gen_tb_end(tb, dc->base.num_insns); #ifdef DEBUG_DISAS From patchwork Wed Sep 6 16:06:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111830 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1149789qge; Wed, 6 Sep 2017 09:30:38 -0700 (PDT) X-Received: by 10.55.12.133 with SMTP id 127mr4049075qkm.251.1504715438699; Wed, 06 Sep 2017 09:30:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715438; cv=none; d=google.com; s=arc-20160816; b=V1mkJbSEbAkFmm0x9UZWog4cNGg9hdy6QZWk98+na/xdZT1oN2o4IP0UrX2ETFBMPP MGUx53RLFGHXB1gDCug6yXAij8JTBSd5U1WP71MkoGkj3QbfUAbcbaAcs+/bcLQUiaii huBPPDrAxX6iU3DOhk6BDn0Veiz8JhKnhwfqsHkWjbxHwsbkrCJSUfOuVzRC22l4URI3 HC7ZYPfy5jwaL6oU1ajKYhIrRuoULhnkap1eklvzuM4+57wmHdOF2/PPVE9zSebchBvJ fcitXFs9fCaYnhQSGiP+IGAiVrJXsM0uWnOYBxiFy6Zcq8Kzr4kszT6+IUYKwLuq9UGu dc9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Tmhd7lJTCptCpYf1L1lrkBjfQN41pZppSXIWh62yW1E=; b=JGwYB5I7kXQgLWRfP/yrbs7X8F9WzalnG4Y6MBjtlVr6jctjuvHidhYfhJlUNVT8z0 THvjl/UJ8Vq125HaGTzc9pQwTc/Qf57ARuEw8hDWa3DcHV0Y+ejavUTuKMnkw/aclTDW Fit0HwjrIV+Xoq0wJwWFUKm/Db7dcRud+PEBDeTjpD14mFKBmJ3kbB2Wuw7Hh5hq1Kby l+T7U1+9h8R0dH2Arwr47DcOBGLO+/ya8lSqcSLcB+c8X2tMCkqQZrLP2i8IvCO0wrsb b9a+897x9MnetRgykM8+vMAzkTUxzbV8qDFpzhytClX08T3dM319YSOPcbxtC8DwfBxv kbLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XCaqWd0/; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:02 -0700 Message-Id: <20170906160612.22769-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PULL 22/32] target/arm: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/translate.c | 165 +++++++++++++++++++++++++++---------------------- 2 files changed, 91 insertions(+), 75 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.h b/target/arm/translate.h index a804ff65ac..e8dcec51ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f5f65310d..5737299943 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11880,6 +11880,8 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ + dc->next_page_start = + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); @@ -11973,14 +11975,93 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp = DISAS_NORETURN; + return; + } +#endif + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns == 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp = DISAS_NORETURN; + return; + } + + if (dc->thumb) { + disas_thumb_insn(env, dc); + if (dc->condexec_mask) { + dc->condexec_cond = (dc->condexec_cond & 0xe) + | ((dc->condexec_mask >> 4) & 1); + dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask == 0) { + dc->condexec_cond = 0; + } + } + } else { + unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc += 4; + disas_arm_insn(dc, insn); + } + + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp = 0; + } + + if (dc->base.is_jmp == DISAS_NEXT) { + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. */ + + if (is_singlestepping(dc)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((dc->pc >= dc->next_page_start) || + ((dc->pc >= dc->next_page_start - 3) && + insn_crosses_page(env, dc))) { + /* We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + dc->base.is_jmp = DISAS_TOO_MANY; + } + } + + dc->base.pc_next = dc->pc; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUARMState *env = cs->env_ptr; DisasContext dc1, *dc = &dc1; - target_ulong next_page_start; int max_insns; - bool end_of_page; /* generate intermediate code */ @@ -11999,7 +12080,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->base.num_insns = 0; dc->base.singlestep_enabled = cs->singlestep_enabled; - next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -12036,83 +12116,18 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_start(); } -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp = DISAS_NORETURN; - break; - } -#endif - - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debugged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp = DISAS_NORETURN; - break; - } - - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond = (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask == 0) { - dc->condexec_cond = 0; - } - } - } else { - unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc += 4; - disas_arm_insn(dc, insn); - } - - if (dc->condjmp && !dc->base.is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp = 0; - } + arm_tr_translate_insn(&dc->base, cs); if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page = (dc->pc >= next_page_start) || - ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc)); - - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - dc->base.num_insns < max_insns); + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { From patchwork Wed Sep 6 16:06:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111826 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1140108qge; Wed, 6 Sep 2017 09:23:48 -0700 (PDT) X-Received: by 10.55.36.3 with SMTP id w3mr4168532qkg.284.1504715028223; Wed, 06 Sep 2017 09:23:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715028; cv=none; d=google.com; s=arc-20160816; b=aMoX5rdCND7wNshbU9SyqZjTJq9nTyvhw94V5BEyDsLUoWu7moyUyQdn01DMEKbTO1 5qg3O65IB9be7PjoqqIlGeNVLew+K116kOJN002y/KR3PvPo/qh7mxrPLkVi0eFeohlY XwuGPgLmUbh7KrVUnIaE8qfBgEDp8/JFaX0sRvEz+TsrHQB8kCGDqb2uSir95qljbqGw Smd1MnoiLYOnVL1W4iRDi+92lQ819QrnF2GKOepE32qUgAnuh0baDuk0td5nHE9YcMPj Id/Iw2+4V0F2DxB4NmP/lu5UCa03NmHAfCOOisyltVTn6ISelnE9YmGuTL2O5CL1T7l7 RXYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xElHN/zfdPbhnMF3R21WRLSn0KBWPuHQqnySWytQRsM=; b=TmJIKdHwzk5AA9nktFXy3RHtAXWnJmIQoKnrOGg++eEc42b6N5OvXHS6B+ZVKYvXnr K41ONkawjk8LnVIBw86/WsTf5857s9ffVjiaioMNx7JyIk/EmV+zCWwK8p5VDBPhTvrX f8Nf8f5EfBPCRI0trb1Zk0YLXkT9tQKCqdo8pIXSQP2LBn48urqNIT12LgvBDRwYuPwR OzE1loAfI4njvoDiH64NoNZGDkJopdNQXDUY5Y8R5s/O8JU3i/JRr4nD3ALUP15hGo5b VPIXy5h7kF8qw27cZYIOBAH7gD/Q4xxs51GKTsdjV40DUI6Lm71vP3OlnzIUy5vS1+fb cFZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OEq4M0Y3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:03 -0700 Message-Id: <20170906160612.22769-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL 23/32] target/arm: [tcg, a64] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 28 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e94198280d..f959f4469a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11254,6 +11254,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); + dc->next_page_start = + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); return max_insns; @@ -11291,12 +11294,43 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns == 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp = DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); + } + + if (dc->base.is_jmp == DISAS_NEXT) { + if (dc->ss_active || dc->pc >= dc->next_page_start) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } + + dc->base.pc_next = dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env = cs->env_ptr; DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; dc->base.tb = tb; @@ -11306,7 +11340,6 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->base.num_insns = 0; dc->base.singlestep_enabled = cs->singlestep_enabled; - next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -11342,42 +11375,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, gen_io_start(); } - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debugged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp = DISAS_NORETURN; - break; - } - - disas_a64_insn(env, dc); + aarch64_tr_translate_insn(&dc->base, cs); if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled || + singlestep || dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several times. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); From patchwork Wed Sep 6 16:06:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111816 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1129010qge; Wed, 6 Sep 2017 09:16:18 -0700 (PDT) X-Received: by 10.55.156.79 with SMTP id f76mr4338392qke.298.1504714578492; Wed, 06 Sep 2017 09:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714578; cv=none; d=google.com; s=arc-20160816; b=MVt/Xb6XMCvWsPvfy45c0b36OOrLx0qc+7VUXBqt40iYfz7pRZ0Asd66qLvjY8C4JR GZif+H+Blb2yWWg26Mz7XzOqWGsjnxH/6jzPzQ+x8BpjvIiOUXNxAN85UWprVr6FgSMR 5WznwMRauZXtMcvAqcVbz0KqwfZMY+yiZ9iF27dowAzo3/bYMOSWAB4vrflHF8skC78z d7hLs9FkJSIA9T6MArU4aZH7j3EiYQDwRd3eS2fujlHwfH6aBSTPTfDJe54MzGBsLce6 xbNO8Io//gV1gng1UlFsC3wCwI2831gZxAXsIHw28D0+UjVvbVGfIR3iu4Wg403tVAlL ZFEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=udUFVDShR2S/ublVBwFZxFSZzoHnpVkH6YgeO1JXXp4=; b=qFDy15WoaG3+uO5Jy3bd61WEoSXUc4oJxuXfE/yMzoyeDyrZ4wcVFPxrU2C4GnGdEX MDnpnwMUTW/gND2JGGLP/PmfIiqHKzpcGOuI4mbQbITp/6hS93+aw+r51/la+8HsLdko bu13TyYA8LOuXsuUng3LxHet1l/csKGFuq6abATm1BpISEUKJPOlX5ateSzlJ6BtNn4R 7Gy1ADKB/HdsaGdW7A73L95IVlO4Qvi5JXVKAzKZ6oifXM6ohvTSdLS1uY1G8SlW3+KS +P3MBg3/jbF95jwT4yM6w+wMVT8hPN2QytBhiIFeY/oy02ClQxWM4/WgifyCd9Rl1YD0 B6JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XLrOqJql; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:04 -0700 Message-Id: <20170906160612.22769-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 24/32] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 161 ++++++++++++++++++++++++++----------------------- 1 file changed, 84 insertions(+), 77 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5737299943..10527b50c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12057,85 +12057,13 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->base.pc_next = dc->pc; } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc = &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; - - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); + DisasContext *dc = container_of(dcbase, DisasContext, base); - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. */ + cpu_abort(cpu, "IO on conditional branch instruction"); } /* At this stage dc->condjmp will only be set when the skipped @@ -12241,6 +12169,85 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc = &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/etc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns); + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc == dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } + } + + if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + gen_io_start(); + } + + arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + arm_tr_tb_stop(&dc->base, cs); gen_tb_end(tb, dc->base.num_insns); From patchwork Wed Sep 6 16:06:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111815 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1127400qge; Wed, 6 Sep 2017 09:15:16 -0700 (PDT) X-Received: by 10.200.39.188 with SMTP id w57mr4607988qtw.285.1504714516685; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:05 -0700 Message-Id: <20170906160612.22769-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PULL 25/32] target/arm: [tcg,a64] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Lluís Vilanova Message-Id: <150002558503.22386.1149037590886263349.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 127 ++++++++++++++++++++++++--------------------- 1 file changed, 67 insertions(+), 60 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f959f4469a..723e86c976 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11327,6 +11327,72 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->base.pc_next = dc->pc; } +static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { + /* Note that this means single stepping WFI doesn't halt the CPU. + * For conditional branch insns this is harmless unreachable code as + * gen_goto_tb() has already handled emitting the debug exception + * (and thus a tb-jump is not possible when singlestepping). + */ + switch (dc->base.is_jmp) { + default: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + if (dc->base.singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; + } + } else { + switch (dc->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + gen_goto_tb(dc, 1, dc->pc); + break; + default: + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(cpu_pc); + break; + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; + case DISAS_NORETURN: + case DISAS_SWI: + break; + case DISAS_WFE: + gen_a64_set_pc_im(dc->pc); + gen_helper_wfe(cpu_env); + break; + case DISAS_YIELD: + gen_a64_set_pc_im(dc->pc); + gen_helper_yield(cpu_env); + break; + case DISAS_WFI: + /* This is a special case because we don't want to just halt the CPU + * if trying to debug across a WFI. + */ + gen_a64_set_pc_im(dc->pc); + gen_helper_wfi(cpu_env); + /* The helper doesn't necessarily throw an exception, but we + * must go back to the main loop to check for interrupts anyway. + */ + tcg_gen_exit_tb(0); + break; + } + } +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11398,66 +11464,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, gen_io_end(); } - if (unlikely(cs->singlestep_enabled || dc->ss_active)) { - /* Note that this means single stepping WFI doesn't halt the CPU. - * For conditional branch insns this is harmless unreachable code as - * gen_goto_tb() has already handled emitting the debug exception - * (and thus a tb-jump is not possible when singlestepping). - */ - switch (dc->base.is_jmp) { - default: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_JUMP: - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); - } - break; - case DISAS_NORETURN: - break; - } - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->pc); - break; - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); - break; - case DISAS_NORETURN: - case DISAS_SWI: - break; - case DISAS_WFE: - gen_a64_set_pc_im(dc->pc); - gen_helper_wfe(cpu_env); - break; - case DISAS_YIELD: - gen_a64_set_pc_im(dc->pc); - gen_helper_yield(cpu_env); - break; - case DISAS_WFI: - /* This is a special case because we don't want to just halt the CPU - * if trying to debug across a WFI. - */ - gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); - /* The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anyway. - */ - tcg_gen_exit_tb(0); - break; - case DISAS_UPDATE: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_EXIT: - default: - tcg_gen_exit_tb(0); - break; - } - } + aarch64_tr_tb_stop(&dc->base, cs); gen_tb_end(tb, dc->base.num_insns); From patchwork Wed Sep 6 16:06:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111820 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1133318qge; 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X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 26/32] target/arm: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002582711.22386.191527630537864599.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 10527b50c8..2dca196e17 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12171,6 +12171,15 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + dc->thumb | (dc->sctlr_b << 1)); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -12251,20 +12260,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_tb_end(tb, dc->base.num_insns); + tb->size = dc->pc - dc->base.pc_first; + tb->icount = dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - dc->thumb | (dc->sctlr_b << 1)); + arm_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size = dc->pc - dc->base.pc_first; - tb->icount = dc->base.num_insns; } static const char *cpu_mode_names[16] = { From patchwork Wed Sep 6 16:06:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111833 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1159260qge; Wed, 6 Sep 2017 09:37:16 -0700 (PDT) X-Received: by 10.200.20.132 with SMTP id l4mr3899667qtj.10.1504715836094; Wed, 06 Sep 2017 09:37:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715836; cv=none; d=google.com; s=arc-20160816; b=xXm1D/S8LuykEluCutBSSIrwmElITT8Mxoy/VKLe3xL2QRSarbkD4kRx49GKz2gvse 9LJUmE7WYiM2cZ88HzEzZXkiKr6j55AxLduWwq7cuPKaRwjnOBnY6kQLV0LazHBjc7Nt 3tr5Eq7p6mRTN/85S0INsQQgm6Sn0C5kuFSzDstEsaCXJKkcVdkxxAjggJqEAAwGRXfB vymgLjBUNT6c96fNn8cbbwrKa5bdnzaa9N1TuZR+00FNJtF+rewiOyJhOfAeFIfTN9OA eYnByBMWxYlkaHl7/ovbO9Ym27O6Xna1NhmwwWSNOw5s3mKQ6Y/DJAyFUzkGkrUUqs3P uSyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=zTHnNo4fpTvvHZYmEhurskvtWnhzILXVy4UhrbbCYXM=; b=m3uncRt0H0Rg3H1SHWyD8gXY29Iw+4AzoCeVWr6CqsmbOMlJtTvkm0XbDdNik1pXFT KGMQ1fdHPsTNwMH6V2CRxP5kMbhsrMtpYY/2FVyaCJgjRJhxjR/aFu5PPoXRLU3M5GR3 6lPJkMy8jVcGscKwhvNLmBtjaRdlmien+GzrRnHAlSbfp6GCSQt7k+ChlYuILfmfWZIX 0SE4TcrHbjQWuUkd4y3zP0nVKCKhxecpVjDJE5vOYCpsef6Ic7mtWRoxNTJRWlXNKzw0 PROxJMMbNOqiQ6kHiKwHeR5fnBUZvWE8uZ+ikwy18MTuc8VLYq7g7noWDw50DsTbPckM Xe5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D8pQR9sj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:07 -0700 Message-Id: <20170906160612.22769-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PULL 27/32] target/arm: [tcg,a64] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Lluís Vilanova Message-Id: <150002606914.22386.15524101311003685068.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 723e86c976..1973a36462 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11393,6 +11393,16 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) } } +static void aarch64_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11468,18 +11478,17 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, gen_tb_end(tb, dc->base.num_insns); + dc->base.tb->size = dc->pc - dc->base.pc_first; + dc->base.tb->icount = dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); + aarch64_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - dc->base.tb->size = dc->pc - dc->base.pc_first; - dc->base.tb->icount = dc->base.num_insns; } From patchwork Wed Sep 6 16:06:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111819 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1131336qge; Wed, 6 Sep 2017 09:17:49 -0700 (PDT) X-Received: by 10.55.114.194 with SMTP id n185mr4608919qkc.180.1504714669901; Wed, 06 Sep 2017 09:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714669; cv=none; d=google.com; s=arc-20160816; b=bIsEyDOsafq1cLHPey1h/Max8iMNdyHgqH1/Cgg20o+zbLkSaMP166r/55p18ZHhNv CXMIR1yxJfPC7Xcg53vxZsbu2bCM0gWZ/1LpJlZ8rMCQnVX5Jiduh3wZE17woFW9m1Gu V+lXutr0rSCUuTXTT0laXv2palN4m2xhZNMpwdDGdmkoDrgFVNZBUBcEuh15VYWGdJw/ GkPADN7L9jK5iDNdN+EeFyYWno8BRQIATNiqbydORzeEQeYB3dRq0HZ671XADYw3LXps Sc4hVhUYjb/pBqYbVihoBwzxKj3r1svGk1/dnVQ+4OVQwGuoDOpc29N6TyDJWB/QdIWt I+dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Ih77dH1LlHs+t4aUfyHaKRK6r0XUJB+LahRMCCHcq1E=; b=Xf8q+T+vZ0EuE59BZgIXoYu7U1zCcAYdYH7aoAnWOMTlTKsW+PuUN6oYj3YvU31mHd 80r4F6Dg+lpA7BCECwiRSaC9BN4a6Ut+8hb6dH6ShguKp5ocXn8xeRwRCSD2JTV9Lv6a 3ayUArnb8tvqu97uRnmUpycFTKxKKS5xqto9xNFmUjNZ9oI96LKTeo+mVbqRGoEQnves P20FC6kik7GgfZaO0A0HzegtWGQHxiCRFVisCml7wCEsU0xf4TZY+8aNhiiQ5VX5R1xK 0OfbTuwCphptwA1vhXjHjfNh4d3CTMrPjTmgLE5ozfpIFIbkrVYHRyaWyGGmnIJQsQtj dvaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=diQlWe4j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:08 -0700 Message-Id: <20170906160612.22769-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL 28/32] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002631325.22386.10348327185029496649.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 +--- target/arm/translate-a64.c | 107 ++++++++------------------------------------ target/arm/translate.c | 109 +++++++++------------------------------------ 3 files changed, 41 insertions(+), 183 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.h b/target/arm/translate.h index e8dcec51ac..55d691db40 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -150,21 +150,15 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1973a36462..25c6622825 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11262,6 +11262,11 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, return max_insns; } +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ + tcg_clear_temp_count(); +} + static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -11325,6 +11330,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->base.pc_next = dc->pc; + translator_loop_temp_check(&dc->base); } static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -11391,6 +11397,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next = dc->pc; } static void aarch64_tr_disas_log(const DisasContextBase *dcbase, @@ -11403,92 +11412,12 @@ static void aarch64_tr_disas_log(const DisasContextBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc = container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; - - max_insns = dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - aarch64_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled || - singlestep || dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - aarch64_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - dc->base.tb->size = dc->pc - dc->base.pc_first; - dc->base.tb->icount = dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif -} +const TranslatorOps aarch64_translator_ops = { + .init_disas_context = aarch64_tr_init_disas_context, + .tb_start = aarch64_tr_tb_start, + .insn_start = aarch64_tr_insn_start, + .breakpoint_check = aarch64_tr_breakpoint_check, + .translate_insn = aarch64_tr_translate_insn, + .tb_stop = aarch64_tr_tb_stop, + .disas_log = aarch64_tr_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2dca196e17..dabd5eb89a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11936,6 +11936,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_movi_i32(tmp, 0); store_cpu_field(tmp, condexec_bits); } + tcg_clear_temp_count(); } static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) @@ -12055,6 +12056,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } dc->base.pc_next = dc->pc; + translator_loop_temp_check(&dc->base); } static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -12169,6 +12171,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next = dc->pc; } static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) @@ -12180,99 +12185,29 @@ static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } +static const TranslatorOps arm_translator_ops = { + .init_disas_context = arm_tr_init_disas_context, + .tb_start = arm_tr_tb_start, + .insn_start = arm_tr_insn_start, + .breakpoint_check = arm_tr_breakpoint_check, + .translate_insn = arm_tr_translate_insn, + .tb_stop = arm_tr_tb_stop, + .disas_log = arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - DisasContext dc1, *dc = &dc1; - int max_insns; - - /* generate intermediate code */ + DisasContext dc; + const TranslatorOps *ops = &arm_translator_ops; - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ +#ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; - - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - arm_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - tb->size = dc->pc - dc->base.pc_first; - tb->icount = dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); + ops = &aarch64_translator_ops; } #endif + + translator_loop(ops, &dc.base, cpu, tb); } static const char *cpu_mode_names[16] = { From patchwork Wed Sep 6 16:06:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111832 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1156608qge; Wed, 6 Sep 2017 09:35:20 -0700 (PDT) X-Received: by 10.200.3.195 with SMTP id z3mr4689192qtg.259.1504715720231; Wed, 06 Sep 2017 09:35:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715720; cv=none; d=google.com; s=arc-20160816; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:09 -0700 Message-Id: <20170906160612.22769-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 29/32] target/arm: [a64] Move page and ss checks to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.13.5 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 25c6622825..9017e30510 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11206,6 +11206,7 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = arm_env_get_cpu(env); + int bound; dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11254,8 +11255,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); - dc->next_page_start = - (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* Bound the number of insns to execute to those left on the page. */ + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound = 1; + } + max_insns = MIN(max_insns, bound); init_tmp_a64_array(dc); @@ -11323,12 +11330,6 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) disas_a64_insn(env, dc); } - if (dc->base.is_jmp == DISAS_NEXT) { - if (dc->ss_active || dc->pc >= dc->next_page_start) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } - dc->base.pc_next = dc->pc; translator_loop_temp_check(&dc->base); } From patchwork Wed Sep 6 16:06:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111834 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1161019qge; Wed, 6 Sep 2017 09:38:30 -0700 (PDT) X-Received: by 10.55.31.211 with SMTP id n80mr4026045qkh.179.1504715910115; Wed, 06 Sep 2017 09:38:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715910; cv=none; d=google.com; s=arc-20160816; b=UbdnThCzo1mFhNnT43iF7m4ejlTKPqy/wKG6DME04++eMm97++PZItJ0LPEsflZ8Df /QJV1knRGznigpnrAf3Jzcy0Qa4rmZOk4rpAtTvIpIkdE6eCKY6sxzuHjMG8n+1i8Gks YmOqLaa8uxjtyb67HYapiGi47nytDZdEvLt2cKwTED/kf9yqBm2aAINU1bTcFK3g4E5m sWAIY1wuJpy6me+iAfWvd5FGE1bb3DHDDkypVJMohzpDDd0AwdSz1pNG4dHhyWEDHxvh x56iLQy7iU/LUkHHkk3c+hOWBvKHhzHNmbfSxPdl2hlc9vbQUW8rQwiU6KQdyP+Q63PY 6uIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=FaKvXHHGiYR75jbxerCmzlpe42rCvutIo5e8u1b0PMw=; b=1A04MeZ8EDwunpVwBVKFOKdOcBbT69rM1g9z4BhYu4pL+Zz5waV+Ds0/qTjQ0Np5OH 44kTrPfU1pGu7r0ismn5Ee+C9BLQr8orCqgVpMFnmolNGl9sKf41wwZw8jMosN7kGBY+ c7zI6d+EdT3dmu9Dvr91iXaEF4vlCI7kfmlX6/Kr5onq/rxgQMTd/Z5OoqogFoItm0gQ xStvpOmdEDDHJ14ZbJlmjcq9n1mSRUCjUOY/EV/rLdLPmTgjRx+TS80miQfOmjeL17cb UOnHH1uEDwegWscGQ9xbMj/k/If0XqA/SQiZp0VL9uzHGw3eMgC+giLy2JFTAv4e+A3v 1mfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Kic5+E7N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:10 -0700 Message-Id: <20170906160612.22769-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL 30/32] target/arm: Move ss check to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We can check for single-step just once. Reviewed-by: Emilio G. Cota Reviewed-by: Lluís Vilanova Signed-off-by: Richard Henderson --- target/arm/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index dabd5eb89a..0dd24aad90 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11883,6 +11883,11 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, dc->next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* If architectural single step active, limit to 1. */ + if (is_singlestepping(dc)) { + max_insns = 1; + } + cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); @@ -12037,11 +12042,9 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - if (is_singlestepping(dc)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } else if ((dc->pc >= dc->next_page_start) || - ((dc->pc >= dc->next_page_start - 3) && - insn_crosses_page(env, dc))) { + if (dc->pc >= dc->next_page_start || + (dc->pc >= dc->next_page_start - 3 && + insn_crosses_page(env, dc))) { /* We want to stop the TB if the next insn starts in a new page, * or if it spans between this page and the next. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:11 -0700 Message-Id: <20170906160612.22769-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 31/32] target/arm: Split out thumb_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 80 insertions(+), 41 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 0dd24aad90..9e7bfbcf0c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11981,11 +11981,8 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } -static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +static bool arm_pre_translate_insn(DisasContext *dc) { - DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUARMState *env = cpu->env_ptr; - #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ if (dc->pc >= 0xffff0000) { @@ -11993,7 +11990,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); dc->base.is_jmp = DISAS_NORETURN; - return; + return true; } #endif @@ -12012,56 +12009,85 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->base.is_jmp = DISAS_NORETURN; - return; + return true; } - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond = (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask == 0) { - dc->condexec_cond = 0; - } - } - } else { - unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc += 4; - disas_arm_insn(dc, insn); - } + return false; +} +static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +{ if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp = 0; } - if (dc->base.is_jmp == DISAS_NEXT) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - if (dc->pc >= dc->next_page_start || - (dc->pc >= dc->next_page_start - 3 && - insn_crosses_page(env, dc))) { - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - dc->base.is_jmp = DISAS_TOO_MANY; - } + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp == DISAS_NEXT + && (dc->pc >= dc->next_page_start + || (dc->pc >= dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp = DISAS_TOO_MANY; } dc->base.pc_next = dc->pc; translator_loop_temp_check(&dc->base); } +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + unsigned int insn; + + if (arm_pre_translate_insn(dc)) { + return; + } + + insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc += 4; + disas_arm_insn(dc, insn); + + arm_post_translate_insn(env, dc); +} + +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond = ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask == 0) { + dc->condexec_cond = 0; + } + } + + arm_post_translate_insn(env, dc); +} + static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -12198,12 +12224,25 @@ static const TranslatorOps arm_translator_ops = { .disas_log = arm_tr_disas_log, }; +static const TranslatorOps thumb_translator_ops = { + .init_disas_context = arm_tr_init_disas_context, + .tb_start = arm_tr_tb_start, + .insn_start = arm_tr_insn_start, + .breakpoint_check = arm_tr_breakpoint_check, + .translate_insn = thumb_tr_translate_insn, + .tb_stop = arm_tr_tb_stop, + .disas_log = arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc; const TranslatorOps *ops = &arm_translator_ops; + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops = &thumb_translator_ops; + } #ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { ops = &aarch64_translator_ops; From patchwork Wed Sep 6 16:06:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111827 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1140230qge; Wed, 6 Sep 2017 09:23:53 -0700 (PDT) X-Received: by 10.200.10.12 with SMTP id b12mr4306103qti.152.1504715033411; Wed, 06 Sep 2017 09:23:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504715033; cv=none; d=google.com; s=arc-20160816; b=Y5EKPKU5dX1Y69/im+0XL29XfzI2ttFm6Ruhea6M3DPyp38ICHqorCMy8wFD+ILc+G G+AOlXyi0rb5WY7E5rie8bzBJRVgBLTOJ/5ogY9B+d+2R4zFmrsShpHzzsh9pYQ5NWcr ZW8e6h9S5R98+tZX5vsE6W4IwUfDN0+Sa1SFSCQUmz+VX0venab19WMxsdVAeKUY0JOL 8WYNf1jl+06qLKJ/jFZx4o7aUU1lZSU5nx+U4QVnFXYnVak+ZJcvaQYI0NTk4AAod2bw lFMOR4Ed1k9omKVECX8nlzB/YNU5MHBo7VdCQCCTuR7+y4jROgCtPx6Lo10SeZCWl5ol DLgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=FcT2poeH+q1L1w+cKeuwQSS5u5zh9VSMqgupWpqmAAU=; b=O/ZF7EVVTXyDtUvMxs7PRtjc7RY8ZkaAc1p/O1HBJ6xFVyTopKoNhDEl3Y6zBFcRH6 u2vh/gZiy38WBx6nAwNg36oGtCg9aebfnQF0e5hPEbeEulhChxcoodwLSR+PT+YN/wIW HLzdtCMsH9P1GwJfWIKWgMQ83mi7CNh89wuw1/qwrbBa4DQcQKegDu/ZkTyuWiKyM2NH kVhyZjXAiTdX9181H2TaXnWNE9hBX34/TATgsNIrNbC3EqoFyXfxGyff1tyjEI1Dbns7 L/+H531MYB0Jj1CGQu89b32LR6lhJv1+UOfbr2c/CdQIiY3fJlb3/oHQ8v3PCn24xvHu vA6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WEZRS3Zj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:12 -0700 Message-Id: <20170906160612.22769-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 32/32] target/arm: Perform per-insn cross-page check only for Thumb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 25 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e7bfbcf0c..6946e56a3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11888,6 +11888,13 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, max_insns = 1; } + /* ARM is a fixed-length ISA. Bound the number of insns to execute + to those left on the page. */ + if (!dc->thumb) { + int bound = (dc->next_page_start - dc->base.pc_first) / 4; + max_insns = MIN(max_insns, bound); + } + cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); @@ -12015,34 +12022,12 @@ static bool arm_pre_translate_insn(DisasContext *dc) return false; } -static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +static void arm_post_translate_insn(DisasContext *dc) { if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp = 0; } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - * - * We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - if (dc->base.is_jmp == DISAS_NEXT - && (dc->pc >= dc->next_page_start - || (dc->pc >= dc->next_page_start - 3 - && insn_crosses_page(env, dc)))) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - dc->base.pc_next = dc->pc; translator_loop_temp_check(&dc->base); } @@ -12061,7 +12046,10 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->pc += 4; disas_arm_insn(dc, insn); - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* ARM is a fixed-length ISA. We performed the cross-page check + in init_disas_context by adjusting max_insns. */ } static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) @@ -12085,7 +12073,27 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } } - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* Thumb is a variable-length ISA. Stop translation when the next insn + * will touch a new page. This ensures that prefetch aborts occur at + * the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp == DISAS_NEXT + && (dc->pc >= dc->next_page_start + || (dc->pc >= dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp = DISAS_TOO_MANY; + } } static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)