From patchwork Fri Sep 8 19:08:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 112133 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp708215qgf; Fri, 8 Sep 2017 12:10:21 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6ron6oXaPN2VF82By+tXYkJUEAE+XWx/yWANbsKJUwrkGw7Ox5xHPJ1hqG9b6XP3JRYT61 X-Received: by 10.80.179.17 with SMTP id q17mr2897834edd.131.1504897820935; Fri, 08 Sep 2017 12:10:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504897820; cv=none; d=google.com; s=arc-20160816; b=WthmSCNIHzYD6QlhE8q3GZTr1Z2Hfr6XzCUO1uGDOFeRwMbZN+BuiZhYOvipcWjp+g 6US7Zd9yD3B3xQCekjjr1W8NDzqQgps2ByKYIW6w5eET846mgLJfvblK9Y5wrpre1aEd 1idvYnpAHF/FyJwSRWXO0pbOUpK47iR+CA0g3SRpmY+FtUjnFoJBRNOAwtx+HcHwoCjI ggv8RpgjRsAZT2ioYYSs0AarUsUfqWmscwWfU+JAoHflOzlTGTFovC0oBLA2pmSaMqZ9 ZAt9fFyK9GTdC9EAuERJFABhcXw1XzhHLxsC6YNNETDXwCBInrCA6T2svxHMakTmmAjM Sudg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=J0/A76QAE2gRoH8G6o59U3FBZi1v3niHO3GjdDR1dT8=; b=PAc+3l3t9u1UJtfmE6aIqKw86iok67FI/s2BkrzetapGqLmEA6eBLfdvdNS+DomAaO 4wEQju0/kRk2Y4RPjiJqZw8aaKcbjE5EhtMg6BTXpLmEJFLlIIvQ/2ZwtWDl7Gvo9FGp vF3KhXLZTdBhO9gDvLuY/knh0LY5rbDfVeQ/hTh97qMG7VORVXiPgWV6fRTyl1LYxpp0 EEajz4NP6jQBTT7gKCUuSe3mgJvNgLU8Qy7a1FFuoaJ738YFAikSyk0MgX1xbmfSbvkB AhGek3k98rX/dD1wbW7HnK4T7Q5PwYTW4YNLNKENggIbpGO6yD3c3adW34hBJXc72bb5 zg1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=lR1MZf5O; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b50si3070630edc.312.2017.09.08.12.10.20; Fri, 08 Sep 2017 12:10:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=lR1MZf5O; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 76DE3C21CA5; Fri, 8 Sep 2017 19:10:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5F234C21E84; Fri, 8 Sep 2017 19:10:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5B54EC21DC8; Fri, 8 Sep 2017 19:10:01 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id D4F21C21F0E for ; Fri, 8 Sep 2017 19:09:57 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v88J8aaR009863; Fri, 8 Sep 2017 14:08:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1504897716; bh=XJZzJXEA/umRuhp/elhW0ZXFmlQGsL4PgVJFdqu0+Ec=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lR1MZf5ODIAm5VTBkdPF9VMQG9sxBjrOnaHMBR6VI9PvYJkd5xOzQaWLdrw+KJUpq 0zdVtzF2T2VTF8n8QsmGBehXVHzcVyS/lcMDretre5455Mqztl0ddKjToIe366NtgN 1M/TYPfFv0uf51vGQeRNz3Fj6UiLeJBO7XcfvGi4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8ax3023193; Fri, 8 Sep 2017 14:08:36 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 8 Sep 2017 14:08:36 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 8 Sep 2017 14:08:36 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8ac6021719; Fri, 8 Sep 2017 14:08:36 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v88J8a302538; Fri, 8 Sep 2017 14:08:36 -0500 (CDT) From: Suman Anna To: Uri Mashiach Date: Fri, 8 Sep 2017 14:08:24 -0500 Message-ID: <20170908190825.21515-2-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170908190825.21515-1-s-anna@ti.com> References: <20170908190825.21515-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/2] arm: am57xx: cl-som-am57x: Use new pinctrl macros X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Commit 6ae4c3efbd62 ("ARM: DRA7: Add pinctrl register definitions") has added new macros for pinmux configuration in line with the kernel definitions. Fixup the current pinctrl data for the CompuLab CL-SOM-AM57x board to use these new macros to facilitate the removal of the old macros. NOTE: The PEN and PDIS macro values used previously were actually defined inversely, a value of 1 in bit position 16 actually means that the internal pullup/pulldown is disabled and not enabled as inferred by PEN. So, previous pinmux config data such as (PDIS | PTU) is confusing as it actually was meant for enabling internal pullup. The data is fixed up only to be equivalent to the previous data. Signed-off-by: Suman Anna --- board/compulab/cl-som-am57x/mux.c | 105 +++++++++++++++++++------------------- 1 file changed, 53 insertions(+), 52 deletions(-) diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c index 0db0609727f7..21449ca029b0 100644 --- a/board/compulab/cl-som-am57x/mux.c +++ b/board/compulab/cl-som-am57x/mux.c @@ -12,97 +12,98 @@ /* Serial console */ static const struct pad_conf_entry cl_som_am57x_padconf_console[] = { - {UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */ - {UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */ + {UART3_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_RXD */ + {UART3_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* UART3_TXD */ }; /* PMIC I2C */ static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = { - {MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */ - {MCASP1_FSR, (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */ + {MCASP1_ACLKR, (M10 | PIN_INPUT)}, /* MCASP1_ACLKR.I2C4_SDA */ + {MCASP1_FSR, (M10 | PIN_INPUT)}, /* MCASP1_FSR.I2C4_SCL */ }; /* Green GPIO led */ static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = { - {GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */ + {GPMC_A15, (M14 | PIN_OUTPUT_PULLDOWN)}, /* GPMC_A15.GPIO2_5 */ }; /* MMC/SD Card */ static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = { - {MMC1_CLK, (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */ - {MMC1_CMD, (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */ - {MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */ - {MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */ - {MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */ - {MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */ - {MMC1_SDCD, (IEN | PEN | M14)}, /* MMC1_SDCD */ - {MMC1_SDWP, (IEN | PEN | M14)}, /* MMC1_SDWP */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CLK */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_CMD */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (M14 | PIN_INPUT) }, /* MMC1_SDCD */ + {MMC1_SDWP, (M14 | PIN_INPUT) }, /* MMC1_SDWP */ }; /* WiFi - must be in the safe mode on boot */ static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = { - {UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */ - {UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */ - {UART2_RXD, (IEN | M15)}, /* UART2_RXD */ - {UART2_TXD, (IEN | M15)}, /* UART2_TXD */ - {UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */ - {UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */ + {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_CTSN */ + {UART1_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART1_RTSN */ + {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RXD */ + {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_TXD */ + {UART2_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_CTSN */ + {UART2_RTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* UART2_RTSN */ }; /* QSPI */ static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = { - {GPMC_A13, (IEN | PEN | M1)}, /* GPMC_A13.QSPI1_RTCLK */ - {GPMC_A18, (IEN | PEN | M1)}, /* GPMC_A18.QSPI1_SCLK */ - {GPMC_A16, (IEN | PEN | M1)}, /* GPMC_A16.QSPI1_D0 */ - {GPMC_A17, (IEN | PEN | M1)}, /* GPMC_A17.QSPI1_D1 */ - {GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */ + {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */ + {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */ + {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */ + {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */ }; /* GPIO Expander I2C */ static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = { - {MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */ - {MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */ + {MCASP1_AXR0, (M10 | PIN_INPUT)}, /* MCASP1_AXR0.I2C5_SDA */ + {MCASP1_AXR1, (M10 | PIN_INPUT)}, /* MCASP1_AXR1.I2C5_SCL */ }; /* eMMC internal storage */ static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = { - {GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */ - {GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */ - {GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */ - {GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */ - {GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */ - {GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */ - {GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */ - {GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */ - {GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */ - {GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A24.MMC2_DAT0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A25.MMC2_DAT1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A26.MMC2_DAT2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A27.MMC2_DAT3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS1.MMC2_CMD */ }; /* usb1_drvvbus */ static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = { - {USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */ + /* USB1_DRVVBUS.USB1_DRVVBUS */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL) }, }; /* Ethernet */ static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = { /* MDIO bus */ - {VIN2A_D10, (PDIS | PTU | M3) }, /* VIN2A_D10.MDIO_MCLK */ - {VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */ + {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */ + {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */ /* EMAC Slave 1 at addr 0x1 - Default interface */ - {VIN2A_D12, (IDIS | PEN | M3) }, /* VIN2A_D12.RGMII1_TXC */ - {VIN2A_D13, (IDIS | PEN | M3) }, /* VIN2A_D13.RGMII1_TXCTL */ - {VIN2A_D14, (IDIS | PEN | M3) }, /* VIN2A_D14.RGMII1_TXD3 */ - {VIN2A_D15, (IDIS | PEN | M3) }, /* VIN2A_D15.RGMII1_TXD2 */ - {VIN2A_D16, (IDIS | PEN | M3) }, /* VIN2A_D16.RGMII1_TXD1 */ - {VIN2A_D17, (IDIS | PEN | M3) }, /* VIN2A_D17.RGMII1_TXD0 */ - {VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */ - {VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */ - {VIN2A_D20, (IEN | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */ - {VIN2A_D21, (IEN | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */ - {VIN2A_D22, (IEN | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */ - {VIN2A_D23, (IEN | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */ + {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */ + {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D20.RGMII1_RXD3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D21.RGMII1_RXD2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D22.RGMII1_RXD1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D23.RGMII1_RXD0 */ /* Eth PHY1 reset GPIOs*/ - {VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */ + {VIN2A_CLK0, (M14 | PIN_OUTPUT_PULLDOWN)}, /* VIN2A_CLK0.GPIO3_28 */ }; #define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \ From patchwork Fri Sep 8 19:08:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 112134 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp708914qgf; Fri, 8 Sep 2017 12:10:59 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6g4qWyD5Rjhy4wsRhU2l6XMLlxztrOWwUxpsM5/+9+h/duoKOzGOVG4FCjc8bX+0Y3y/9H X-Received: by 10.80.206.11 with SMTP id y11mr3036299edi.94.1504897859479; Fri, 08 Sep 2017 12:10:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504897859; cv=none; d=google.com; s=arc-20160816; b=iVS2FLjNmboZxbAOKF5X3kyv3q8bGPfv3pXFtXUpVBIZ9vMWPH3+rwL8mlS0KRAa3K s5DlkBRW+/b6w/aiPOnFi56h65gnPPOIOjRjLti2Kco7ZBhoztBc2j9oEs3InfLUDPTp 9rxGupqkGmvkJM9UZN+K7Xx0/GXl2//pkIrh//2rwxl41UVr3WcKrau2EQOWTWFaEJY4 X3x631lG0ayorl+H/C8htGRLxRMrYNgRJI8S0Q1blJmQ+Tgf1iEvhBCKiazIHNG15m3s rdPc0JamtgpPNIpXKfrL/oF/w0iJ9GiDrXnP3K80RPSk6U9jTHPeJSyuMHY4fqYoMeFR RZSw== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id r55si2484235edd.139.2017.09.08.12.10.59; Fri, 08 Sep 2017 12:10:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=if8pkcf1; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id E1A79C21C34; Fri, 8 Sep 2017 19:10:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 588F3C21F0B; Fri, 8 Sep 2017 19:10:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0D7EAC21CB2; Fri, 8 Sep 2017 19:10:00 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 8FBA0C21EE8 for ; Fri, 8 Sep 2017 19:09:56 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v88J8cBn009868; Fri, 8 Sep 2017 14:08:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1504897718; bh=yjGrYd4sA19s6cXrtMCb5s200UXVn+poz5lgEizQGTE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=if8pkcf1gU4oKYFCrrv0TBiKJMMpHa/sks5Uz+rEifstQtT2DM3aLDM9mecivtkwW pz5qp15c9t3R/iukx9QKVdmwOSLAdwFJli2QVtp2iLUiaiZCotgG3tljGYd7GgPMVi fjwqtKPS5LynyvgYBa7GtUR5uqS1i46AIhUHAcWk= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8cX1031255; Fri, 8 Sep 2017 14:08:38 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 8 Sep 2017 14:08:38 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 8 Sep 2017 14:08:38 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v88J8b2E021736; Fri, 8 Sep 2017 14:08:38 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v88J8b302548; Fri, 8 Sep 2017 14:08:37 -0500 (CDT) From: Suman Anna To: Uri Mashiach Date: Fri, 8 Sep 2017 14:08:25 -0500 Message-ID: <20170908190825.21515-3-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170908190825.21515-1-s-anna@ti.com> References: <20170908190825.21515-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/2] ARM: DRA7: Cleanup old pinctrl macros X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Commit 6ae4c3efbd62 ("ARM: DRA7: Add pinctrl register definitions") has added new macros for pinmux configuration in line with the kernel definitions. Cleanup the old pinctrl macros from the common header file so that they are not used by any new boards. Signed-off-by: Suman Anna --- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index 5eed98ca27a4..55f49c784857 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -12,20 +12,6 @@ #include -#define FSC (1 << 19) -#define SSC (0 << 19) - -#define IEN (1 << 18) -#define IDIS (0 << 18) - -#define PTU (1 << 17) -#define PTD (0 << 17) -#define PEN (1 << 16) -#define PDIS (0 << 16) - -#define WKEN (1 << 24) -#define WKDIS (0 << 24) - #define PULL_ENA (0 << 16) #define PULL_DIS (1 << 16) #define PULL_UP (1 << 17)