From patchwork Mon Sep 11 13:52:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112191 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825760pji; Mon, 11 Sep 2017 06:51:51 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7+5eet8Nmd191ItMIu5w+DkC20oHdNpRzaMg42JYbzfKJsH4OeMcVcswmd57ASubJgWYpf X-Received: by 10.99.97.148 with SMTP id v142mr12222283pgb.413.1505137911167; Mon, 11 Sep 2017 06:51:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137911; cv=none; d=google.com; s=arc-20160816; b=SsvNufbIF8+uLVdXB3XSDxtbxfN3RUcdW8g92M9oyzayQWD8SaWi4m/LgobvPNhBu6 SPmyJCiyCkSwRpSnYKrir3o6XS8i6bfYHqfHuIOP9rIONN/cV4FWo1trYOc18HEF2fgl oUiE/JmkmLR1F597mPpPrr+EcS0oUVA0Y6mkUrZsiCB5uk8N7CQkAFon4D61pUzVgC1u n67PhjaPC8mZV3f07+MdHJn6FTjGBwMMgwY6UIzLJ4KG+hvPcuBpcfuMSa6HDFJECxw5 2LyZ1AGAD8ljhPEr1CvNq5+PSrzeL4MOfzQmFZDoDhxkQzM5ypCbE6zbuIo1o20uGlhV oPUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Cw1uYhjDSVmI8ptdsucthUFSvhXnPYZcwKfVp+ghky0=; b=ERkVyamscu9prqpUU0SIOp0aHqiNyNqPJ4rwipNKoQw88FGSUvcpvlQPX//l+uf+8I iPrz9Tfi5Z9xr6q6Rmb/JnDW3iMBjEsyR08KZUVAg59hOyqQSw0bldRqmOGuHIeR+uVV xNgihg+UANA88ie6zLX1piGB7GpbLP+O0EjN3+icY9+ZyBk6wbxyNloqIW+X/O5cMUZn 19VVq/Nw9vSdDWuAQjAW2cty/U2m0bODRzBSwuFqE7SptV6Gt/TKdpvPTGyC/IypKSFU JEMXROLg5iZUW7Kn22X7XkVRYpklTsWdpUdhpupGqfJWr2TCpJVLgVqeSvCXK/S8MrC2 sloA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id i35si6807301plg.722.2017.09.11.06.51.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7p-0007lo-Gn; Mon, 11 Sep 2017 14:51:45 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 1/7] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 Date: Mon, 11 Sep 2017 14:52:04 +0100 Message-Id: <1505137930-13255-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- Philippe suggested this in review on the last round of patches but I forgot about it :-( --- target/arm/cpu.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26..5a1f957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -81,8 +81,11 @@ * accessed via env->registerfield[env->v7m.secure] (whether the security * extension is implemented or not). */ -#define M_REG_NS 0 -#define M_REG_S 1 +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 @@ -433,19 +436,19 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t other_ss_msp; uint32_t other_ss_psp; - uint32_t vecbase[2]; - uint32_t basepri[2]; - uint32_t control[2]; - uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr[2]; /* Configurable Fault Status */ + uint32_t vecbase[M_REG_NUM_BANKS]; + uint32_t basepri[M_REG_NUM_BANKS]; + uint32_t control[M_REG_NUM_BANKS]; + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar[2]; /* MemManage Fault Address */ + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl[2]; /* MPU_CTRL */ + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ int exception; - uint32_t primask[2]; - uint32_t faultmask[2]; + uint32_t primask[M_REG_NUM_BANKS]; + uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; @@ -546,7 +549,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr[2]; + uint32_t rnr[M_REG_NUM_BANKS]; } pmsav7; /* PMSAv8 MPU */ @@ -556,10 +559,10 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar[2]; - uint32_t *rlar[2]; - uint32_t mair0[2]; - uint32_t mair1[2]; + uint32_t *rbar[M_REG_NUM_BANKS]; + uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t mair0[M_REG_NUM_BANKS]; + uint32_t mair1[M_REG_NUM_BANKS]; } pmsav8; void *nvic; From patchwork Mon Sep 11 13:52:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112193 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825802pji; Mon, 11 Sep 2017 06:51:53 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5WDIlv2oVJKxYAqtruy8NSDIr/Es6IxMRioBARHlL9MmYiC3gYaffhp+YGktK2byHVocVu X-Received: by 10.98.157.74 with SMTP id i71mr12351689pfd.168.1505137912916; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137912; cv=none; d=google.com; s=arc-20160816; b=n84nPP1vPhDvhUar9JO8iT0UJE/ohCSkVd32XGXd9UeaNMt0Cqll7iFpgx8D2Hio0V saiU9Wb0Xbqk3nUhYg4TXMa7FbGaRpjzorhiXuBTraowFigtPL5Znd4OKRiCAzK6M1fm VbI/cDqEbap87Wug1auvhQsAFRx+Nv99rfhCBi49NlQkFdbpVp0jYNqWfA9e5C+tXkL5 xaO8A07dv1CoPGYfOr6VWhUQpPwJ0Dyf4iCjveMA5/F0CdrIz9EGQt1NW+6p3/cLqvjo COAbkfJDrBqUX4dJGfX0h0YA0qDWkza4UjqULvoJZ8LqCfvbk8vQTGGiLuzPlaw3Pl55 BMVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=OAQAEcY47GohXWNIe8wik0dL6owj/qwY92P7fleqBa4=; b=VvYghOcOj1UrdBYH5PM9tU/iRNlDszrAwsWxwTApIF7bts3mHzJhHEBWLVHCyPD6bw 0MLM3g/yP7PE+vaKIj4hdi7CoVq2PMwGloT13Bcra55uw3VivN7MtmktkVztXAa6nt/f /Y68Xb0pEmphOFtKO5jTDlEULsUdvD+bF05XWGXNVEfrPUA2aXYsd3nXCvKMhzwKVOvq Bxr3PlCgahP0B2dIx98TPbuNo0WR5tvW9O/Jai7SQW7jznyOo85s/YWXrcJRwc6hD9RC XJufiOaDPU7PP8h+VNdu1F+fWWng7NS73bi3+qPSNdikYYX9kB0h0DdjJWrgOntBQ2o5 uNlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 92si6810776plw.40.2017.09.11.06.51.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7q-0007m1-6B; Mon, 11 Sep 2017 14:51:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 2/7] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit Date: Mon, 11 Sep 2017 14:52:05 +0100 Message-Id: <1505137930-13255-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 6 ++++++ target/arm/helper.c | 2 ++ target/arm/op_helper.c | 2 +- 4 files changed, 19 insertions(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson diff --git a/target/arm/internals.h b/target/arm/internals.h index 5d7f24c..a315354 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -444,6 +444,16 @@ void arm_handle_psci_call(ARMCPU *cpu); #endif /** + * arm_clear_exclusive: clear the exclusive monitor + * @env: CPU env + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. + */ +static inline void arm_clear_exclusive(CPUARMState *env) +{ + env->exclusive_addr = -1; +} + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1acce3..412e94c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,6 +235,12 @@ static void arm_cpu_reset(CPUState *s) env->regs[15] = 0xFFFF0000; } + /* M profile requires that reset clears the exclusive monitor; + * A profile does not, but clearing it makes more sense than having it + * set with an exclusive access on address zero. + */ + arm_clear_exclusive(env); + env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 329e517..668e367 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6175,6 +6175,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) armv7m_nvic_acknowledge_irq(env->nvic); switch_v7m_sp(env, 0); + arm_clear_exclusive(env); /* Clear IT bits */ env->condexec_bits = 0; env->regs[14] = lr; @@ -6354,6 +6355,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } /* Otherwise, we have a successful exception exit. */ + arm_clear_exclusive(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d1bca46..6a60464 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1022,7 +1022,7 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_save_sp(env, cur_el); - env->exclusive_addr = -1; + arm_clear_exclusive(env); /* We must squash the PSTATE.SS bit to zero unless both of the * following hold: From patchwork Mon Sep 11 13:52:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112192 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825800pji; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4QtxF/LkZdoF2Q1nOGhzVIeC0NRtIUvNvz4ZHSrIXoepP4dwV4tRdkczRCyKoKwVPy7Wsr X-Received: by 10.98.196.73 with SMTP id y70mr11943784pff.334.1505137912749; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137912; cv=none; d=google.com; s=arc-20160816; b=0pM1OzDmZi6t0DzK9zKAMzvgO+qkak3k0QmqrRkLzI7+VI4hYWkGkyCusSejFW0wY1 y18eBeYAJCZyAKEbx+rh7Ov+6bBsqhKWsDA/wuxxD1ynu38phFOMbte6GhSo+hTXPjGc JpCBqZkh4XOU3MR2aBKmXlCWS0GllLk84Q9V5Ck55o2FEN7D7IwvsT7Wenxj3UtuHHKG Efitej879p7Wmx9U6tC1L6G8mKWD1TZ728YMx1kttaIwd+w/5J7i3PPWKsj/fng3k1T8 JO9whTjZA+fKaOwvaVBPutbnmvefHtL5sWIMkCqfeRiNCS2RGCEPbzKDyoTKq5WDaX2v dP6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=ak6eDkVOr9wRUe7yevzq9xJxkTkFAKk1+BvJtSbvFWQ=; b=kbS3PnN8c8rHau5ld+WC1vAV0tvbVXauZckfSWpx/ZxkUj0ADadUo5EBZwdmzjk2Da 7CxpFmbHNbrSnOFgPyKFegQVg9dvxvmTuoAoMbNCjfj8sj9wUSCFSXER8gCS9b5xvHAN 7d718ziUlfWUqbaXjnHC2hov/XCXt8VwdXsP3LEnkL8w+xwZQ7caILMYrTHuuVQf4REB +dKaY9MMIHKYsbNFU1ptyPi90q+CLGhLZoIIg1/VNC9psImfA9RFF4gicaETpzBbjdNQ 9d/T9Egmy9+PzBSG045WNGYB7bWozHPAR1PQgIvS3q8tKCOuzMb9e/fSWilz5vKyHFpr ROPw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id d2si5963935pge.795.2017.09.11.06.51.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7q-0007mE-Rl; Mon, 11 Sep 2017 14:51:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 3/7] target/arm: Get PRECISERR and IBUSERR the right way round Date: Mon, 11 Sep 2017 14:52:06 +0100 Message-Id: <1505137930-13255-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> For a bus fault, the M profile BFSR bit PRECISERR means a bus fault on a data access, and IBUSERR means a bus fault on an instruction access. We had these the wrong way around; fix this. Signed-off-by: Peter Maydell --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 668e367..1741e0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6430,15 +6430,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); break; case EXCP_DATA_ABORT: env->v7m.cfsr[M_REG_NS] |= - (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); env->v7m.bfar = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, - "...with CFSR.IBUSERR and BFAR 0x%x\n", + "...with CFSR.PRECISERR and BFAR 0x%x\n", env->v7m.bfar); break; } From patchwork Mon Sep 11 13:52:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112187 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825711pji; Mon, 11 Sep 2017 06:51:49 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7FysvbbDZ+otsAtWrYtDbBXSmjo3RA9QgqvaUwiuMzEGJR0Fq6aNkbut0Sy4a+iF2GItzO X-Received: by 10.223.135.102 with SMTP id 35mr8552215wrz.160.1505137909500; Mon, 11 Sep 2017 06:51:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137909; cv=none; d=google.com; s=arc-20160816; b=iy4YgApt0Rqq1DrwWGqymgom3BFe2KR77QSguxVWFM4m+Evt2wnC+WQtXPiUBNy7dI QBpTXWNH20HtrhtGl+nqnCNzYRDiaaBXuCucrxq3tIY162e3tBoQJxgxUP5xH7mToaFd jh1m28miqjhxByTLIP1Rma//GmT8YgVze+fsP9YKcaIST1LzYLewPadP2/WiFCRiMZ2z Eh3pu7EeCYrVhWeSHdFo+mQdeiJhYOW4JlXSPiWKUPpF+rG6+CSCrPvI8FKlH+CKQgga f8U7Xj0AHQve6dkATZtwdGi17GdIqsSH8gn0UA+U106YLjbdv9Eg56l4im3PS5E7Sa/2 +GUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=TEbPFvKwynEH4nFWQ+8A95zks8NameeaaLUNU2P4XeA=; b=MKwjnS96z+CqcW9czG+bd23WG60Qb+4Uqj7n11o3bkfu09AvfcEBnEI7cdmeO+wgYL RJWJZ3AXOyOtXQJEK8D8UzXH4sKW1Jx3Um2DqI7Bz1Id8WkBwkfk/P4WZoJ+zx21GRWN AZozqE9fkx3kAfuoSbXEJ9GfKN1Ad5SbXgeKAEbnRE89jQ42FeSup2abc4jQL9HlePbf q12J9dHiFZB2iMNwKGG5xn/sPN65cxZcQiUzwc5IKXG8WOAtsBUfhb8s8K3GpgE/djJ3 nsXeepMTS80voVcg5BBB0OPCiNFz2wtkCIsC/stTeioChfCcyHFekLwy9d+Flxh3K1LP N72Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s10si1681507wra.196.2017.09.11.06.51.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7r-0007mR-ID; Mon, 11 Sep 2017 14:51:47 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 4/7] nvic: Don't apply group priority mask to negative priorities Date: Mon, 11 Sep 2017 14:52:07 +0100 Message-Id: <1505137930-13255-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> In several places we were unconditionally applying the nvic_gprio_mask() to a priority value. This is incorrect if the priority is one of the fixed negative priority values (for NMI and HardFault), so don't do it. This bug would have caused both NMI and HardFault to be considered as the same priority and so NMI wouldn't correctly preempt HardFault. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1fecfd6..d3e2056 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -152,8 +152,12 @@ static void nvic_recompute_state(NVICState *s) } } + if (active_prio > 0) { + active_prio &= nvic_gprio_mask(s); + } + s->vectpending = pend_irq; - s->exception_prio = active_prio & nvic_gprio_mask(s); + s->exception_prio = active_prio; trace_nvic_recompute_state(s->vectpending, s->exception_prio); } @@ -329,7 +333,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque) assert(vec->enabled); assert(vec->pending); - pendgroupprio = vec->prio & nvic_gprio_mask(s); + pendgroupprio = vec->prio; + if (pendgroupprio > 0) { + pendgroupprio &= nvic_gprio_mask(s); + } assert(pendgroupprio < running); trace_nvic_acknowledge_irq(pending, vec->prio); From patchwork Mon Sep 11 13:52:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112189 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825732pji; Mon, 11 Sep 2017 06:51:50 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBA1Xhx9w2IR+AgQ3L8TlctTXAA0KZv+dHk5y0dyW386m4HAq58PiWs0fnRHBquL+AvN0CK X-Received: by 10.25.199.207 with SMTP id x198mr4049601lff.182.1505137910073; Mon, 11 Sep 2017 06:51:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137910; cv=none; d=google.com; s=arc-20160816; b=KXz8DMtcwmDRga/VF54TuOfEU4VuMUqHXnHavzBNNK/kh+8LAU4G/eC+JUW1PbOQDn sA2/Z7zQoAgoYW3fYh0HtCUYyOOgvwPZEcngS1m29Qa/FqvbupVIvWElpU24Y3E9cbfX nyCFc1wUTFW7v3FKU+iliqB+KmSyAGqzaXH3vHAauRvao0UufehnZW2HsCw0J/EU1K1h zk8muEci0SBA7jiFBThKUIoU+SEj3tjrheGHeFtVa7Szfv/lYiVPIQ76L/KOWvko+N3r P+D5VM+rxuVCs1IkMyInK6BYAtMCa/aaTMhk4x1dfvlQnDFXCI/eFBnK2LYOzQRAkSl3 O7Yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=JWlZA0idTGOrOFxfvK6PWXZIQM8oXWoz2jdBs7Gmu4U=; b=n95Qh+ZAB5iaiznVIpke3FDSTEUuv1GnckyCV7SILj4zvV1ukVgYyB9VeFtUuFr3IZ Maz1uHk4xr7agn2FMnaneajHvIxf4mu4UVEsBxxJi9PzNBZ3SEp8usCvw0Xond6MynCe HVqKb53YHnDKcYrQr07OzHuisP0EGKgK5cFzOkgm/RPmCHoPcoLjTHz83K9H+hj9+WWB e1uZ3LsPUFgz/xxeYq8LL0T3VKXt0IF5Z5XavNivQv1IF3kIOq1dr0VWbBR4S954RRla kllPfqRDdXxZX/gKZYp61g2zeR4OkRZu3n6pE170M4eGinxh+f0ACOtxvWhucRkBaFoL QwnQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id h13si1550870ljf.218.2017.09.11.06.51.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7s-0007me-8q; Mon, 11 Sep 2017 14:51:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 5/7] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() Date: Mon, 11 Sep 2017 14:52:08 +0100 Message-Id: <1505137930-13255-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> In do_v7m_exception_exit(), there's no need to force the high 4 bits of 'type' to 1 when calling v7m_exception_taken(), because we know that they're always 1 or we could not have got to this "handle return to magic exception return address" code. Remove the unnecessary ORs. Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 Acked-by: Alistair Francis Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 1741e0d..fdd5cc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6306,7 +6306,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check\n"); return; @@ -6348,7 +6348,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " "failed exception return integrity check\n"); return; From patchwork Mon Sep 11 13:52:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112194 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825804pji; Mon, 11 Sep 2017 06:51:53 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4rQxFuEpw/SoBiG3tT30XazHOwDXxwYbxu0B/UXnKqvHOKYcAnIXHHkh7pHeaJ4aaBSodD X-Received: by 10.98.100.206 with SMTP id y197mr12150320pfb.53.1505137912954; Mon, 11 Sep 2017 06:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137912; cv=none; d=google.com; s=arc-20160816; b=JOMCUjMJy1bNKMR2Q5pcyKElI4V4wMOKi1iVmhY0nK05bAkDbzRWTovhJFd5nItxkd euAZN4D0dabbw6cw/UPXHily5zI1AVrrmHND65orbM63FPWmdu8p7NGCw+EQdTuRlehP SBjDU5V/4XIv7WjEcrtwL6QbqWc9uQZMycfX/TUXGk1p+tjJYxGMJq7AUddLp9rNZ8p7 sRCnj89s6nxeOQTBtSaZctqRFXS1uWiOcWgxLtDc2MUZbi810LyDLNflmY6oWoOwZyB4 yDzyz65wthOmFuP/ZOchRBoFNyriQVz6/bt+xEF3C6wMK5rrhtU2Q1mDAQt2lxguUGnz SL8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=BWsjrYSavSxCnT1vxbk0oAog74deWZZ/WZ4O5Nys86A=; b=O62yQA5wByb3U1TQq+4WwIFtyxQKug6UQ75nxHZtP/n+uTltVmjjSJMOtazEQfbzO3 DYClHd9GPane+bZMbA0loTpePIwSRKcdl1PDa/SlCaR3XFY25++XEoSPFhvK7GoD6PAy GfL3T/c2y7hEn/OMnad0tFQnhnpnuZ6my8saNSoofsVsD7z0qFIlGgrb3Oik1gyBVQgh iNNGqa25h/H12Sg6rU+JvHaA0KvyaZtXyaTfxFPQ58dO9ePJuZoF9IWnR2fkb4SIdAyX zXjvFtmVbW2Zdhcv1CrBXmAwt91guVyzVBeV/8kDykfHNSbH2E0NF5tlX2ifibtL77Uo vypQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id j188si3244968pfb.412.2017.09.11.06.51.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7s-0007mr-VD; Mon, 11 Sep 2017 14:51:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 6/7] target/arm: Add and use defines for EXCRET constants Date: Mon, 11 Sep 2017 14:52:09 +0100 Message-Id: <1505137930-13255-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell --- target/arm/internals.h | 10 ++++++++++ target/arm/helper.c | 14 +++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis diff --git a/target/arm/internals.h b/target/arm/internals.h index a315354..18be370 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) +/* Bit definitions for v7M exception return payload */ +FIELD(V7M_EXCRET, ES, 0, 1) +FIELD(V7M_EXCRET, RES0, 1, 1) +FIELD(V7M_EXCRET, SPSEL, 2, 1) +FIELD(V7M_EXCRET, MODE, 3, 1) +FIELD(V7M_EXCRET, FTYPE, 4, 1) +FIELD(V7M_EXCRET, DCRS, 5, 1) +FIELD(V7M_EXCRET, S, 6, 1) +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/helper.c b/target/arm/helper.c index fdd5cc6..a502e4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6242,7 +6242,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) " previous exception %d\n", type, env->v7m.exception); - if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { + if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); } @@ -6255,7 +6255,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es = type & 1; + int es = type & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { env->v7m.faultmask[es] = 0; } @@ -6491,12 +6491,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } - lr = 0xfffffff1; + lr = R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_S_MASK | + R_V7M_EXCRET_DCRS_MASK | + R_V7M_EXCRET_FTYPE_MASK | + R_V7M_EXCRET_ES_MASK; if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { - lr |= 4; + lr |= R_V7M_EXCRET_SPSEL_MASK; } if (!arm_v7m_is_handler_mode(env)) { - lr |= 8; + lr |= R_V7M_EXCRET_MODE_MASK; } v7m_push_stack(cpu); From patchwork Mon Sep 11 13:52:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112190 Delivered-To: patches@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5825739pji; Mon, 11 Sep 2017 06:51:50 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4yX60h8hksQPuMs8GdKASZK4GG95WwpjONerm2KC3rugdo0rsIC/6s0cIunQYNWIpAor6U X-Received: by 10.28.72.131 with SMTP id v125mr6265915wma.134.1505137910319; Mon, 11 Sep 2017 06:51:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505137910; cv=none; d=google.com; s=arc-20160816; b=y/tHmzAR8qkBaHRc6AIcwGnVCzUZQe9tfc3iC//lm51usAQClDNqMG/EP6vJ6RHcEz Z0SmaTc96gNBV8arVVkKUdImf7QuEfEEmOHcURWODzLdr5DzHHAETsdBPyDFn+N8o93P 30uTv2CayfMjeOyOo29lFy8ZkmrZXdFD9bAtjYvDxoNQI1qZQs9jZeld5i3E3BvkWMfU Rv82zKLpKo2MWFuY4+6zBby/2wDorymfjvo+fXaM/at1rC/0tIrqMMlwsMZcIP9nF4IE qVKCKZ1asYJdcCOR/hsBl5kDqneIRYECJ4M1Oj0AoFsWFL18ih/lMF1WXNpTzh5ZP4UY mLmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=6k5j7bPh2UtJioHBiuqMq6WxLOlMKo58G366QlD0APk=; b=WQQjZaoGtlhqlTrch372wvOm7e2kGuw7g6a/Z4i13gTq/t5uTpXYUmoPX6XatyG6Zr TShlZEdceRPP8P+n28kQZQ/S11wtr9Rk9/Yulr8fYnG4wEi2z0d5REbLPGcH3HfwmVe0 SFgyxGwDXZB4aYGFEmgM5rXRYjlexoYtQ0/BIpNnmP6/IYUu2LTPrl+XLiA0lNlFLMJm FOhoy97uaBtCMGXP3IoUvjFJ6aTeN0pw6TCema3ej5Lfa2yTVP2OZuE7zBucnObup4Aw ExiVAo8ApFU1ECdHyaHpJouYHYWExtmngtmbBylim5/MuRO6p+HRnrTebrnW49UHCrZX u/Qg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l14si6900577wrl.332.2017.09.11.06.51.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 06:51:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7t-0007nI-Lz; Mon, 11 Sep 2017 14:51:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 7/7] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() Date: Mon, 11 Sep 2017 14:52:10 +0100 Message-Id: <1505137930-13255-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> In the v7M and v8M ARM ARM, the magic exception return values are referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_* constants to define bits within them. Rename the 'type' variable which holds the exception return value in do_v7m_exception_exit() to excret, making it clearer that it does hold an EXC_RETURN value. Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index a502e4e..4f41841 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6212,7 +6212,7 @@ static void v7m_push_stack(ARMCPU *cpu) static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env = &cpu->env; - uint32_t type; + uint32_t excret; uint32_t xpsr; bool ufault = false; bool return_to_sp_process = false; @@ -6233,18 +6233,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * the target value up between env->regs[15] and env->thumb in * gen_bx(). Reconstitute it. */ - type = env->regs[15]; + excret = env->regs[15]; if (env->thumb) { - type |= 1; + excret |= 1; } qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 " previous exception %d\n", - type, env->v7m.exception); + excret, env->v7m.exception); - if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { + if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " - "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); + "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", + excret); } if (env->v7m.exception != ARMV7M_EXCP_NMI) { @@ -6255,7 +6256,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es = type & R_V7M_EXCRET_ES_MASK; + int es = excret & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { env->v7m.faultmask[es] = 0; } @@ -6283,7 +6284,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) g_assert_not_reached(); } - switch (type & 0xf) { + switch (excret & 0xf) { case 1: /* Return to Handler */ return_to_handler = true; break; @@ -6306,7 +6307,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check\n"); return; @@ -6341,14 +6342,14 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the - * exception return type specified then this is a UsageFault. + * exception return excret specified then this is a UsageFault. */ if (return_to_handler != arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " "failed exception return integrity check\n"); return;