From patchwork Mon Sep 11 15:23:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Lloyd X-Patchwork-Id: 112201 Delivered-To: patch@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5947533pji; Mon, 11 Sep 2017 08:23:47 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7NIsXdKn4NSNv+mG9jFI1YY6jRBk1qq0rXyD36ui32KfEnweqf5kSNJ7Ed8Blyej5wz30Q X-Received: by 10.98.29.199 with SMTP id d190mr4233065pfd.74.1505143427254; Mon, 11 Sep 2017 08:23:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505143427; cv=none; d=google.com; s=arc-20160816; b=mOZKxUvwQL4i4t8KZOuHgwO19H9Ypxe4tL7cOPzrbpg+uFFeuzqOnMhcldUedQqLNG Viv60l4qr8gi7p0F4mQquxWtb6ALZf1CNazJwq+xJKwmkdh6rA6xKkj2JecEB6UMkA1y BEOLbSmdPrzYVF/SEHPSmROViKpIwUF+RgpKu59GHLwVaZGeKWfWJSmVS5XkMwOPvJEs vJMblUibolIgtT4QPund37ol2TXUf7wenU3fxsVWLVDxNGfX06UHeih+/ykGr0YRFNir L5gE7MulspsJgX6wgKxs4o4B0+oWHRayp7ihmpElzk72lfJtTmxUKREZcBCO7MZMD2HU Fa1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=AcVAR8v3+8nc9EOP08DeWZ+SkQuvH6vxugmo6FR39C0=; b=XBwVSxYyVta0e8b4Rumni/DXxVDd7ffNzSfC2S8/hKRoJM3i3nUM671UYHc6wZyQqT 6wAjlagKhFLluNqA7p4qCvW9a5L/vFy4uL0/HhAreXh40okgZwkvvpteGddTXWnShckL 7AJltfGuu7Zspe0e1INPNwRBDpNoYWp28MNuPbeAMXS8AYMM6udz0lJaDl3bH+0JOye1 F+kqBI+zLMMq6MiYiCWxjDlkFszCVhgbIDpMFuhcydukeJTwRMZHJ+0ycCqsztLdvbSv xIpUG/jPqjKG5hpJ80qIykjuqZYtrJ35gcNmxnImvffyy1GxeF1Q3R84/yhYU26icoYu OJWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id f1si6990806plb.122.2017.09.11.08.23.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Sep 2017 08:23:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E5AB621CEB0F7; Mon, 11 Sep 2017 08:20:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5BCDC21CEB0E4 for ; Mon, 11 Sep 2017 08:20:47 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.26.71]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8BFNeaI010774; Mon, 11 Sep 2017 16:23:41 +0100 From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Mon, 11 Sep 2017 16:23:32 +0100 Message-Id: <20170911152335.72672-3-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170911152335.72672-1-evan.lloyd@arm.com> References: <20170911152335.72672-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 2/5] EmbeddedPkg: Introduce HardwareInterrupt2 protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel The existing HardwareInterrupt protocol lacks the means to configure the level/edge and polarity properties of an interrupt. So introduce a new protocol HardwareInterrupt2, and add some new members that allow manipulation of those properties. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- EmbeddedPkg/EmbeddedPkg.dec | 1 + EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h | 182 ++++++++++++++++++++ 2 files changed, 183 insertions(+) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm Reviewed-by: Leif Lindholm diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index 0be102ad9c767d81a004c757f40a65063aab1d7a..151b1d503dee463d529a173d2555b6c9208100e5 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -69,6 +69,7 @@ [Guids.common] [Protocols.common] gHardwareInterruptProtocolGuid = { 0x2890B3EA, 0x053D, 0x1643, { 0xAD, 0x0C, 0xD6, 0x48, 0x08, 0xDA, 0x3F, 0xF1 } } + gHardwareInterrupt2ProtocolGuid = { 0x32898322, 0x2da1, 0x474a, { 0xba, 0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94, 0x70 } } gEfiDebugSupportPeriodicCallbackProtocolGuid = { 0x9546e07c, 0x2cbb, 0x4c88, { 0x98, 0x6c, 0xcd, 0x34, 0x10, 0x86, 0xf0, 0x44 } } gEfiEblAddCommandProtocolGuid = { 0xaeda2428, 0x9a22, 0x4637, { 0x9b, 0x21, 0x54, 0x5e, 0x28, 0xfb, 0xb8, 0x29 } } gEmbeddedDeviceGuid = { 0xbf4b9d10, 0x13ec, 0x43dd, { 0x88, 0x80, 0xe9, 0xb, 0x71, 0x8f, 0x27, 0xde } } diff --git a/EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h b/EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h new file mode 100644 index 0000000000000000000000000000000000000000..505052bd81afe7432e3122a2722ceab348777c29 --- /dev/null +++ b/EmbeddedPkg/Include/Protocol/HardwareInterrupt2.h @@ -0,0 +1,182 @@ +/** @file + + Copyright (c) 2016-2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __HARDWARE_INTERRUPT2_H__ +#define __HARDWARE_INTERRUPT2_H__ + +#include + +// 22838932-1a2d-4a47-aaba-f3f7cf569470 + +#define EFI_HARDWARE_INTERRUPT2_PROTOCOL_GUID \ + { 0x32898322, 0x2d1a, 0x474a, \ + { 0xba, 0xaa, 0xf3, 0xf7, 0xcf, 0x56, 0x94, 0x70 } } + +typedef enum { + EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_LOW, + EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH, + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_FALLING, + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING, +} EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE; + +typedef struct _EFI_HARDWARE_INTERRUPT2_PROTOCOL \ + EFI_HARDWARE_INTERRUPT2_PROTOCOL; + +/** + Register Handler for the specified interrupt source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param Handler Callback for interrupt. NULL to unregister + + @retval EFI_SUCCESS Source was updated to support Handler. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_REGISTER) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN HARDWARE_INTERRUPT_HANDLER Handler + ); + + +/** + Enable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt enabled. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_ENABLE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ); + + +/** + Disable interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt disabled. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_DISABLE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ); + + +/** + Return current state of interrupt source Source. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param InterruptState TRUE: source enabled, FALSE: source disabled. + + @retval EFI_SUCCESS InterruptState is valid + @retval EFI_DEVICE_ERROR InterruptState is not valid + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_INTERRUPT_STATE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN BOOLEAN *InterruptState + ); + +/** + Signal to the hardware that the End Of Intrrupt state + has been reached. + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + + @retval EFI_SUCCESS Source interrupt EOI'ed. + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_END_OF_INTERRUPT) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source + ); + +/** + Return the configured trigger type for an interrupt source + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param TriggerType The configured trigger type + + @retval EFI_SUCCESS Operation successful + @retval EFI_DEVICE_ERROR Information could not be returned + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_GET_TRIGGER_TYPE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType + ); + + +/** + Configure the trigger type for an interrupt source + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt + @param TriggerType The trigger type to configure + + @retval EFI_SUCCESS Operation successful + @retval EFI_DEVICE_ERROR Hardware could not be programmed. + +**/ +typedef +EFI_STATUS +(EFIAPI *HARDWARE_INTERRUPT2_SET_TRIGGER_TYPE) ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType + ); + +struct _EFI_HARDWARE_INTERRUPT2_PROTOCOL { + HARDWARE_INTERRUPT2_REGISTER RegisterInterruptSource; + HARDWARE_INTERRUPT2_ENABLE EnableInterruptSource; + HARDWARE_INTERRUPT2_DISABLE DisableInterruptSource; + HARDWARE_INTERRUPT2_INTERRUPT_STATE GetInterruptSourceState; + HARDWARE_INTERRUPT2_END_OF_INTERRUPT EndOfInterrupt; + + // v2 members + HARDWARE_INTERRUPT2_GET_TRIGGER_TYPE GetTriggerType; + HARDWARE_INTERRUPT2_SET_TRIGGER_TYPE SetTriggerType; +}; + +extern EFI_GUID gHardwareInterrupt2ProtocolGuid; + +#endif From patchwork Mon Sep 11 15:23:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Lloyd X-Patchwork-Id: 112203 Delivered-To: patch@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5947738pji; Mon, 11 Sep 2017 08:23:56 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4HxnRMKnTcbENMoIYKPjnm+3PKEN3qe9g5l2jnl9J5luklgLItgWcjkGhPn0iNLAJ5N6DL X-Received: by 10.84.157.74 with SMTP id u10mr9472526plu.402.1505143436049; Mon, 11 Sep 2017 08:23:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505143436; cv=none; d=google.com; s=arc-20160816; b=CIhS/ENHZPFrbXINRlKoQO8el5Q6pSohwZXwLqnxtJ5sA+0iGHsvPwks0YnuAlxVw7 AOWp3DCOS+DS9o6xXCH/SKjag6ukzov0iIlhcRs4QrL+2A1sQ/LJogccfbyKfELZtm2s fW0vqjkLrtCwKqyeF6BD5dHMKKebE0Jqf7P97v6HRxxo1Sl2T1ZtGIWQJPjcZ5lPYmU4 inB8RJAbWXSJjiVEnbvPzvuCBATB/toveScxymgTO5kaYtkFzhQvo4zn3km73ol600M4 yD9W3eCgOQ/ocpqG7pO/mfdSHRe0Pxe2/DW5bd3EnP4oD2y4KFkQqTxUoyolQSaVvPX9 pHUw== ARC-Message-Signature: i=1; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id r27si6371877pfd.323.2017.09.11.08.23.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Sep 2017 08:23:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AED0421CEB102; Mon, 11 Sep 2017 08:20:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E92BF21CEB0F8 for ; Mon, 11 Sep 2017 08:20:50 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.26.71]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8BFNeaJ010774; Mon, 11 Sep 2017 16:23:41 +0100 From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Mon, 11 Sep 2017 16:23:33 +0100 Message-Id: <20170911152335.72672-4-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170911152335.72672-1-evan.lloyd@arm.com> References: <20170911152335.72672-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 3/5] ArmPkg/ArmGicDxe: Expose HardwareInterrupt2 protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel The existing HardwareInterrupt protocol lacked a means to configure the level/edge properties of an interrupt. The new HardwareInterrupt2 protocol introduced this capability. This patch updates the GIC drivers to provide the new interfaces. The changes comprise: Update to use HardwareInterrupt2 protocol Additions to register info in ArmGicLib.h Added new functionality (GetTriggerType and SetTriggerType) The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic (ARM) relevance. This commit is in response to review on the mailing list and, as suggested there, rolls Girish's updates onto Ard's original example. NOTE: At this point the GICv3 code is not tested. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf | 3 +- ArmPkg/Drivers/ArmGic/ArmGicDxe.h | 25 +++- ArmPkg/Include/Library/ArmGicLib.h | 12 +- ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c | 44 ++++++- ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 139 +++++++++++++++++++- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 138 ++++++++++++++++++- 6 files changed, 354 insertions(+), 7 deletions(-) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf index e554301c4b28022c805f69242cf6ee979d19abc2..d5921533fb68fa32c3e0705b05930700ee81da07 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.inf @@ -1,7 +1,7 @@ #/** @file # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.
+# Copyright (c) 2012 - 2017, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -48,6 +48,7 @@ [LibraryClasses] [Protocols] gHardwareInterruptProtocolGuid + gHardwareInterrupt2ProtocolGuid gEfiCpuArchProtocolGuid [Pcd.common] diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h index 1018f2004e75d879a72c2d6bf37b64051e720d12..cefa4c2d4e4a05c54e51642db0f471e9a338afb6 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -1,6 +1,6 @@ /*++ -Copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+Copyright (c) 2013-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -24,6 +24,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include #include +#include extern UINTN mGicNumInterrupts; extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers; @@ -34,6 +35,7 @@ extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers; EFI_STATUS InstallAndRegisterInterruptService ( IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_EVENT_NOTIFY ExitBootServicesEvent ); @@ -64,4 +66,25 @@ GicV3DxeInitialize ( IN EFI_SYSTEM_TABLE *SystemTable ); + +// Shared code + +/** + Calculate GICD_ICFGRn base address and corresponding bit + field Int_config[1] of the GIC distributor register. + + @param Source Hardware source of the interrupt. + @param RegAddress Corresponding GICD_ICFGRn base address. + @param Config1Bit Bit number of F Int_config[1] bit in the register. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +EFI_STATUS +GicGetDistributorIcfgBaseAndBit ( + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT UINTN *RegAddress, + OUT UINTN *Config1Bit + ); + #endif diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index f7b546895d116f81c65a853fcdb067ec7601b2da..1c8d8cf6a7c39e2b5e2e36feb3e5433f29f488e2 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -51,10 +51,18 @@ #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) +// GICD_ICDICFR bits +#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register +#define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8) +#define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits +#define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register +#define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field +#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt +#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt + // GIC Redistributor - #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB diff --git a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c index 88cb455b75bb8e8cb22157643a392403ce93129d..13a7fae07b856025ab1c0eac97d07ec4c4df20a9 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -1,6 +1,6 @@ /*++ -Copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+Copyright (c) 2013-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -43,6 +43,46 @@ UINTN mGicNumInterrupts = 0; HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL; + +/** + Calculate GICD_ICFGRn base address and corresponding bit + field Int_config[1] of the GIC distributor register. + + @param Source Hardware source of the interrupt. + @param RegAddress Corresponding GICD_ICFGRn base address. + @param Config1Bit Bit number of F Int_config[1] bit in the register. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +EFI_STATUS +GicGetDistributorIcfgBaseAndBit ( + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT UINTN *RegAddress, + OUT UINTN *Config1Bit + ) +{ + UINTN RegIndex; + UINTN Field; + + if (Source >= mGicNumInterrupts) { + ASSERT(Source < mGicNumInterrupts); + return EFI_UNSUPPORTED; + } + + RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant + Field = Source % ARM_GIC_ICDICFR_F_STRIDE; + *RegAddress = PcdGet64 (PcdGicDistributorBase) + + ARM_GIC_ICDICFR + + (ARM_GIC_ICDICFR_BYTES * RegIndex); + *Config1Bit = ((Field * ARM_GIC_ICDICFR_F_WIDTH) + + ARM_GIC_ICDICFR_F_CONFIG1_BIT); + + return EFI_SUCCESS; +} + + + /** Register Handler for the specified interrupt source. @@ -88,6 +128,7 @@ RegisterInterruptSource ( EFI_STATUS InstallAndRegisterInterruptService ( IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol, + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_EVENT_NOTIFY ExitBootServicesEvent ) @@ -105,6 +146,7 @@ InstallAndRegisterInterruptService ( Status = gBS->InstallMultipleProtocolInterfaces ( &gHardwareInterruptHandle, &gHardwareInterruptProtocolGuid, InterruptProtocol, + &gHardwareInterrupt2ProtocolGuid, Interrupt2Protocol, NULL ); if (EFI_ERROR (Status)) { diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c index 50ec90207b515d849cbf64f0a4b0d639b3868e60..41db2277132d47dda1a047b73eaf63323b5b9aaf 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -29,6 +29,7 @@ Abstract: #define ARM_GIC_DEFAULT_PRIORITY 0x80 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; +extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol; STATIC UINT32 mGicInterruptInterfaceBase; STATIC UINT32 mGicDistributorBase; @@ -184,7 +185,7 @@ GicV2IrqInterruptHandler ( // Call the registered interrupt handler. InterruptHandler (GicInterrupt, SystemContext); } else { - DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); + DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); } } @@ -200,6 +201,141 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = { GicV2EndOfInterrupt }; +/** + Get interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Returns interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +STATIC +EFI_STATUS +EFIAPI +GicV2GetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType + ) +{ + UINTN RegAddress; + UINTN Config1Bit; + EFI_STATUS Status; + + Status = GicGetDistributorIcfgBaseAndBit ( + Source, + &RegAddress, + &Config1Bit + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + if (MmioBitFieldRead32 (RegAddress, Config1Bit, Config1Bit) == 0) { + *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH; + } else { + *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; + } + + return EFI_SUCCESS; +} + +/** + Set interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +STATIC +EFI_STATUS +EFIAPI +GicV2SetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType + ) +{ + UINTN RegAddress; + UINTN Config1Bit; + UINT32 Value; + EFI_STATUS Status; + BOOLEAN SourceEnabled; + + if (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING + && TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH) { + DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \ + TriggerType)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status = GicGetDistributorIcfgBaseAndBit ( + Source, + &RegAddress, + &Config1Bit + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = GicV2GetInterruptSourceState ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source, + &SourceEnabled + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING) + ? ARM_GIC_ICDICFR_EDGE_TRIGGERED + : ARM_GIC_ICDICFR_LEVEL_TRIGGERED; + + // Before changing the value, we must disable the interrupt, + // otherwise GIC behavior is UNPREDICTABLE. + if (SourceEnabled) { + GicV2DisableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + + MmioAndThenOr32 ( + RegAddress, + ~(0x1 << Config1Bit), + Value << Config1Bit + ); + + // Restore interrupt state + if (SourceEnabled) { + GicV2EnableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + + return EFI_SUCCESS; +} + +EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = { + (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, + (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource, + (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource, + (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceState, + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt, + GicV2GetTriggerType, + GicV2SetTriggerType +}; + /** Shutdown our hardware @@ -324,6 +460,7 @@ GicV2DxeInitialize ( Status = InstallAndRegisterInterruptService ( &gHardwareInterruptV2Protocol, + &gHardwareInterrupt2V2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent ); diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 69b2d8d794e151e25f06cbea079e2796d9793a43..0c1d5b53119e8cad7ae67c57e9efaa51c1386be6 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -19,6 +19,7 @@ #define ARM_GIC_DEFAULT_PRIORITY 0x80 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol; +extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol; STATIC UINTN mGicDistributorBase; STATIC UINTN mGicRedistributorsBase; @@ -177,7 +178,7 @@ GicV3IrqInterruptHandler ( // Call the registered interrupt handler. InterruptHandler (GicInterrupt, SystemContext); } else { - DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); + DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt); } } @@ -193,6 +194,140 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = { GicV3EndOfInterrupt }; +/** + Get interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Returns interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +STATIC +EFI_STATUS +EFIAPI +GicV3GetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType + ) +{ + UINTN RegAddress; + UINTN Config1Bit; + EFI_STATUS Status; + + Status = GicGetDistributorIcfgBaseAndBit ( + Source, + &RegAddress, + &Config1Bit + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + if (MmioBitFieldRead32 (RegAddress, Config1Bit, Config1Bit) == 0) { + *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH; + } else { + *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; + } + + return EFI_SUCCESS; +} + +/** + Set interrupt trigger type of an interrupt + + @param This Instance pointer for this protocol + @param Source Hardware source of the interrupt. + @param TriggerType Interrupt trigger type. + + @retval EFI_SUCCESS Source interrupt supported. + @retval EFI_UNSUPPORTED Source interrupt is not supported. +**/ +STATIC +EFI_STATUS +EFIAPI +GicV3SetTriggerType ( + IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType + ) +{ + UINTN RegAddress; + UINTN Config1Bit; + UINT32 Value; + EFI_STATUS Status; + BOOLEAN SourceEnabled; + + if (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING + && TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH) { + DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \ + TriggerType)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status = GicGetDistributorIcfgBaseAndBit ( + Source, + &RegAddress, + &Config1Bit + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = GicV3GetInterruptSourceState ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source, + &SourceEnabled + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Value = (TriggerType == EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING) + ? ARM_GIC_ICDICFR_EDGE_TRIGGERED + : ARM_GIC_ICDICFR_LEVEL_TRIGGERED; + + // Before changing the value, we must disable the interrupt, + // otherwise GIC behavior is UNPREDICTABLE. + if (SourceEnabled) { + GicV3DisableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + + MmioAndThenOr32 ( + RegAddress, + ~(0x1 << Config1Bit), + Value << Config1Bit + ); + // Restore interrupt state + if (SourceEnabled) { + GicV3EnableInterruptSource ( + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, + Source + ); + } + + return EFI_SUCCESS; +} + +EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = { + (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, + (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource, + (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource, + (HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceState, + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt, + GicV3GetTriggerType, + GicV3SetTriggerType +}; + /** Shutdown our hardware @@ -354,6 +489,7 @@ GicV3DxeInitialize ( Status = InstallAndRegisterInterruptService ( &gHardwareInterruptV3Protocol, + &gHardwareInterrupt2V3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent ); From patchwork Mon Sep 11 15:23:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Lloyd X-Patchwork-Id: 112202 Delivered-To: patch@linaro.org Received: by 10.100.153.131 with SMTP id 3csp5947665pji; Mon, 11 Sep 2017 08:23:52 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6Mh+rxbxHxwUlkhic28wukil01Iw1fDfIzPgKinNSc0UXHLN2WwLVjWtRzR6KNdF5FqChj X-Received: by 10.84.217.221 with SMTP id d29mr13884869plj.309.1505143432662; Mon, 11 Sep 2017 08:23:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505143432; cv=none; d=google.com; s=arc-20160816; b=e41gMM82ba6w/hs5woEMY+YGMt/UBZ5eCVRBNFKIjX6guthZw8sqfI1rNlhr6DZGzv 2Fnfq4PrnGgvFlN+0suVNbJTj07HKwJAj8qgnvyW5Kz0fM73WXTxeRc/r6KO9pYF5Kqy +QbFkmXYiDJIk1k+KJVyVQJqDuh8TFOBKN2TV49wO0kgqlQFfSKuQkrNLYYRC6PtivBK e09yv0mgiETDptU641te/hwkgx90GIafjrrZk38XrxdopY+Qub3JLrRWI2xxcxQ0NRWI Z1NIt4/QQFhvsLr3STjJKMLBJPY7q2YSSLKhMYD6irO0oMyBiV5Wp+oO8F1Is31oKWYq 4PKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:delivered-to:arc-authentication-results; bh=u6CeYk0JSAyw5Q9QFDjuxHumnhyHaAzpjwBFjTM8PwI=; b=BkPpqcHJy2YiQg5P9B9JMKyaP5Hpdpms1id0uFldUbgf48tJ7woRU57fLSq0ZR1rqV sb0BZi9YXtZ/xpBJVdH3NaMD2jVXa6UtTjSQ9C2DksNL6NknuCmCuts1tukyVMcXa77y QgskMOz1IGremM60dKbaIUkaybvaYoRvmcwofOuSTQDp9lwO7b1fhmqhBIUcajE6zMo7 gijcrnVZmZeB+5wiNUbjpf8al28ZLqrVjfG/XfN6Cay4BkO0iHwbTL+8QZEtxC8slOU/ pDxBugu31jXnEUtukAq2CThXy6g9cF5kfO4LDiFLq3LIIshMHYkQssO8ICthRCiq6NaQ +YfQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id y72si7117210plh.184.2017.09.11.08.23.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Sep 2017 08:23:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 718C321CEB0FE; Mon, 11 Sep 2017 08:20:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6621921CEB0E4 for ; Mon, 11 Sep 2017 08:20:48 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.26.71]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8BFNeaK010774; Mon, 11 Sep 2017 16:23:41 +0100 From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Mon, 11 Sep 2017 16:23:34 +0100 Message-Id: <20170911152335.72672-5-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170911152335.72672-1-evan.lloyd@arm.com> References: <20170911152335.72672-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 4/5] ArmPkg/GenericWatchdogDxe: Set Watchdog interrupt type X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com, Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ard Biesheuvel Utilise the new HardwareInterrupt2 protocol to adjust the Edge/Level characteristics of the Watchdog interrupt. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Tested-by: Girish Pathak --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf | 6 ++--- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 28 ++++++++++++-------- 2 files changed, 20 insertions(+), 14 deletions(-) -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf index fece14cc18315cd15510680c438288687b60c018..ba0403d7fdc3589803c643c27a44918e73afa97e 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# Copyright (c) 2013-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -47,7 +47,7 @@ [Pcd.common] [Protocols] gEfiWatchdogTimerArchProtocolGuid - gHardwareInterruptProtocolGuid + gHardwareInterrupt2ProtocolGuid [Depex] - gHardwareInterruptProtocolGuid + gHardwareInterrupt2ProtocolGuid diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index 6d102e25047253048ac555d6fb5de7223d78f381..69844db2e11f51907e6c8bff5c67d27ceb498150 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* Copyright (c) 2013-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD @@ -24,8 +24,8 @@ #include #include +#include #include -#include #include "GenericWatchdog.h" @@ -41,7 +41,7 @@ UINTN mTimerFrequencyHz = 0; // It is therefore stored here. 0 means the timer is not running. UINT64 mNumTimerTicks = 0; -EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol; +EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; EFI_STATUS WatchdogWriteOffsetRegister ( @@ -320,7 +320,7 @@ GenericWatchdogEntry ( if (!EFI_ERROR (Status)) { // Install interrupt handler Status = gBS->LocateProtocol ( - &gHardwareInterruptProtocolGuid, + &gHardwareInterrupt2ProtocolGuid, NULL, (VOID **)&mInterruptProtocol ); @@ -331,13 +331,19 @@ GenericWatchdogEntry ( WatchdogInterruptHandler ); if (!EFI_ERROR (Status)) { - // Install the Timer Architectural Protocol onto a new handle - Handle = NULL; - Status = gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, - NULL - ); + Status = mInterruptProtocol->SetTriggerType ( + mInterruptProtocol, + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), + EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING); + if (!EFI_ERROR (Status)) { + // Install the Timer Architectural Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer, + NULL + ); + } } } }