From patchwork Tue Sep 12 08:34:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 112253 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4880962qgf; Tue, 12 Sep 2017 01:35:25 -0700 (PDT) X-Received: by 10.98.220.66 with SMTP id t63mr14696158pfg.328.1505205325503; Tue, 12 Sep 2017 01:35:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505205325; cv=none; d=google.com; s=arc-20160816; b=L+lUWmZCflZwanQmQxHgxBzl+wGLU1yh+PLTe44ETBYUO5V+N5L8ARQPtTbiGJWfAM lWgZt/b9O/H3XqXh3W/rh3m7Xd210bJ1m8wPYXKGkpjgkWX9HORM/8xupavBP+Bu+qQG Mywkx63L+E7JDLFK6hVp2mMkz9mzYPK59APiPtDGvtMrEwDnTWPddN5fIb6leEfH8AOu 06PAbwKZlCJfG9ef3gSUbsa9pDbEec+KWyGa+aehX0hFvxfvFphNEQhJVRbw8THG3Hn7 zVbuH8w7sguUpgvjdNo1iykePmHehvTcOLngQtIHcUWk7UAvc/agkWXs9cCBmzGHzWPZ GLeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=//UwRE2ND77guwTYUG3tcO2LhAn9wAAvlnwex+hmMq4=; b=c74r5sC0QselEOO/moXsdflKEYEsEYWwQ4JVS2OB8HYxzcCdBhwwdZfoNiTVICUGQo WUpRz4MI0X0lXJ1TrNhXGxsXwqUut0NllS3kEaTDiArpm7j8TfcqM0RbVbPAKqjhszRx O7VCGmbuX4F/zlidZZyVTCzjcbVnN/yRSQYnz8p5H/4xCxW5oXdJF+VkWJlRi1AD1eDf 13z8W7oxTSgeH+FEKiFXxKsQIsUSjt/R2VLOIrpUU4qu6QDAOKoHSHZZe5MZFlikDtpw cUpk4DS+cPzEV+Cfzk6ZnFkXUGRKkBA+grxXqHR9r25QzqAumEiufp0FT9B4PblxbJXy lUrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wMPHuMze; spf=pass (google.com: domain of gcc-patches-return-461893-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461893-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id s10si4710605pgr.417.2017.09.12.01.35.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 01:35:25 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-461893-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wMPHuMze; spf=pass (google.com: domain of gcc-patches-return-461893-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461893-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=uxhVQg+dvWao2P6YtjAVbuWiVAXUd03hcgdi+syJPaUAZQS2lONVz Jgc82uNk1EDtao41GfAuIJwR4JAIQ6jWi7H7CfvvNgJ8mQI9rlrWkhGCvhkGpK/Y 1JmzWZRKvPu32VTtlsWCVAM7sF0th0BZiJCfC4evxhBoOdz2aOMclA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=OrvdAY4DMXMhy98nR0B3Uy8HUD4=; b=wMPHuMzeJ+1yvKhRX+rm oBY+Ax5iyb4y7BKmEgyqCCwpYOV1DmA+PXGclQ0ThRM/UN3IjMKEi9+UZCat4dre k5F/J1ayIw++O55lpPwDk7c8gmN5ZdcY1xjPCXJzU9v0yxZrwyYleQT6LkE/c4Yk E3iqa/1i9IgMNz1ATcIMH78= Received: (qmail 74987 invoked by alias); 12 Sep 2017 08:34:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 74890 invoked by uid 89); 12 Sep 2017 08:34:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:charles X-HELO: mail-wr0-f172.google.com Received: from mail-wr0-f172.google.com (HELO mail-wr0-f172.google.com) (209.85.128.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Sep 2017 08:34:55 +0000 Received: by mail-wr0-f172.google.com with SMTP id m18so19037963wrm.2 for ; Tue, 12 Sep 2017 01:34:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=//UwRE2ND77guwTYUG3tcO2LhAn9wAAvlnwex+hmMq4=; b=P4yNHi/PbaYRxka9M5vZJyeJvXDHlxBVi61ENLZ/ex2H8So/dmvgvcmRcEoxkyraJy DWD2PFuijLayohqfVsehXwMDujjPSbKhk4CpGIFqy/uqKDQe+zznCwA6u2D5S2vApFaC YON74OIKzRCy5FOAmre4L88BVLiJ/fkFya30DcVIlmdVnUDJD1nUbB95AxguR80wv18h eK3H3+74ugYGhI+xtcPNaZA6IW2kkIZP0XY6PJAmoODT5t4OlNNVHw6dCXUcbK6zoBv5 qNARLzAOLt5TQZZXS8CKi5gFFf3Slt4270322EEDUKTQ47p3WiLnvwcnN/BVsTA3mb6w ce3A== X-Gm-Message-State: AHPjjUgnNJv9rvuttJZ5sbNV9KAFbdDdP9RlEKmNIM4i7FPctDRfLYeR PTpY4xrRSoKpfdtW X-Google-Smtp-Source: ADKCNb4kfqZB7oSnkZeZ0u9hutwxZtsy+HyAnl1sYdbjc9N+C/ZO4l6NA8xM8hv9qmqELAoxMtGSyw== X-Received: by 10.223.170.202 with SMTP id i10mr11500880wrc.232.1505205293363; Tue, 12 Sep 2017 01:34:53 -0700 (PDT) Received: from localhost.localdomain (cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net. [86.26.39.137]) by smtp.gmail.com with ESMTPSA id s126sm13321227wmd.46.2017.09.12.01.34.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Sep 2017 01:34:52 -0700 (PDT) From: charles.baylis@linaro.org To: rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com, kyrylo.tkachov@arm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params Date: Tue, 12 Sep 2017 09:34:35 +0100 Message-Id: <1505205277-26276-2-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> References: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis Add bus widths. These use the approximation that v7 and later cores have 64bit data bus width, and earlier cores have 32 bit bus width, with the exception of v7m. Charles Baylis * config/arm/arm-protos.h (struct tune_params): New field bus_width. * config/arm/arm.c (arm_slowmul_tune): Initialise bus_width field. (arm_fastmul_tune): Likewise. (arm_strongarm_tune): Likewise. (arm_xscale_tune): Likewise. (arm_9e_tune): Likewise. (arm_marvell_pj4_tune): Likewise. (arm_v6t2_tune): Likewise. (arm_cortex_tune): Likewise. (arm_cortex_a8_tune): Likewise. (arm_cortex_a7_tune): Likewise. (arm_cortex_a15_tune): Likewise. (arm_cortex_a35_tune): Likewise. (arm_cortex_a53_tune): Likewise. (arm_cortex_a57_tune): Likewise. (arm_exynosm1_tune): Likewise. (arm_xgene1_tune): Likewise. (arm_cortex_a5_tune): Likewise. (arm_cortex_a9_tune): Likewise. (arm_cortex_a12_tune): Likewise. (arm_cortex_a73_tune): Likewise. (arm_v7m_tune): Likewise. (arm_cortex_m7_tune): Likewise. (arm_v6m_tune): Likewise. (arm_fa726te_tune): Likewise. Change-Id: I613e876db93ffd6f8c1e72ba483be2efc0b56d66 --- gcc/config/arm/arm-protos.h | 2 ++ gcc/config/arm/arm.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) -- 2.7.4 diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 4538078..47a85cc 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -278,6 +278,8 @@ struct tune_params int max_insns_inline_memset; /* Issue rate of the processor. */ unsigned int issue_rate; + /* Bus width (bits). */ + unsigned int bus_width; /* Explicit prefetch data. */ struct { diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index bca8a34..32001e5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1761,6 +1761,7 @@ const struct tune_params arm_slowmul_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1783,6 +1784,7 @@ const struct tune_params arm_fastmul_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1808,6 +1810,7 @@ const struct tune_params arm_strongarm_tune = 3, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1830,6 +1833,7 @@ const struct tune_params arm_xscale_tune = 3, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1852,6 +1856,7 @@ const struct tune_params arm_9e_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1874,6 +1879,7 @@ const struct tune_params arm_marvell_pj4_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -1896,6 +1902,7 @@ const struct tune_params arm_v6t2_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1920,6 +1927,7 @@ const struct tune_params arm_cortex_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1942,6 +1950,7 @@ const struct tune_params arm_cortex_a8_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1964,6 +1973,7 @@ const struct tune_params arm_cortex_a7_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -1986,6 +1996,7 @@ const struct tune_params arm_cortex_a15_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 3, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2008,6 +2019,7 @@ const struct tune_params arm_cortex_a35_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2030,6 +2042,7 @@ const struct tune_params arm_cortex_a53_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2052,6 +2065,7 @@ const struct tune_params arm_cortex_a57_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 3, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2074,6 +2088,7 @@ const struct tune_params arm_exynosm1_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 3, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2096,6 +2111,7 @@ const struct tune_params arm_xgene1_tune = 2, /* Max cond insns. */ 32, /* Memset max inline. */ 4, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2121,6 +2137,7 @@ const struct tune_params arm_cortex_a5_tune = 1, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2143,6 +2160,7 @@ const struct tune_params arm_cortex_a9_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_BENEFICIAL(4,32,32), tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2165,6 +2183,7 @@ const struct tune_params arm_cortex_a12_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2187,6 +2206,7 @@ const struct tune_params arm_cortex_a73_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_TRUE, @@ -2216,6 +2236,7 @@ const struct tune_params arm_v7m_tune = 2, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -2240,6 +2261,7 @@ const struct tune_params arm_cortex_m7_tune = 1, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 64, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, @@ -2265,6 +2287,7 @@ const struct tune_params arm_v6m_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 1, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_FALSE, tune_params::PREF_LDRD_FALSE, @@ -2287,6 +2310,7 @@ const struct tune_params arm_fa726te_tune = 5, /* Max cond insns. */ 8, /* Memset max inline. */ 2, /* Issue rate. */ + 32, /* Bus width. */ ARM_PREFETCH_NOT_BENEFICIAL, tune_params::PREF_CONST_POOL_TRUE, tune_params::PREF_LDRD_FALSE, From patchwork Tue Sep 12 08:34:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 112254 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4881308qgf; Tue, 12 Sep 2017 01:35:48 -0700 (PDT) X-Received: by 10.99.114.76 with SMTP id c12mr13781560pgn.221.1505205348270; Tue, 12 Sep 2017 01:35:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505205348; cv=none; d=google.com; s=arc-20160816; b=H7NPeKb+Kh8zp7oI8o7We2pTrmOYijcjzvTBMTSFBRwU9oO9KRAqIJwquLE+KOl/1I vWa/YwATAyRDf1NhpbONt/GdobOGaCjG+kuuI/Wo4o+f5+Rc/w08dQqRx+wrP8+7A6ps x6p70xE17GRda0Xj2r6n4Pw4tzjSJxeqF0cCP5lAJPTZoHcz7ODYgRU9lI5HzgugbKi/ 4jqveuGLrQDLFiakl78psWO+kcPXu9P1ltmNZT2iqDhpQxoMlEUX8dHZbyOwN6fS94Pg pL1Sqg6Kkn2gCOGieyG5BTNwfrxRYvtBao5CuWF+EZxqsSm6+nPdhQzUNlZhDRhMP9GK Yiwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=DQRhajOLkIRNno4LcKAYiHFaexKOXmrd9AacYrbw4zQ=; b=cRbhgsLmz0U4nlDmQwNEKnZVZlVujAus1iovPjBd/hGkvT+MED6+1jbdDPubRK9MMZ jTzSsrHMVq2YBo5Vj8qmXR8a9TVSGq/RfkcMm3Mfu1JT/guJh6RCM1qKi46Z0lDnC2ML W8SpNf8Jm6bpiKOx3O+NiV/mKbHB60w6jdTxdjyFv/lheYOkRx07M56xo7cvtUSM0luy Pe8gO8tiMAoL37NrtnNH5arxrGFbrWtcMrGuhJrVkgpscbQUdpk031yboGooaWGxcy2A qHtIMKcXxmYOvAhVjiTqyTzmDVhYrXzSoaG7DVvzXIMGcPYccrwc46Hnmou7Qcc9YOO4 k8Iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=F95YookR; spf=pass (google.com: domain of gcc-patches-return-461894-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461894-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 64si8295241ply.469.2017.09.12.01.35.48 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 01:35:48 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-461894-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=F95YookR; spf=pass (google.com: domain of gcc-patches-return-461894-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461894-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=cTW528XrdeUcj2xP3DaVCv0sQMl/Sy/QH1M0mOQwblJJ52SEW8DEa 5gPtJBa/B3rMASd6s0i2a48AeRVrNC7y7STChHoPvvR/8MRuoF/2mQNS1kiI5e1T 5gFoE55auFcnH3hcODMZ5WOK9nLM5bhZDqzozRwdF3r2DsLAWUuUG4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=Nr1Wh96q/z7rrs58aXGAYCH2r7s=; b=F95YookR7V8Fn9XTv332 ixT/1OiAk5ZU4WNfOVWeb48WR2pXKs8sTLhSh8GfRFSosE9LL/qmbnXMTKrm9Qic OKP1opH9CekGCadiEJjiPfhhU3LdEcUnsjqYY97CjNIYe64e9nYGVb4Uy5HEKoC2 QjGdvXsfqPmiTmY+6yX1rOs= Received: (qmail 76004 invoked by alias); 12 Sep 2017 08:35:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75867 invoked by uid 89); 12 Sep 2017 08:35:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f170.google.com Received: from mail-wr0-f170.google.com (HELO mail-wr0-f170.google.com) (209.85.128.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Sep 2017 08:34:58 +0000 Received: by mail-wr0-f170.google.com with SMTP id v109so19072088wrc.1 for ; Tue, 12 Sep 2017 01:34:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DQRhajOLkIRNno4LcKAYiHFaexKOXmrd9AacYrbw4zQ=; b=k3fmNDiQxEOe+R601rMC61elFcY7WZzVD4xIReeNX0vk5Gj/WkfL6mkuh9OShrYajf NU3G7heYuit3Axhd8JkC37OtBXFH0tGggDH7XkfKrX5BCV9wUiS9qB7u21huFVR0RbjH CgD+rnfrThF4tGxxzZevVxjqW15x4p9A0WROw/t4rznOaI1trNdQy1CiE1jpJSt4+Xwf OrU9q7JlrDmi/bCZ/UXFug+UEJ2A0oP46yRVpx4nIK+setxTz0blL3HjCOP9eRdqpKJX 63lvX6h0LMs/6SofmEkIx6pTrsa1SziCxIRekgthrn5s7ZvKqp2pB+3htxYNUPJHuaDs vdUw== X-Gm-Message-State: AHPjjUg3sauOPXcEeypvicK3d6wvLV/jiS7hoE9+mYL4qxS1Mj4o1wrZ tg7UPQJuA29c2E7e X-Google-Smtp-Source: ADKCNb6e1ypQ8yq8YRKhKOSqgyeNA745rluQX7NLHKU4RX10kDEmyWE3PczWg3S1G+jONDVb6wSftg== X-Received: by 10.223.135.97 with SMTP id 30mr9976757wrz.245.1505205296712; Tue, 12 Sep 2017 01:34:56 -0700 (PDT) Received: from localhost.localdomain (cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net. [86.26.39.137]) by smtp.gmail.com with ESMTPSA id s126sm13321227wmd.46.2017.09.12.01.34.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Sep 2017 01:34:56 -0700 (PDT) From: charles.baylis@linaro.org To: rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com, kyrylo.tkachov@arm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] [ARM] Refactor costs calculation for MEM. Date: Tue, 12 Sep 2017 09:34:36 +0100 Message-Id: <1505205277-26276-3-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> References: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis This patch moves the calculation of costs for MEM into a separate function, and reforms the calculation into two parts. Firstly any additional cost of the addressing mode is calculated, and then the cost of the memory access itself is added. In this patch, the calculation of the cost of the addressing mode is left as a placeholder, to be added in a subsequent patch. gcc/ChangeLog: Charles Baylis * config/arm/arm.c (arm_mem_costs): New function. (arm_rtx_costs_internal): Use arm_mem_costs. gcc/testsuite/ChangeLog: Charles Baylis * gcc.target/arm/addr-modes-float.c: New test. * gcc.target/arm/addr-modes-int.c: New test. * gcc.target/arm/addr-modes.h: New header. Change-Id: I99e93406ea39ee31f71c7bf428ad3e127b7a618e --- gcc/config/arm/arm.c | 67 ++++++++++++++++--------- gcc/testsuite/gcc.target/arm/addr-modes-float.c | 42 ++++++++++++++++ gcc/testsuite/gcc.target/arm/addr-modes-int.c | 46 +++++++++++++++++ gcc/testsuite/gcc.target/arm/addr-modes.h | 53 +++++++++++++++++++ 4 files changed, 183 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/addr-modes-float.c create mode 100644 gcc/testsuite/gcc.target/arm/addr-modes-int.c create mode 100644 gcc/testsuite/gcc.target/arm/addr-modes.h -- 2.7.4 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 32001e5..b8dbed6 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9228,8 +9228,48 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost) } \ while (0); +/* Helper function for arm_rtx_costs_internal. Calculates the cost of a MEM, + considering the costs of the addressing mode and memory access + separately. */ +static bool +arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost, + int *cost, bool speed_p) +{ + machine_mode mode = GET_MODE (x); + if (flag_pic + && GET_CODE (XEXP (x, 0)) == PLUS + && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) + /* This will be split into two instructions. Add the cost of the + additional instruction here. The cost of the memory access is computed + below. See arm.md:calculate_pic_address. */ + *cost = COSTS_N_INSNS (1); + else + *cost = 0; + + /* Calculate cost of the addressing mode. */ + if (speed_p) + { + /* TODO: Add table-driven costs for addressing modes. (See patch 2) */ + } + + /* Calculate cost of memory access. */ + if (speed_p) + { + /* data transfer is transfer size divided by bus width. */ + int bus_width_bytes = current_tune->bus_width / 4; + *cost += CEIL (GET_MODE_SIZE (mode), bus_width_bytes); + *cost += extra_cost->ldst.load; + } + else + { + *cost += COSTS_N_INSNS (1); + } + + return true; +} + /* RTX costs. Make an estimate of the cost of executing the operation - X, which is contained with an operation with code OUTER_CODE. + X, which is contained within an operation with code OUTER_CODE. SPEED_P indicates whether the cost desired is the performance cost, or the size cost. The estimate is stored in COST and the return value is TRUE if the cost calculation is final, or FALSE if the @@ -9308,30 +9348,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; case MEM: - /* A memory access costs 1 insn if the mode is small, or the address is - a single register, otherwise it costs one insn per word. */ - if (REG_P (XEXP (x, 0))) - *cost = COSTS_N_INSNS (1); - else if (flag_pic - && GET_CODE (XEXP (x, 0)) == PLUS - && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) - /* This will be split into two instructions. - See arm.md:calculate_pic_address. */ - *cost = COSTS_N_INSNS (2); - else - *cost = COSTS_N_INSNS (ARM_NUM_REGS (mode)); - - /* For speed optimizations, add the costs of the address and - accessing memory. */ - if (speed_p) -#ifdef NOT_YET - *cost += (extra_cost->ldst.load - + arm_address_cost (XEXP (x, 0), mode, - ADDR_SPACE_GENERIC, speed_p)); -#else - *cost += extra_cost->ldst.load; -#endif - return true; + return arm_mem_costs (x, extra_cost, cost, speed_p); case PARALLEL: { diff --git a/gcc/testsuite/gcc.target/arm/addr-modes-float.c b/gcc/testsuite/gcc.target/arm/addr-modes-float.c new file mode 100644 index 0000000..3b4235c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/addr-modes-float.c @@ -0,0 +1,42 @@ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-do compile } */ + +#include + +#include "addr-modes.h" + +POST_STORE(float) +/* { dg-final { scan-assembler "vstmia.32" } } */ +POST_STORE(double) +/* { dg-final { scan-assembler "vstmia.64" } } */ + +POST_LOAD(float) +/* { dg-final { scan-assembler "vldmia.32" } } */ +POST_LOAD(double) +/* { dg-final { scan-assembler "vldmia.64" } } */ + +POST_STORE_VEC (int8_t, int8x8_t, vst1_s8) +/* { dg-final { scan-assembler "vst1.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ +POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8) +/* { dg-final { scan-assembler "vst1.8\t\{.*\[-,\]d.*\}, \\\[r\[0-9\]+\\\]!" } } */ + +POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8) +/* { dg-final { scan-assembler "vst2.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ +POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8) +/* { dg-final { scan-assembler "vst2.8\t\{.*-d.*\}, \\\[r\[0-9\]+\\\]!" } } */ + +POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8) +/* { dg-final { scan-assembler "vst3.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ +POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8) +/* { dg-final { scan-assembler "vst3.8\t\{d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */ +/* { dg-final { scan-assembler "vst3.8\t\{d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */ + +POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8) +/* { dg-final { scan-assembler "vst4.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */ +POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8) +/* { dg-final { scan-assembler "vst4.8\t\{d\[02468\], d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */ +/* { dg-final { scan-assembler "vst4.8\t\{d\[13579\], d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */ + +/* { dg-final { scan-assembler-not "add" { xfail *-*-* } } } */ diff --git a/gcc/testsuite/gcc.target/arm/addr-modes-int.c b/gcc/testsuite/gcc.target/arm/addr-modes-int.c new file mode 100644 index 0000000..e3e1e6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/addr-modes-int.c @@ -0,0 +1,46 @@ +/* { dg-options "-O2 -march=armv7-a" } */ +/* { dg-add-options arm_neon } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-do compile } */ + +#include "addr-modes.h" + +typedef long long ll; + +PRE_STORE(char) +/* { dg-final { scan-assembler "strb.*#1]!" } } */ +PRE_STORE(short) +/* { dg-final { scan-assembler "strh.*#2]!" } } */ +PRE_STORE(int) +/* { dg-final { scan-assembler "str.*#4]!" } } */ +PRE_STORE(ll) +/* { dg-final { scan-assembler "strd.*#8]!" } } */ + +POST_STORE(char) +/* { dg-final { scan-assembler "strb.*], #1" } } */ +POST_STORE(short) +/* { dg-final { scan-assembler "strh.*], #2" } } */ +POST_STORE(int) +/* { dg-final { scan-assembler "str.*], #4" } } */ +POST_STORE(ll) +/* { dg-final { scan-assembler "strd.*], #8" } } */ + +PRE_LOAD(char) +/* { dg-final { scan-assembler "ldrb.*#1]!" } } */ +PRE_LOAD(short) +/* { dg-final { scan-assembler "ldrsh.*#2]!" } } */ +PRE_LOAD(int) +/* { dg-final { scan-assembler "ldr.*#4]!" } } */ +PRE_LOAD(ll) +/* { dg-final { scan-assembler "ldrd.*#8]!" } } */ + +POST_LOAD(char) +/* { dg-final { scan-assembler "ldrb.*], #1" } } */ +POST_LOAD(short) +/* { dg-final { scan-assembler "ldrsh.*], #2" } } */ +POST_LOAD(int) +/* { dg-final { scan-assembler "ldr.*], #4" } } */ +POST_LOAD(ll) +/* { dg-final { scan-assembler "ldrd.*], #8" } } */ + +/* { dg-final { scan-assembler-not "\tadd" } } */ diff --git a/gcc/testsuite/gcc.target/arm/addr-modes.h b/gcc/testsuite/gcc.target/arm/addr-modes.h new file mode 100644 index 0000000..eac4678 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/addr-modes.h @@ -0,0 +1,53 @@ + +#define PRE_STORE(T) \ + T * \ + T ## _pre_store (T *p, T v) \ + { \ + *++p = v; \ + return p; \ + } \ + +#define POST_STORE(T) \ + T * \ + T ## _post_store (T *p, T v) \ + { \ + *p++ = v; \ + return p; \ + } + +#define POST_STORE_VEC(T, VT, OP) \ + T * \ + VT ## _post_store (T * p, VT v) \ + { \ + OP (p, v); \ + p += sizeof (VT) / sizeof (T); \ + return p; \ + } + +#define PRE_LOAD(T) \ + void \ + T ## _pre_load (T *p) \ + { \ + extern void f ## T (T*,T); \ + T x = *++p; \ + f ## T (p, x); \ + } + +#define POST_LOAD(T) \ + void \ + T ## _post_load (T *p) \ + { \ + extern void f ## T (T*,T); \ + T x = *p++; \ + f ## T (p, x); \ + } + +#define POST_LOAD_VEC(T, VT, OP) \ + void \ + VT ## _post_load (T * p) \ + { \ + extern void f ## T (T*,T); \ + VT x = OP (p, v); \ + p += sizeof (VT) / sizeof (T); \ + f ## T (p, x); \ + } From patchwork Tue Sep 12 08:34:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 112255 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4881519qgf; Tue, 12 Sep 2017 01:36:04 -0700 (PDT) X-Received: by 10.99.95.147 with SMTP id t141mr14642646pgb.340.1505205364322; Tue, 12 Sep 2017 01:36:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505205364; cv=none; d=google.com; s=arc-20160816; b=gAD4XixpiazYDec18W4Dnp732OJFsT57QTtKjqJ2arXPsrJ7uN5b+pMaLWVqKQv2R7 xAIUoWq8vaa11SExyMpT0cB0c6kKHgBkywgi7g4h60RUnvIAZrj05nftzl6IrijpE3vQ bY3BzvDjfnsiYbQVLY6pmM+LuY+UJU682Z9W9iT5dXolt2ob9ll1rS/ygQdqGWYQ679r SjEGK/YhWvV6mYT7omseMDOKihDxkb8kpyKCcktRGzT0NKYa86iPtz6cNm9hn9hENoff 21dsQtugajAxvv9yFYI1B/qF33ilJBbkTi+rI8N8KoTLRkgOtjpA0iIhCC73b9LRIOB9 ZGvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=NbPr68XWvqbEmdxyvktwj0aLFXIp7UXh/gXRQgvwtaY=; b=f3xOQiueNTdTnt1VQZD1SJ5xLMDyxlFxfJmmzEW4v8BMPHfuep5qbhRJpJcCWwJ5gT EuFyO7o4RjdQ+0+zTcoBkTBDD1zIVAw/0cVeyYb+/H9xkkajqcZZSGeJtt47w5A64wJC wfqYlzAs9BhliPbj/yRV0cg4rlfl55JT/UsuV8SKg0Hw73xynsFvJbMaw6Y7OYZkWoFh 10B2lEtwQRj+gJd8AXRMBa/1ZgniBpeAeLmZcRUpPRW6yCM1vXE8MaY8EuVoHQ7PDuoS A71VhWY5iKoSf5dHiqSJFHHeVGM6SiTR1Sxe1XQpRNV3mL2BwY/hOpfmzbMuENyBZqbD I00Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=sy0OqUlg; spf=pass (google.com: domain of gcc-patches-return-461895-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461895-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 10si7081465pfj.239.2017.09.12.01.36.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 01:36:04 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-461895-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=sy0OqUlg; spf=pass (google.com: domain of gcc-patches-return-461895-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461895-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=YCqj7BC0DlTRk+ObZtVQBjPnc0RFJZDuW9x3lBOttiNIkJvvibvnP k9nebmO2xXs7HtAs45sKFT2VOh7LFsSzH1XTa8wWN7v9HacQkU0kFM2dn+9L/me6 F7EjFDv1U4DuaX9g/RfJKjmNkVzvKbP6pRG0lk0ALKhYsGwlOj6AyY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=wYebF4JJBs07OMEN24wCwcpy7ww=; b=sy0OqUlgWOxO1fKVPDxo nf3lZ01NiBYiAKg0cOpcDW32x7Kx0s3lIcuQYDe4FaWbAZo0yckIofjvHbiqeaUN GCNjc2LZmaWwCm4Maxv6scBLO3QDThn7vLb7m5KsxW/gF56eR+dL8Lguhv/i3woT R+y9KmaRzb/dY4aN+90afLc= Received: (qmail 76493 invoked by alias); 12 Sep 2017 08:35:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 76399 invoked by uid 89); 12 Sep 2017 08:35:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f182.google.com Received: from mail-wr0-f182.google.com (HELO mail-wr0-f182.google.com) (209.85.128.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Sep 2017 08:35:01 +0000 Received: by mail-wr0-f182.google.com with SMTP id 108so19040632wra.5 for ; Tue, 12 Sep 2017 01:35:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NbPr68XWvqbEmdxyvktwj0aLFXIp7UXh/gXRQgvwtaY=; b=QaobSZFPuEfmhdCKOOEB094iIuR8haZ0gsgGhGrLmgL/mUFSwR3y9wRGht5YFKoYx2 LKAImAWjKFWUHLAOOAfMx0hbzQNQmCFSfk4mMwP1iExNOTexAX53GdbjNWsjFRYGO1NF Zot2N0NmB6ISbJS3X8EUpnsow0LlBv2PaInqC2HSfo5DGBznnxbm0UJpCvM8Cr0JWs9j jQ17lHSCcWESSrdOVxSWDo3qbCRIlDI7/8RdzpOqBhn8l1L5X8PMob0SwKtkS64hE8y8 svs32h1GYPW2LhMnsc9babBRqGYRhAFnrOnWQphGF66gzdmNsnb3Af2b+7+2dLEYBbE2 zfpw== X-Gm-Message-State: AHPjjUgOszRQq1NWvfDs1g7cVELEjIadG6Ty/exuWT+DlXj9h9JF7763 gFixgQ/MJIBjiPNh X-Google-Smtp-Source: ADKCNb7g5sYK9THP5SxObAdvrsheT099B9u+vL9VL8x20ks1GGKOWnMdLI67cG652sTb9Oq2R7dL1w== X-Received: by 10.223.134.157 with SMTP id 29mr10310783wrx.72.1505205299180; Tue, 12 Sep 2017 01:34:59 -0700 (PDT) Received: from localhost.localdomain (cpc92322-cmbg19-2-0-cust1928.5-4.cable.virginm.net. [86.26.39.137]) by smtp.gmail.com with ESMTPSA id s126sm13321227wmd.46.2017.09.12.01.34.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 12 Sep 2017 01:34:58 -0700 (PDT) From: charles.baylis@linaro.org To: rearnsha@arm.com, Ramana.Radhakrishnan@arm.com, pinskia@gmail.com, kyrylo.tkachov@arm.com Cc: gcc-patches@gcc.gnu.org Subject: [PATCH 3/3] [ARM] Add table of costs for AAarch32 addressing modes. Date: Tue, 12 Sep 2017 09:34:37 +0100 Message-Id: <1505205277-26276-4-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> References: <1505205277-26276-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis This patch adds support for modelling the varying costs of different addressing modes. The generic cost table treats all addressing modes as having equal cost. gcc/ChangeLog: Charles Baylis * config/arm/arm-protos.h (enum arm_addr_mode_op): New. (struct addr_mode_cost_table): New. (struct tune_params): Add field addr_mode_costs. * config/arm/arm.c (generic_addr_mode_costs): New. (arm_slowmul_tune): Initialise addr_mode_costs field. (arm_fastmul_tune): Likewise. (arm_strongarm_tune): Likewise. (arm_xscale_tune): Likewise. (arm_9e_tune): Likewise. (arm_marvell_pj4_tune): Likewise. (arm_v6t2_tune): Likewise. (arm_cortex_tune): Likewise. (arm_cortex_a8_tune): Likewise. (arm_cortex_a7_tune): Likewise. (arm_cortex_a15_tune): Likewise. (arm_cortex_a35_tune): Likewise. (arm_cortex_a53_tune): Likewise. (arm_cortex_a57_tune): Likewise. (arm_exynosm1_tune): Likewise. (arm_xgene1_tune): Likewise. (arm_cortex_a5_tune): Likewise. (arm_cortex_a9_tune): Likewise. (arm_cortex_a12_tune): Likewise. (arm_cortex_a73_tune): Likewise. (arm_v7m_tune): Likewise. (arm_cortex_m7_tune): Likewise. (arm_v6m_tune): Likewise. (arm_fa726te_tune): Likewise. (arm_mem_costs): Use table lookup to calculate cost of addressing mode. Change-Id: If71bd7c4f4bb876c5ed82dc28791130efb8bf89e --- gcc/config/arm/arm-protos.h | 20 +++++++++++ gcc/config/arm/arm.c | 83 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 102 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 47a85cc..3d6b515 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -261,12 +261,32 @@ struct cpu_vec_costs { struct cpu_cost_table; +/* Addressing mode operations. Used to index tables in struct + addr_mode_cost_table. */ +enum arm_addr_mode_op +{ + AMO_DEFAULT, + AMO_NO_WB, /* Offset with no writeback. */ + AMO_WB, /* Offset with writeback. */ + AMO_MAX /* For array size. */ +}; + +/* Table of additional costs when using addressing modes for each + access type. */ +struct addr_mode_cost_table +{ + const int integer[AMO_MAX]; + const int fp[AMO_MAX]; + const int vector[AMO_MAX]; +}; + /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this structure is modified. */ struct tune_params { const struct cpu_cost_table *insn_extra_cost; + const struct addr_mode_cost_table *addr_mode_costs; bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *); int (*branch_cost) (bool, bool); /* Vectorizer costs. */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b8dbed6..0d31f5f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1751,9 +1751,32 @@ const struct cpu_cost_table v7m_extra_costs = } }; +const struct addr_mode_cost_table generic_addr_mode_costs = +{ + /* int. */ + { + 0, /* AMO_DEFAULT. */ + 0, /* AMO_NO_WB. */ + 0 /* AMO_WB. */ + }, + /* float. */ + { + 0, /* AMO_DEFAULT. */ + 0, /* AMO_NO_WB. */ + 0 /* AMO_WB. */ + }, + /* vector. */ + { + 0, /* AMO_DEFAULT. */ + 0, /* AMO_NO_WB. */ + 0 /* AMO_WB. */ + } +}; + const struct tune_params arm_slowmul_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1777,6 +1800,7 @@ const struct tune_params arm_slowmul_tune = const struct tune_params arm_fastmul_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1803,6 +1827,7 @@ const struct tune_params arm_fastmul_tune = const struct tune_params arm_strongarm_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1826,6 +1851,7 @@ const struct tune_params arm_strongarm_tune = const struct tune_params arm_xscale_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ xscale_sched_adjust_cost, arm_default_branch_cost, &arm_default_vec_cost, @@ -1849,6 +1875,7 @@ const struct tune_params arm_xscale_tune = const struct tune_params arm_9e_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1872,6 +1899,7 @@ const struct tune_params arm_9e_tune = const struct tune_params arm_marvell_pj4_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1895,6 +1923,7 @@ const struct tune_params arm_marvell_pj4_tune = const struct tune_params arm_v6t2_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1920,6 +1949,7 @@ const struct tune_params arm_v6t2_tune = const struct tune_params arm_cortex_tune = { &generic_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1943,6 +1973,7 @@ const struct tune_params arm_cortex_tune = const struct tune_params arm_cortex_a8_tune = { &cortexa8_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1966,6 +1997,7 @@ const struct tune_params arm_cortex_a8_tune = const struct tune_params arm_cortex_a7_tune = { &cortexa7_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -1989,6 +2021,7 @@ const struct tune_params arm_cortex_a7_tune = const struct tune_params arm_cortex_a15_tune = { &cortexa15_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2012,6 +2045,7 @@ const struct tune_params arm_cortex_a15_tune = const struct tune_params arm_cortex_a35_tune = { &cortexa53_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2035,6 +2069,7 @@ const struct tune_params arm_cortex_a35_tune = const struct tune_params arm_cortex_a53_tune = { &cortexa53_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2058,6 +2093,7 @@ const struct tune_params arm_cortex_a53_tune = const struct tune_params arm_cortex_a57_tune = { &cortexa57_extra_costs, + &generic_addr_mode_costs, /* addressing mode costs */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2081,6 +2117,7 @@ const struct tune_params arm_cortex_a57_tune = const struct tune_params arm_exynosm1_tune = { &exynosm1_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2104,6 +2141,7 @@ const struct tune_params arm_exynosm1_tune = const struct tune_params arm_xgene1_tune = { &xgene1_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, @@ -2130,6 +2168,7 @@ const struct tune_params arm_xgene1_tune = const struct tune_params arm_cortex_a5_tune = { &cortexa5_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_cortex_a5_branch_cost, &arm_default_vec_cost, @@ -2153,6 +2192,7 @@ const struct tune_params arm_cortex_a5_tune = const struct tune_params arm_cortex_a9_tune = { &cortexa9_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ cortex_a9_sched_adjust_cost, arm_default_branch_cost, &arm_default_vec_cost, @@ -2176,6 +2216,7 @@ const struct tune_params arm_cortex_a9_tune = const struct tune_params arm_cortex_a12_tune = { &cortexa12_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, /* Vectorizer costs. */ @@ -2199,6 +2240,7 @@ const struct tune_params arm_cortex_a12_tune = const struct tune_params arm_cortex_a73_tune = { &cortexa57_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, /* Vectorizer costs. */ @@ -2229,6 +2271,7 @@ const struct tune_params arm_cortex_a73_tune = const struct tune_params arm_v7m_tune = { &v7m_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_cortex_m_branch_cost, &arm_default_vec_cost, @@ -2254,6 +2297,7 @@ const struct tune_params arm_v7m_tune = const struct tune_params arm_cortex_m7_tune = { &v7m_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_cortex_m7_branch_cost, &arm_default_vec_cost, @@ -2280,6 +2324,7 @@ const struct tune_params arm_cortex_m7_tune = const struct tune_params arm_v6m_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ NULL, /* Sched adj cost. */ arm_default_branch_cost, &arm_default_vec_cost, /* Vectorizer costs. */ @@ -2303,6 +2348,7 @@ const struct tune_params arm_v6m_tune = const struct tune_params arm_fa726te_tune = { &generic_extra_costs, /* Insn extra costs. */ + &generic_addr_mode_costs, /* Addressing mode costs. */ fa726te_sched_adjust_cost, arm_default_branch_cost, &arm_default_vec_cost, @@ -9249,7 +9295,42 @@ arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost, /* Calculate cost of the addressing mode. */ if (speed_p) { - /* TODO: Add table-driven costs for addressing modes. (See patch 2) */ + arm_addr_mode_op op_type; + switch (GET_CODE (XEXP (x, 0))) + { + default: + case REG: + op_type = AMO_DEFAULT; + break; + case MINUS: + /* MINUS does not appear in RTL, but the architecture supports it, + so handle this case defensively. */ + /* fall through */ + case PLUS: + op_type = AMO_NO_WB; + break; + case PRE_INC: + case PRE_DEC: + case POST_INC: + case POST_DEC: + case PRE_MODIFY: + case POST_MODIFY: + op_type = AMO_WB; + break; + } + + if (VECTOR_MODE_P (mode)) + { + *cost += current_tune->addr_mode_costs->vector[op_type]; + } + else if (FLOAT_MODE_P (mode)) + { + *cost += current_tune->addr_mode_costs->fp[op_type]; + } + else + { + *cost += current_tune->addr_mode_costs->integer[op_type]; + } } /* Calculate cost of memory access. */