From patchwork Wed Sep 13 08:56:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112413 Delivered-To: patch@linaro.org Received: by 10.80.202.13 with SMTP id d13csp712747edi; Wed, 13 Sep 2017 01:57:56 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6LM95IkBFkXpJiYPw8aOF715yurVCYQuYOg8crPsqVbJhvw+f+eEFk7QJyX9MIHEdZT/5P X-Received: by 10.84.132.4 with SMTP id 4mr6798021ple.449.1505293076496; Wed, 13 Sep 2017 01:57:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505293076; cv=none; d=google.com; s=arc-20160816; b=jfh8Ah9WatU/FTeAPUBqL18vcZtUzr9AIivVphZbppvI0Kd3i+GfTb3RYvE5B64t7x W5D9agFw9wU12E3WicnDmtIBC4NCgOfhlmAanHXTYBhKjAb59JUXF5A4nUcRqwfhAI1T G3UE/F9nGFmFeBbUGsH9kGOMyflyS0ejfbg+AJKKlNghkYJk2Wg/RCX+0kLwMfCwbWnX g29E2WcdLsSLIonew4soX5ynq/hkmfwIgSmP+VyrnxMmiulC86uv2pcjllfM781IGMRC PNTIjSKGbXDTTbbY+MZXrLM0zQsZVUHkPiQ8W7Ql10/wCxHGUgE938CCbMyDQb+IVa3Y phvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=Fi0rMYmY34XQC0s7Emb9gJxaVO+VmzBCKsLBPuTRECI=; b=Zngm2+hjgudouoXcqZdEWENqF326B8T/sKBcvniWLq0hvLBtgs8i8xlTGptlxnZeDT dyQqqGQsm4x78gathZNchq7Y2abPUGe1No2IEHRuNujNl5VJK8/uhvsNkgvDdApxTcqz AhAree6Ivr/cCTX/aPRHwJaLCfB57qntRwZrEQ1+DcwOPXDT0YuBZbixEm2v8dM0sqxU pPWjo0ZI9HarV+3K87EnASLfmOiF2HLeKm1dFf6aTOvWxTxrbSp3ddavcpIjXkYZifTf jD2E3U4IBgVlntYZ2zgB/FswPDH3mBFhiWZ3qCmtDvEddPmnInUCODK1zT/NILehGYtN 1Zzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=tNqCiR+k; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 9si9162243pgr.594.2017.09.13.01.57.56; Wed, 13 Sep 2017 01:57:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=tNqCiR+k; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751529AbdIMI5z (ORCPT + 5 others); Wed, 13 Sep 2017 04:57:55 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:63482 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751509AbdIMI5y (ORCPT ); Wed, 13 Sep 2017 04:57:54 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8D8ugqj027391; Wed, 13 Sep 2017 17:56:44 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8D8ugqj027391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505293004; bh=K71TLI2/P3W5pwWNaeGBWb/aEFj77mq1rVvWPb8V2yc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tNqCiR+k1LS9sStTgVnfvEBXEfxYZ/xYBrL4uhmK/vlUIg82j2S9V2jh+ad5EqNWc otvvHP8Sz/kIfVFIz9tp+VE7r46iQKmZMbN3n/WGAc2+mGbKejOmkbSMzDWV1Qw05B wZKF71hCm62mmcvo/yzKV3qfv6JDYR4JhFbSohq3ens8rihj+Sb8ZX7Ip/jHEQMi56 4Rr6wyOXDx89JzEjq1eNJ3WEzvztakrZkRx4WB5+rXawdhjtJtLVNFSDMzl2C9KTi6 ylIr1QOnPgPdfxOKRYBloYdlAkTfg+KtUUAmLrurQuN5MGJl/XZut7OR2Cgm5iXMIP kiuinI0BGzgNA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Marc Zyngier , linux-gpio@vger.kernel.org Cc: Thomas Gleixner , Jason Cooper , Rob Herring , Linus Walleij , David Daney , Masami Hiramatsu , Jassi Brar , Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH v5 1/3] irqdomain: export of_phandle_args_to_fwspec Date: Wed, 13 Sep 2017 17:56:28 +0900 Message-Id: <1505292990-22957-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505292990-22957-1-git-send-email-yamada.masahiro@socionext.com> References: <1505292990-22957-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This helper will be useful for irqchip drivers that need to convert DT binding into IRQ fwspec. Signed-off-by: Masahiro Yamada --- This patch is necessary for my GPIO driver. Since it is trivial enough, I hope Marc will allow this to go though the GPIO subsystem. If this patch is rejected, I can copy this function into my GPIO driver, but I'd like to avoid code duplication. include/linux/irqdomain.h | 2 ++ kernel/irq/irqdomain.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 81e4889..440772c 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -259,6 +259,8 @@ extern void irq_set_default_host(struct irq_domain *host); extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs, irq_hw_number_t hwirq, int node, const struct cpumask *affinity); +extern void of_phandle_args_to_fwspec(struct of_phandle_args *irq_data, + struct irq_fwspec *fwspec); static inline struct fwnode_handle *of_node_to_fwnode(struct device_node *node) { diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index e84b705..e34cd63 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -727,8 +727,8 @@ static int irq_domain_translate(struct irq_domain *d, return 0; } -static void of_phandle_args_to_fwspec(struct of_phandle_args *irq_data, - struct irq_fwspec *fwspec) +void of_phandle_args_to_fwspec(struct of_phandle_args *irq_data, + struct irq_fwspec *fwspec) { int i; @@ -738,6 +738,7 @@ static void of_phandle_args_to_fwspec(struct of_phandle_args *irq_data, for (i = 0; i < irq_data->args_count; i++) fwspec->param[i] = irq_data->args[i]; } +EXPORT_SYMBOL_GPL(of_phandle_args_to_fwspec); unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) { From patchwork Wed Sep 13 08:56:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112415 Delivered-To: patch@linaro.org Received: by 10.80.202.13 with SMTP id d13csp713137edi; Wed, 13 Sep 2017 01:58:37 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6AywgYALxx0p3sjb0WDc6ivCa7Xd72il1se3YcqJp4eNLw4LHZ/9/l1ZWLtUU1EQ76MtZR X-Received: by 10.98.236.198 with SMTP id e67mr17146969pfm.157.1505293117391; Wed, 13 Sep 2017 01:58:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505293117; cv=none; d=google.com; s=arc-20160816; b=AjH6/xtKSFO/AkeHnyb81rEvckQKcVobvsO+oLj92z2wlvBF8FmApfmi9z0IS4U1oi xdfoOtE6w9aYGJmsq5bdQj6md5W0eIMihUX7AU2VYaI2Hm2F2rEhCE2l+CflxZD0QaV8 HIFfTsV82rprDCt7p6/K2tZRI1NXFyvxigtkBiGGHMcAht2x08uR/7pY2InKSYp+Gh43 qjLRMFbTm9JLY0tE3Td8I4K49RMuxugEcNW41CySIYe1L8M5aOmtzeYis9PA8q9Mzkj9 F3Ak+wsA0D/hEkge0r3O2FXM6jk5aqqL6Nf1RiF5nDLS0Pq3p+kgHZ9VTGLqli+Fencd wo8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=pZkNRP2KT5+pPAVI/bXlZE1IQVtBW/ZWGXVDruQSTts=; b=pyBVjB7eiFa1B/ZDJ8Pcw+QAlb01VBJ9XbetwzLiLzTBVZgAx6KTTxnsJII+r7Uv1M VUd7e7uyA3qlIP92hrYKp9CaVK3jHo609kvAA+9EJJ+aIAL+p5f3BLYAIUiS4mC8bf8z ywC9f+jWRCZYFLt2f53vCyCHAqb/v4CdP2ZnXKCB+6n78qWOO39ua9KHlmfILkwAL8RD 3qg0789Wt1+7eHvQZiEt6lzRzEt42GQsW/NgluX86+yPJRtuGNyVvQ1WCoFG/NAnkm5U eoFJJbDbKHJvWK3HrNppiFEkJOBDk/pBqrdgyykZ/okp9xvOvDun9ahbNMpiPhq4yrgw fkXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=xR8mK0R1; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p14si10286994pli.693.2017.09.13.01.58.37; Wed, 13 Sep 2017 01:58:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=xR8mK0R1; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752110AbdIMI6g (ORCPT + 5 others); Wed, 13 Sep 2017 04:58:36 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:64543 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752090AbdIMI6a (ORCPT ); Wed, 13 Sep 2017 04:58:30 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8D8ugql027391; Wed, 13 Sep 2017 17:56:46 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8D8ugql027391 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505293007; bh=MeHoC8YLCKkxVH+G0Wb3+ycFPU1lo5L6OhpxJmIaJ7g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xR8mK0R1olfATFhArdbnBdUa/Bw2m7UbRlp8p4V0xuGhLkZvQ/KKi1L4kDTfI4ZSZ D0lqVMJIqLuomDaKQGjPq0j0M3GJ4g3LGjujDm+BnqjG6iLqwAModwG1k+rFSvWnJx MeRcMpBw58AKhDgosxaamIkxqrslxZF1LOnWEHgJ5I7gWkYWANpBDj9vBJQDhVAG/O H1gvcBULC0BixYpnX2iZCyhzQuqDI0sWUUTlSm9E27DZWbojqLiOrSU8yifvDSPdHR vlxtwhDOGTiLLMly0MyEELURGKjZe64KJ5KwC412ip8bKLV0sWx3z3N4EoezTfKLAn GeDJljKvAtvpg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: Marc Zyngier , linux-gpio@vger.kernel.org Cc: Thomas Gleixner , Jason Cooper , Rob Herring , Linus Walleij , David Daney , Masami Hiramatsu , Jassi Brar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/3] gpio: uniphier: add UniPhier GPIO controller driver Date: Wed, 13 Sep 2017 17:56:30 +0900 Message-Id: <1505292990-22957-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505292990-22957-1-git-send-email-yamada.masahiro@socionext.com> References: <1505292990-22957-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This GPIO controller is used on UniPhier SoC family. It also serves as an interrupt controller, but interrupt signals are just delivered to the parent irqchip without any latching or OR'ing. This is implemented by using hierarchy IRQ domain. Signed-off-by: Masahiro Yamada --- MAINTAINERS | 1 + drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uniphier.c | 504 +++++++++++++++++++++++++++++++ include/dt-bindings/gpio/uniphier-gpio.h | 18 ++ 5 files changed, 532 insertions(+) create mode 100644 drivers/gpio/gpio-uniphier.c create mode 100644 include/dt-bindings/gpio/uniphier-gpio.h -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/MAINTAINERS b/MAINTAINERS index f46a322..f7c9cfa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2013,6 +2013,7 @@ F: arch/arm/mm/cache-uniphier.c F: arch/arm64/boot/dts/socionext/ F: drivers/bus/uniphier-system-bus.c F: drivers/clk/uniphier/ +F: drivers/gpio/gpio-uniphier.c F: drivers/i2c/busses/i2c-uniphier* F: drivers/irqchip/irq-uniphier-aidet.c F: drivers/pinctrl/uniphier/ diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3f80f16..25c0f308 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -475,6 +475,14 @@ config GPIO_TZ1090_PDC help Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs. +config GPIO_UNIPHIER + tristate "UniPhier GPIO support" + depends on ARCH_UNIPHIER || COMPILE_TEST + depends on OF_GPIO + select IRQ_DOMAIN_HIERARCHY + help + Say yes here to support UniPhier GPIOs. + config GPIO_VF610 def_bool y depends on ARCH_MXC && SOC_VF610 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aeb70e9d..472f675 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -131,6 +131,7 @@ obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o obj-$(CONFIG_GPIO_TZ1090_PDC) += gpio-tz1090-pdc.o obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o +obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c new file mode 100644 index 0000000..450474d --- /dev/null +++ b/drivers/gpio/gpio-uniphier.c @@ -0,0 +1,504 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UNIPHIER_GPIO_BANK_MASK \ + GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0) + +#define UNIPHIER_GPIO_IRQ_MAX_NUM 24 + +#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */ +#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */ +#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */ +#define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */ +#define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */ +#define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */ + +struct uniphier_gpio_priv { + struct gpio_chip chip; + struct irq_chip irq_chip; + struct irq_domain *domain; + void __iomem *regs; + spinlock_t lock; + u32 saved_vals[0]; +}; + +static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) +{ + unsigned int reg; + + reg = (bank + 1) * 8; + + /* + * Unfortunately, the GPIO port registers are not contiguous because + * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. + */ + if (reg >= UNIPHIER_GPIO_IRQ_EN) + reg += 0x10; + + return reg; +} + +static void uniphier_gpio_get_bank_and_mask(unsigned int offset, + unsigned int *bank, u32 *mask) +{ + *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; + *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); +} + +static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv, + unsigned int reg, u32 mask, u32 val) +{ + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(&priv->lock, flags); + tmp = readl(priv->regs + reg); + tmp &= ~mask; + tmp |= mask & val; + writel(tmp, priv->regs + reg); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, + unsigned int reg, u32 mask, u32 val) +{ + struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); + + if (!mask) + return; + + uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, + mask, val); +} + +static void uniphier_gpio_offset_write(struct gpio_chip *chip, + unsigned int offset, unsigned int reg, + int val) +{ + unsigned int bank; + u32 mask; + + uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); + + uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); +} + +static int uniphier_gpio_offset_read(struct gpio_chip *chip, + unsigned int offset, unsigned int reg) +{ + struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); + unsigned int bank, reg_offset; + u32 mask; + + uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); + reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; + + return !!(readl(priv->regs + reg_offset) & mask); +} + +static int uniphier_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR); +} + +static int uniphier_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1); + + return 0; +} + +static int uniphier_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0); + + return 0; +} + +static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA); +} + +static void uniphier_gpio_set(struct gpio_chip *chip, + unsigned int offset, int val) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); +} + +static void uniphier_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + unsigned int bank, shift, bank_mask, bank_bits; + int i; + + for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) { + bank = i / UNIPHIER_GPIO_LINES_PER_BANK; + shift = i % BITS_PER_LONG; + bank_mask = (mask[BIT_WORD(i)] >> shift) & + UNIPHIER_GPIO_BANK_MASK; + bank_bits = bits[BIT_WORD(i)] >> shift; + + uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, + bank_mask, bank_bits); + } +} + +static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct irq_fwspec fwspec; + + if (offset < UNIPHIER_GPIO_IRQ_OFFSET) + return -ENXIO; + + fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node); + fwspec.param_count = 2; + fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET; + fwspec.param[1] = IRQ_TYPE_NONE; + + return irq_create_fwspec_mapping(&fwspec); +} + +static void uniphier_gpio_irq_mask(struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = data->chip_data; + u32 mask = BIT(data->hwirq); + + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0); + + return irq_chip_mask_parent(data); +} + +static void uniphier_gpio_irq_unmask(struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = data->chip_data; + u32 mask = BIT(data->hwirq); + + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask); + + return irq_chip_unmask_parent(data); +} + +static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct uniphier_gpio_priv *priv = data->chip_data; + u32 mask = BIT(data->hwirq); + u32 val = 0; + + if (type == IRQ_TYPE_EDGE_BOTH) { + val = mask; + type = IRQ_TYPE_EDGE_FALLING; + } + + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val); + /* To enable both edge detection, the noise filter must be enabled. */ + uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val); + + return irq_chip_set_type_parent(data, type); +} + +static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + + *out_hwirq = fwspec->param[0]; + *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct uniphier_gpio_priv *priv = domain->host_data; + struct irq_domain *parent_domain = domain->parent; + struct of_phandle_args parent_irq; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq, parent_hwirq; + unsigned int type, parent_virq; + int ret; + + if (WARN_ON(nr_irqs != 1)) + return -EINVAL; + + ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type); + if (ret) + return ret; + + ret = of_irq_parse_one(priv->chip.parent->of_node, hwirq, &parent_irq); + if (ret) + return ret; + + of_phandle_args_to_fwspec(&parent_irq, &parent_fwspec); + + if (WARN_ON(!parent_domain)) + return -EINVAL; + + if (WARN_ON(parent_domain->fwnode != parent_fwspec.fwnode)) + return -EINVAL; + + parent_hwirq = parent_fwspec.param[0]; + + /* + * of_platform_populate() may allocate IRQ resources statically. + * If the parent hwirq has been already mapped, we need to unmap it + * because hierarchy irqdomain shares one virq among stacked irqchips. + */ + parent_virq = irq_find_mapping(parent_domain, parent_hwirq); + if (parent_virq) { + /* If someone has requested this irq, do not bother it */ + if (irq_has_action(parent_virq)) + return -EBUSY; + irq_dispose_mapping(parent_virq); + } + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &priv->irq_chip, priv); + if (ret) + return ret; + + if (type == IRQ_TYPE_EDGE_BOTH) + parent_fwspec.param[1] = IRQ_TYPE_EDGE_FALLING; + else + parent_fwspec.param[1] = type; + + return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); +} + +static void uniphier_gpio_irq_domain_activate(struct irq_domain *domain, + struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = domain->host_data; + struct gpio_chip *chip = &priv->chip; + + gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); +} + +static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain, + struct irq_data *data) +{ + struct uniphier_gpio_priv *priv = domain->host_data; + struct gpio_chip *chip = &priv->chip; + + gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); +} + +static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = { + .alloc = uniphier_gpio_irq_domain_alloc, + .free = irq_domain_free_irqs_common, + .activate = uniphier_gpio_irq_domain_activate, + .deactivate = uniphier_gpio_irq_domain_deactivate, + .translate = uniphier_gpio_irq_domain_translate, +}; + +static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv) +{ + /* + * Due to the hardware design, the noise filter must be enabled to + * detect both edge interrupts. This filter is intended to remove the + * noise from the irq lines. It does not work for GPIO input, so GPIO + * debounce is not supported. Unfortunately, the filter period is + * shared among all irq lines. Just choose a sensible period here. + */ + writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC); +} + +static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio) +{ + return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK); +} + +static int uniphier_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *parent_np; + struct irq_domain *parent_domain; + struct uniphier_gpio_priv *priv; + struct gpio_chip *chip; + struct irq_chip *irq_chip; + struct resource *regs; + unsigned int nregs; + u32 ngpios; + int ret; + + parent_np = of_irq_find_parent(dev->of_node); + if (!parent_np) + return -ENXIO; + + parent_domain = irq_find_host(parent_np); + of_node_put(parent_np); + if (!parent_domain) + return -EPROBE_DEFER; + + ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios); + if (ret) + return ret; + + nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3; + priv = devm_kzalloc(dev, + sizeof(*priv) + sizeof(priv->saved_vals[0]) * nregs, + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, regs); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + spin_lock_init(&priv->lock); + + chip = &priv->chip; + chip->label = dev_name(dev); + chip->parent = dev; + chip->request = gpiochip_generic_request; + chip->free = gpiochip_generic_free; + chip->get_direction = uniphier_gpio_get_direction; + chip->direction_input = uniphier_gpio_direction_input; + chip->direction_output = uniphier_gpio_direction_output; + chip->get = uniphier_gpio_get; + chip->set = uniphier_gpio_set; + chip->set_multiple = uniphier_gpio_set_multiple; + chip->to_irq = uniphier_gpio_to_irq; + chip->base = -1; + chip->ngpio = ngpios; + + irq_chip = &priv->irq_chip; + irq_chip->name = dev_name(dev); + irq_chip->irq_mask = uniphier_gpio_irq_mask; + irq_chip->irq_unmask = uniphier_gpio_irq_unmask; + irq_chip->irq_eoi = irq_chip_eoi_parent; + irq_chip->irq_set_affinity = irq_chip_set_affinity_parent; + irq_chip->irq_set_type = uniphier_gpio_irq_set_type; + + uniphier_gpio_hw_init(priv); + + ret = devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + priv->domain = irq_domain_create_hierarchy( + parent_domain, 0, + UNIPHIER_GPIO_IRQ_MAX_NUM, + of_node_to_fwnode(dev->of_node), + &uniphier_gpio_irq_domain_ops, priv); + if (!priv->domain) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int uniphier_gpio_remove(struct platform_device *pdev) +{ + struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev); + + irq_domain_remove(priv->domain); + + return 0; +} + +static int __maybe_unused uniphier_gpio_suspend(struct device *dev) +{ + struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); + unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); + u32 *val = priv->saved_vals; + unsigned int reg; + int i; + + for (i = 0; i < nbanks; i++) { + reg = uniphier_gpio_bank_to_reg(i); + + *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); + *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); + } + + *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN); + *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE); + *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); + + return 0; +} + +static int __maybe_unused uniphier_gpio_resume(struct device *dev) +{ + struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); + unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); + const u32 *val = priv->saved_vals; + unsigned int reg; + int i; + + for (i = 0; i < nbanks; i++) { + reg = uniphier_gpio_bank_to_reg(i); + + writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); + writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); + } + + writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN); + writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE); + writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); + + uniphier_gpio_hw_init(priv); + + return 0; +} + +static const struct dev_pm_ops uniphier_gpio_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend, + uniphier_gpio_resume) +}; + +static const struct of_device_id uniphier_gpio_match[] = { + { .compatible = "socionext,uniphier-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_gpio_match); + +static struct platform_driver uniphier_gpio_driver = { + .probe = uniphier_gpio_probe, + .remove = uniphier_gpio_remove, + .driver = { + .name = "uniphier-gpio", + .of_match_table = uniphier_gpio_match, + .pm = &uniphier_gpio_pm_ops, + }, +}; +module_platform_driver(uniphier_gpio_driver); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h new file mode 100644 index 0000000..9f0ad17 --- /dev/null +++ b/include/dt-bindings/gpio/uniphier-gpio.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + */ + +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H +#define _DT_BINDINGS_GPIO_UNIPHIER_H + +#define UNIPHIER_GPIO_LINES_PER_BANK 8 + +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) + +#define UNIPHIER_GPIO_PORT(bank, line) \ + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) + +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) + +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */