From patchwork Thu Sep 14 12:57:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112553 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714491qgf; Thu, 14 Sep 2017 06:00:49 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6n1HI9JoCFpe3+UdQLtO6LXlT67b20+z6TuVOBkUc5sgGucj6zyDEhSRDgF4h5FJzidenh X-Received: by 10.84.235.5 with SMTP id o5mr23711706plk.4.1505394049803; Thu, 14 Sep 2017 06:00:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394049; cv=none; d=google.com; s=arc-20160816; b=pRGemYwSy97sPNSUao1TDZff9I36Fr87fM0APh4W8aay/dqpikQ++wjkgL7TcFNPbx Xop9yR0qduB/9m8hJlps5pTMFDlt6h7o89KvP+YGqwG+6uaaxoNP4dcVLyzwQ8QS6GCe 3kFo9osfuYbWfV3b0jDoi1FwiCORX1BzPquPn+j002I0LieENWLWVa9rSGoPIVS1bQ0z PeqVl2NzCe209A4ctGRRzmO0CERi5tEI6JWNFljM6BwBlWJBICgSc0o9BeRxT0uRWCI5 ylNuUWsgHffqZBu/UXfHQ+SRPurt2nm8YF0/292Eu/cCYLejLcDk1peGheylHCAukQFx 2OVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=KcPIIRVmD3XFZzUcyZElBtCMmO5k0QOTeajdx6b7wPk=; b=LlRa3mKn1LJbU0j13jYYo3EJREt0ro6vu2xmP4LqTgfN0oxxTkieZI8TqL23vghlss SOaELFiyRVHzwD6K57FeCUXADt9FyZaDnpmlRXIcvrsbFYdTq6FWzE4LloGoJqgFJh+P 505Sv2bhhJZahd3oJgxBsXIYEj2Y2/flCk865RytRuzsvPKX50iAennjC5fzuRBSqjxI +3ws8qYic4yS5mVRLdc0I4IJ0m1opYLGCVArTnDixmLObvemmu4hIdY0z5DwEkwCKwnq SOS1BT9I4KQsDCl/VauyWlhNIX0g0I9gaSJE5rnLNeK4u/cYOPeE9zuB9ABv53/5LaNy hWhg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.00.49; Thu, 14 Sep 2017 06:00:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751131AbdINNAs (ORCPT + 7 others); Thu, 14 Sep 2017 09:00:48 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6478 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751133AbdINNAr (ORCPT ); Thu, 14 Sep 2017 09:00:47 -0400 Received: from 172.30.72.58 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHF34305; Thu, 14 Sep 2017 21:00:44 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:35 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801 Date: Thu, 14 Sep 2017 13:57:52 +0100 Message-ID: <20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59BA7D7C.011C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 314c5d550487ad0133a819442a53b2b4 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: John Garry The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMU mappings for MSI transactions. On these platforms, GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch adds a SMMUv3 binding to flag that the SMMU breaks msi translation at ITS. Also, the arm64 silicon errata is updated with this same erratum. Signed-off-by: John Garry Signed-off-by: Shameer Kolothum --- Documentation/arm64/silicon-errata.txt | 1 + Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 3 +++ 2 files changed, 4 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 66e8ce1..02816b1 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -70,6 +70,7 @@ stable kernels. | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | | Hisilicon | Hip0{6,7} | #161010701 | N/A | +| Hisilicon | Hip0{6,7} | #161010801 | N/A | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index c9abbf3..1f5f7f9 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -55,6 +55,9 @@ the PCIe specification. - hisilicon,broken-prefetch-cmd : Avoid sending CMD_PREFETCH_* commands to the SMMU. +- hisilicon,broken-untranslated-msi + : Reserve ITS HW region to avoid translating msi. + - cavium,cn9900-broken-page1-regspace : Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. From patchwork Thu Sep 14 12:57:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112554 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714618qgf; Thu, 14 Sep 2017 06:00:54 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6yflO4dkQgehswHvs7+19JKToy+ooJX5818lcdtz0mNDZ66kjC2HCc7wU+QMSDWYPhXPkc X-Received: by 10.84.248.13 with SMTP id p13mr24057702pll.447.1505394054492; Thu, 14 Sep 2017 06:00:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394054; cv=none; d=google.com; s=arc-20160816; b=hZA5k2G/bbrXHN8sb5ZmX45Yf9GfEOJuknIpjOUgmIaKlIyFrbmVlgHFeeVEmLEfgs lYrEln4Z846NqDj+qrYUJHA97qT6NWehLAgeB/dWwhs/uB2iwgFvpZTPbESzJmggV6ps D4Kn/sDOh6wU86vp2IA0rEobQqzUkRtTjULiau5Jb4Rj1bSqpS/rY1r48NTWg7eETOAS 3a7HJaLQzJKAJru5h4SmXegUXbVDF6yDlGzbRk5sAEYL4hdvCzeEugvkq8UMQDF/zAU9 3egHXH/qLLd9pMkySxGqVS2HcJGUp0mMute7YjfiIvkHBOZRHJsWIWafggyPo/UONqSO FnjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=jb9OU9Sa2ukPX1crAvndYquCFa/jFms+WYntOypByj0=; b=bM6vMaCmkHMxdOHRha0XfJDyELms1vjDZdsYakzxvODwVNjxc4AKeNz/xuTX4hF8DE 8QfIpwbTxWm+vR18m8zbDv5NRd1+T7GDJ5VrC9hfkG35IzQsvxBentREAlWXXvQ84k5p IelCLXdJ68vzEHsFvOGtjT3od7Wi/Tt0b6yMu0aIs9v540xkpKHskx6nSyw3ner0mYpv jJgzGspNsPRO6bbcx0YMRNTf2r399F7R8h3ZXQ/t4+WPadNoHxK21VK3CrSyWa85O1lX 767ZMhcQVZfabrbrPTw86TsDvlBxt1L33wwmHU7PV7QOw4honCltK7r7NlHCUCIZPWFA P2TA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.00.54; Thu, 14 Sep 2017 06:00:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751328AbdINNAx (ORCPT + 7 others); Thu, 14 Sep 2017 09:00:53 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:6059 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751318AbdINNAw (ORCPT ); Thu, 14 Sep 2017 09:00:52 -0400 Received: from 172.30.72.59 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHH33805; Thu, 14 Sep 2017 21:00:49 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:39 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 2/5] ACPI/IORT: Add msi address regions reservation helper Date: Thu, 14 Sep 2017 13:57:53 +0100 Message-ID: <20170914125756.14836-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59BA7D81.00DE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8e9c2f138bec784de46f6c0aa625cb03 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the msi parent - through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. Signed-off-by: Shameer Kolothum [lorenzo.pieralisi@arm.com: updated commit log/added comments] Signed-off-by: Lorenzo Pieralisi --- drivers/acpi/arm64/iort.c | 96 ++++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 101 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index a3215ee..b2e9150 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -39,6 +39,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -136,14 +137,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -153,6 +156,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -481,6 +485,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + bool match = false; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + match = true; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return match ? 0 : -ENODEV; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -639,6 +661,72 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) return err; } + +/** + * iort_iommu_msi_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success (0 if no associated msi + * regions), appropriate error value otherwise. The ITS regions + * associated with the device are the msi reserved regions. + */ +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *node, *its_node = NULL; + int i, resv = 0; + + node = iort_find_dev_node(dev); + if (!node) + return -ENODEV; + + /* + * Current logic to reserve ITS regions relies on HW topologies + * where a given PCI or named component maps its IDs to only one + * ITS group; if a PCI or named component can map its IDs to + * different ITS groups through IORT mappings this function has + * to be reworked to ensure we reserve regions for all ITS groups + * a given PCI or named component may map IDs to. + */ + if (dev_is_pci(dev)) { + u32 rid; + + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); + its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE); + } else { + for (i = 0; i < node->mapping_count; i++) { + its_node = iort_node_map_platform_id(node, NULL, + IORT_MSI_TYPE, i); + if (its_node) + break; + } + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base, SZ_128K, prot, + IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return (resv == its->its_count) ? resv : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) @@ -646,6 +734,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif static const struct iommu_ops *iort_iommu_xlate(struct device *dev, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 284738a..cd41780 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1951,7 +1951,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 8379d40..586fb95 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -38,6 +39,7 @@ /* IOMMU interface */ void iort_set_dma_mask(struct device *dev); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id) @@ -51,6 +53,9 @@ static inline void iort_set_dma_mask(struct device *dev) { } static inline const struct iommu_ops *iort_iommu_configure(struct device *dev) { return NULL; } +static inline +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */