From patchwork Thu Sep 14 12:57:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112556 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714816qgf; Thu, 14 Sep 2017 06:01:01 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6NaPyibOHj9nsf+7WAR+OSWD/dsxQl12ZkT/0gLpLQcM8jNvRFTjF61KOgCjOVXHpuweJ1 X-Received: by 10.98.14.213 with SMTP id 82mr21291584pfo.320.1505394061211; Thu, 14 Sep 2017 06:01:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394061; cv=none; d=google.com; s=arc-20160816; b=ugFC+9LZybf6MXuWuiy86WD90DObOtq5jzESyfhrF8ZZ0Vsqj9WD7afvyevzPe/Q5U Ow+OsXtiJ+L+lj1oonEJuOfJD4NejTmKzd0Qj+ztyb/McEAlX8o0WqC/EWaXuuGZuVzk CrGMTuUgpQLqJIxxMDwa+pBID7cd3Ey8O7cW5B+OdcfUdc1BEDldv6iG2HrbtrZILrmh bvczi987Pbgum/SU3rsx1XwewKrFRfpiRhUH6keVF4zFiPzzhLAHk4GltVd7jpE97a8L auaF/JfpEpR9TEkKQ4mYhmyPLXxuEEUqv3NbcMJ1yMXGAcYJ+83gWL2UWc9l8TsCNyoo dRpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=MHdCOhdk71Roxd/yglkBE1k5F56IYPucJbseVzdpbmM=; b=NMiMtUrLtpVjmeAbcCrK1l40d0wIr79xGbU7S0d3WhmyFvCIuR7WUf0aTvRY5vfGDQ TAYAudx7ys3Fo8jDAsiyQ0zbEObaE1qNaziwjnbwuC1OeMvhrqRcqzMAXr4Pznj5FPQq xiByPmyTKrzdMxjROaoCFxt9zN48+nsWO84hJsIrrNjh+PBGv2cR253RubO/VVJW2fRO IAch7O8O9YoWKqxgzHyEU58STG0JwjM4J7NvE0JPpZzKYSyMfHfAka+1o4et/2VeV0ZR Ta5TB25K27IWghegvK94Mqo5QygyF3OH8jfxU1SvFTgUadqMCSSpgYldNwgxwtH80L8h qj4Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.00.59; Thu, 14 Sep 2017 06:01:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751365AbdINNA5 (ORCPT + 6 others); Thu, 14 Sep 2017 09:00:57 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6480 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751335AbdINNA4 (ORCPT ); Thu, 14 Sep 2017 09:00:56 -0400 Received: from 172.30.72.59 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHF34348; Thu, 14 Sep 2017 21:00:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:43 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 3/5] iommu/of: Add msi address regions reservation helper Date: Thu, 14 Sep 2017 13:57:54 +0100 Message-ID: <20170914125756.14836-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59BA7D86.0122, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 8efd3143354b48dbe223742ebc3bebbe Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: John Garry On some platforms msi-controller address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves msi address regions through device tree msi mapping, so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. Signed-off-by: John Garry Signed-off-by: Shameer Kolothum --- drivers/iommu/of_iommu.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/of_iommu.h | 10 ++++ 2 files changed, 127 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 8cb6082..f2d1a76 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -246,6 +247,122 @@ const struct iommu_ops *of_iommu_configure(struct device *dev, return ops; } +/** + * of_iommu_msi_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success (0 if no associated + * msi parent), appropriate error value otherwise. + */ +int of_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + struct device_node *np; + struct resource res; + int i, resv = 0, mappings = 0; + + if (dev_is_pci(dev)) { + struct device *dma_dev, *bridge; + struct of_phandle_args iommu_spec; + struct pci_dev *pdev = to_pci_dev(dev); + int err, count; + u32 rid, map_mask; + const __be32 *msi_map; + + bridge = pci_get_host_bridge_device(pdev); + dma_dev = bridge->parent; + pci_put_host_bridge_device(bridge); + + if (!dma_dev->of_node) + return -ENODEV; + + iommu_spec.args_count = 1; + np = iommu_spec.np = dma_dev->of_node; + pci_for_each_dma_alias(pdev, __get_pci_rid, &iommu_spec); + + rid = iommu_spec.args[0]; + if (!of_property_read_u32(np, "msi-map-mask", &map_mask)) + rid &= map_mask; + + msi_map = of_get_property(np, "msi-map", NULL); + if (!msi_map) + return -ENODEV; + + mappings = of_count_phandle_with_args(np, "msi-map", NULL) / 4; + + for (i = 0, count = mappings; i < count; i++, msi_map += 4) { + struct device_node *msi_node; + u32 rid_base, rid_len, phandle; + + rid_base = be32_to_cpup(msi_map + 0); + phandle = be32_to_cpup(msi_map + 1); + rid_len = be32_to_cpup(msi_map + 3); + + /* check rid is within range */ + if (rid < rid_base || rid >= rid_base + rid_len) { + mappings--; + continue; + } + + msi_node = of_find_node_by_phandle(phandle); + if (!msi_node) + return -ENODEV; + + err = of_address_to_resource(msi_node, 0, &res); + of_node_put(msi_node); + if (err) + return err; + + region = iommu_alloc_resv_region(res.start, + resource_size(&res), + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } else if (dev->of_node) { + struct device_node *msi_np; + int index = 0; + int tuples; + + np = dev->of_node; + + tuples = of_count_phandle_with_args(np, "msi-parent", NULL); + + while (index < tuples) { + int msi_cells = 0; + int err; + + msi_np = of_parse_phandle(np, "msi-parent", index); + if (!msi_np) + return -ENODEV; + + of_property_read_u32(msi_np, "#msi-cells", &msi_cells); + + err = of_address_to_resource(msi_np, 0, &res); + of_node_put(msi_np); + if (err) + return err; + + mappings++; + + region = iommu_alloc_resv_region(res.start, + resource_size(&res), + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + index += 1 + msi_cells; + } + } + + return (resv == mappings) ? resv : -ENODEV; +} + static int __init of_iommu_init(void) { struct device_node *np; diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h index 13394ac..9267772 100644 --- a/include/linux/of_iommu.h +++ b/include/linux/of_iommu.h @@ -14,6 +14,9 @@ extern int of_get_dma_window(struct device_node *dn, const char *prefix, extern const struct iommu_ops *of_iommu_configure(struct device *dev, struct device_node *master_np); +extern int of_iommu_msi_get_resv_regions(struct device *dev, + struct list_head *head); + #else static inline int of_get_dma_window(struct device_node *dn, const char *prefix, @@ -29,6 +32,13 @@ static inline const struct iommu_ops *of_iommu_configure(struct device *dev, return NULL; } +static int of_iommu_msi_get_resv_regions(struct device *dev, + struct list_head *head) +{ + return -ENODEV; +} + + #endif /* CONFIG_OF_IOMMU */ extern struct of_device_id __iommu_of_table; From patchwork Thu Sep 14 12:57:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112555 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714732qgf; Thu, 14 Sep 2017 06:00:59 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4d1MK3mS2jQ9dKsWsGqqY7+k2tzOYYs1RqW5uZRtVPAOXqwU8xOGBSR8OgBfbH+SxrKrHg X-Received: by 10.98.158.26 with SMTP id s26mr20710610pfd.284.1505394058965; Thu, 14 Sep 2017 06:00:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394058; cv=none; d=google.com; s=arc-20160816; b=rFKf+W1L2zdMT9JdMxzvNQKRsz+Ap7FJbSWGbgLi80peOaOAItWqTydClXy2O7RUDx oM02NpowKw/Z7EYg+gSecYB9eH5beRNLo9cQkOG2+WMZkQEJmBrnqr3t0D0JR/C9ZTG1 hvDbK9shrDawkNkKJ/eX1tENEUtOxcfTvi8lguOBA+J8R/R1OTUPm2eelSO0/dHcqpdm 6CXtnHGXaW9HQHsn2YCkMpMKXIEGYBp+K1VQQiu4ridS4gc+GLJTSx9eeibgiI96aJ0X 351myvQJ7RAUQV0Qnx5AZfSqeApecwnc0BZW984jPwuxAgJIMF+GZzNhlnfLJqEbLEuW YoyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Sn/OZrn9QWe9KSs2wWcRA5lEvPUrdMrXYxpPPAmOK4A=; b=dR+icTTLpapjXwY/P6VxxYSvD41KCfQrWh17a5EG3fzwj2ZhRlAwA+gsoP4ap2pZA8 9Qv9yKiLZwFkVIetLoLvAzWhimXhoDXA+pMIZSTSPM5u0dibh3cAc8aA05aitTLD2zpr aWCMCBuA8M+ZOSNiC4+K4uzW4ZAPZ0lOSbvtz5p9SnPJIyIpStR9lfOlBIVguXeLmTsF exfIjm6H0yuf9igmMgh81NU8Y3dEIrRqoGFcY8nhLYsUExJMPEQlShCh/EVnZ3wxe5jR drONqSCiVyoR0qlWEZbG7oyQbEcsoY9SUA4WpmsrLiMgpWjp61kZ0TDOjjfKBB9bXYOV JvpQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.00.58; Thu, 14 Sep 2017 06:00:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751352AbdINNA5 (ORCPT + 6 others); Thu, 14 Sep 2017 09:00:57 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6479 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751318AbdINNA4 (ORCPT ); Thu, 14 Sep 2017 09:00:56 -0400 Received: from 172.30.72.59 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHF34346; Thu, 14 Sep 2017 21:00:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:47 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 4/5] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Thu, 14 Sep 2017 13:57:55 +0100 Message-ID: <20170914125756.14836-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.59BA7D86.0116, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ad2e8d7bb81a8ce18279d6c843ef64eb Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IOMMU drivers can use this to implement their .get_resv_regions callback for HW MSI specific reservations(e.g. ARM GICv3 ITS MSI region). Signed-off-by: Shameer Kolothum [John: added DT support] Signed-off-by: John Garry --- drivers/iommu/dma-iommu.c | 19 +++++++++++++++++++ include/linux/dma-iommu.h | 7 +++++++ 2 files changed, 26 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9d1cebe..f8709a2 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -19,6 +19,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -198,6 +200,23 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(iommu_dma_get_resv_regions); +/** + * iommu_dma_get_msi_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * IOMMU drivers can use this to implement their .get_resv_regions + * callback for HW MSI specific reservations. + */ +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + if (is_of_node(dev->iommu_fwspec->iommu_fwnode)) + return of_iommu_msi_get_resv_regions(dev, list); + + return iort_iommu_msi_get_resv_regions(dev, list); +} +EXPORT_SYMBOL(iommu_dma_get_msi_resv_regions); + static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, phys_addr_t start, phys_addr_t end) { diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h index 92f2083..6062ef0 100644 --- a/include/linux/dma-iommu.h +++ b/include/linux/dma-iommu.h @@ -74,6 +74,8 @@ void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg); void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list); + #else struct iommu_domain; @@ -107,6 +109,11 @@ static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_he { } +static inline int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + return -ENODEV; +} + #endif /* CONFIG_IOMMU_DMA */ #endif /* __KERNEL__ */ #endif /* __DMA_IOMMU_H */ From patchwork Thu Sep 14 12:57:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112557 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714885qgf; Thu, 14 Sep 2017 06:01:04 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5yh1tCwdkwPDsq/pHmGXbsq7lri/1KibYq2juhYohZFVe3JBBWB5y5HdE2JrYHBX+tpcQP X-Received: by 10.98.196.206 with SMTP id h75mr20789810pfk.35.1505394063828; Thu, 14 Sep 2017 06:01:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394063; cv=none; d=google.com; s=arc-20160816; b=EYrpZ9oL/5CUBvqiUCLCW2E26Xy5E6EKAHC8MPo+RBkJC2nu5za3BiZq5U2XjMdJg4 X1gwWd/tOlg/wRDriWCRWEWvYNZ1rDYusR/r+Z80yswDz9LkTS8hYLXDiidb2XEDf8e3 2RiqbXuO8gV3GtNWkOJRAY16tRnqJnvqScatjuiazyzeRPpECs0ybE44cByJUxF9hMXP KoClXiJBmFWwNDbnuojjk2G5ahMYBHK2hmt36CNees9bSDKzGWvtHAKJG3nSSAWjrNCE sXU/39QdtTLA6R4HU84XT42q4rq3RUBE6DvZ0RVtieeewKheHwgCD/oEdR5JnHwyam7h MJBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=OFLTg5gKWDtX4DwR9iSliarC+D21FTenPPO3Mda24XE=; b=shUBuAjX4dveXv9EZRJaP9igCkRhyDCEWSq+yw8jk+UV7xn/ZUkflQTU7Xv6C1pHpD gfUGL3XAlF5Qm7zqVaWH6igmaYSon64a48+XPyrc+GfTExDTMOl/gDkBb10C3WZbEF0L Fn4k23bWFhLJu83BDVej4yLdc50y4rkMTpRNA72sBarD/+/LW2vEyujAq1L76HRdqYkC Bov+Pi/xNCLdq++fKKc5C2rF+oXkxrWGwIywobG+UXnfRTxZxuXFDo77VTf/bNpTDiw7 VdUnaF/B9t29+RhsEhU47p4JLI9zXR5Gza6zp2+h81fl39UsShULEzqrHY18JvVQaPLl qXWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.01.03; Thu, 14 Sep 2017 06:01:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751335AbdINNBC (ORCPT + 6 others); Thu, 14 Sep 2017 09:01:02 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6481 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751370AbdINNBB (ORCPT ); Thu, 14 Sep 2017 09:01:01 -0400 Received: from 172.30.72.59 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHF34364; Thu, 14 Sep 2017 21:00:59 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:52 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 5/5] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Thu, 14 Sep 2017 13:57:56 +0100 Message-ID: <20170914125756.14836-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> References: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59BA7D8B.010C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: a619a19319a561b74f86834c14b34d46 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum [John: add DT support] Signed-off-by: John Garry --- drivers/iommu/arm-smmu-v3.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 568c400..8503f4d 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -608,6 +608,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -674,6 +675,7 @@ struct arm_smmu_option_prop { static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, + { ARM_SMMU_OPT_RESV_HW_MSI, "hisilicon,broken-untranslated-msi" }, { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"}, { 0, NULL}, }; @@ -1934,14 +1936,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2684,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; }