From patchwork Thu Sep 14 17:52:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112589 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1046236qgf; Thu, 14 Sep 2017 10:53:02 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBFIxDTD+PsvgY/TvyjkzLnQehcixsAdQCUE+OZeAQFcK+FBI93ihc8a6k1i8i80gAc6BiS X-Received: by 10.55.52.207 with SMTP id b198mr4052877qka.60.1505411581954; Thu, 14 Sep 2017 10:53:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411581; cv=none; d=google.com; s=arc-20160816; b=vzxhWYouYF91WptIsdTywirjb0Yx0nssEuIuPkTnQwCGkUR99JEqFE5XkUcHY4fJ62 EvVqYDmgu6TxpCukWJYkKU2fYvSvuNo8Sy5QrDICA7yAKoesJ8UiO51xS2E4hR1LIuUd LdLBpI8xZCI+gRPb4DavzlcS+ndrosIe8QSf76cVyaRksUTxLQMOAfZoVUghIOUGGLxI O6cTCtzguqGe7Zmdo4glKNsDbQHIFZr1yVLyN282HrZsgk1lEsQUkFyR4NRKWfb9Uef0 nu6VwODTMVAGh1jSWfgPMSBznf5YCmouWUemE2bpueLx9ZWjKVYaZmtBO/R0gEvngYPj dFjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=OKarblD3djNpkPXYNLB65TFYL0Q4Tdr75j7OHoZ8gEA=; b=VG6QjiVf4/QlnqN1QEqmZHq4MqoTnslCzu+n3wFuZB9mYpU6FfF7z8LzwmaRGzM7Sq /GljkVwpZ3B66pnXcZk0jcSoPp4y80gD1LP8S7AaMJ/L778YfmfmkdzzZl0iSPGVezTQ XJqa9UzC6/8Zra8magmDGsqWUSaNDAGIV4IaJ1sHNQoRKMQ006dxUQzv3LzzOWIai5Ji 6MeRx6QOX5y5c13VFBhYJkSSPkpS1uvTPd3pIEjRCKLJ7GW1uNrmaehSAFeykZkeiM8R PAojy6e3A7d5cd3y03WxpNAJAgqhFJgAS2TGPl67xOzhenA12WBkJw1Bxxvu0Rs6H6HC sIbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26..5a1f957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -81,8 +81,11 @@ * accessed via env->registerfield[env->v7m.secure] (whether the security * extension is implemented or not). */ -#define M_REG_NS 0 -#define M_REG_S 1 +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 @@ -433,19 +436,19 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t other_ss_msp; uint32_t other_ss_psp; - uint32_t vecbase[2]; - uint32_t basepri[2]; - uint32_t control[2]; - uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr[2]; /* Configurable Fault Status */ + uint32_t vecbase[M_REG_NUM_BANKS]; + uint32_t basepri[M_REG_NUM_BANKS]; + uint32_t control[M_REG_NUM_BANKS]; + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar[2]; /* MemManage Fault Address */ + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl[2]; /* MPU_CTRL */ + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ int exception; - uint32_t primask[2]; - uint32_t faultmask[2]; + uint32_t primask[M_REG_NUM_BANKS]; + uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; @@ -546,7 +549,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr[2]; + uint32_t rnr[M_REG_NUM_BANKS]; } pmsav7; /* PMSAv8 MPU */ @@ -556,10 +559,10 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar[2]; - uint32_t *rlar[2]; - uint32_t mair0[2]; - uint32_t mair1[2]; + uint32_t *rbar[M_REG_NUM_BANKS]; + uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t mair0[M_REG_NUM_BANKS]; + uint32_t mair1[M_REG_NUM_BANKS]; } pmsav8; void *nvic; From patchwork Thu Sep 14 17:52:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112607 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1067375qgf; Thu, 14 Sep 2017 11:11:32 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAgXFYK6h9YSNRplh/PETAfxwsap3EG3s1gheTqpmAZIVbpVzLtmoAp4ScMfbb6n8549Jc2 X-Received: by 10.200.41.143 with SMTP id 15mr24257252qts.56.1505412692033; Thu, 14 Sep 2017 11:11:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412692; cv=none; d=google.com; s=arc-20160816; b=HV3UXpY37pX4pvkl0WxtTCY8MX3xWOXtIbQweQZ82J/zHw2AEM02r90VTIHdcGeIu4 NuqsufLYbk3lBFghWSO5h/i3f5cvWgjgLHJKW9W0TxORRAneyJ3RtpP4LwdkfA2A5mEo ruWShYiMNZy0hgrlrr9iJ4yD6zFVpJ7PMjcm0CsRhlWTEEdSNviHJ4MrTjPijyVlyP/h IKig6SB9tYPJRQJrx+EtU1RHM8Stqh6q2oKZHnIpwT8GOt7tEbJ3UTjVAXC7pIQei+bs 5ARpIl85vkk0Oy7efrxMoIuQagK/qniPYol18gvFmGK6nOiek3kERQf86nBDa5+ROoiX w6UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=BKWZjFruR27NZ33MwAXeMwVMmCJbyQSwL+I8VWhQYgg=; b=T2M/Pnl4X5aoQG/1bQ/eeZHhZm2yimnQFC0RsMTadQuSoVAFYOdSwro8NGNq0AA/ic PdQFdcSVGLFAG0AjALeLUK/k10t/ntxSJOYO6bNGdhLUDiOTRzSI1Npn48rcv3pVILJB MfSPlv5O37X9w1w4kAfjl9/Zt3csDqE/pnH0rncxzj5NZcn9erHpYjkEOYAGqJy/3nFX sf4RyLfDj42uZ4RWk80B6JXRXX7LaT8m3yI/YBB0Qy8yEgluS5OJwiD/dnV63nEch2qs LoKrQBi7iJEKLfeQKm33eseekkxtW7MF3GX99FaCSSCPixAcIDMBYhIBI4UmmBvR83P1 FOHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 81si18177339qkw.22.2017.09.14.11.11.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:11:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYbp-0004SU-Vs for patch@linaro.org; Thu, 14 Sep 2017 14:11:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088Z-GZ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJb-00083Z-Do for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJb-0007x0-5h for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJN-0005nI-TW for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:37 +0100 Message-Id: <1505411573-27848-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/18] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 6 ++++++ target/arm/helper.c | 2 ++ target/arm/op_helper.c | 2 +- 4 files changed, 19 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/target/arm/internals.h b/target/arm/internals.h index 5d7f24c..a315354 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -444,6 +444,16 @@ void arm_handle_psci_call(ARMCPU *cpu); #endif /** + * arm_clear_exclusive: clear the exclusive monitor + * @env: CPU env + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. + */ +static inline void arm_clear_exclusive(CPUARMState *env) +{ + env->exclusive_addr = -1; +} + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1acce3..412e94c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,6 +235,12 @@ static void arm_cpu_reset(CPUState *s) env->regs[15] = 0xFFFF0000; } + /* M profile requires that reset clears the exclusive monitor; + * A profile does not, but clearing it makes more sense than having it + * set with an exclusive access on address zero. + */ + arm_clear_exclusive(env); + env->vfp.xregs[ARM_VFP_FPEXC] = 0; #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 329e517..668e367 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6175,6 +6175,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) armv7m_nvic_acknowledge_irq(env->nvic); switch_v7m_sp(env, 0); + arm_clear_exclusive(env); /* Clear IT bits */ env->condexec_bits = 0; env->regs[14] = lr; @@ -6354,6 +6355,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } /* Otherwise, we have a successful exception exit. */ + arm_clear_exclusive(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d1bca46..6a60464 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1022,7 +1022,7 @@ void HELPER(exception_return)(CPUARMState *env) aarch64_save_sp(env, cur_el); - env->exclusive_addr = -1; + arm_clear_exclusive(env); /* We must squash the PSTATE.SS bit to zero unless both of the * following hold: From patchwork Thu Sep 14 17:52:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112606 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1065134qgf; Thu, 14 Sep 2017 11:09:41 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBDojZFHqPlZutp510aaOTwZtags7dmqcCgv678tIDJ06v/4zAJSW/i6rpD2COb75/vr6g1 X-Received: by 10.55.19.75 with SMTP id d72mr3723701qkh.266.1505412581193; Thu, 14 Sep 2017 11:09:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412581; cv=none; d=google.com; s=arc-20160816; b=LGzdrsvnXsr+drPIFP+08DfIfVq2gdpDEFBecnrd4fTwRouWhswgAKoLOIBcv5ip/F I71OYKToKqFICF3D7X16qRq5svutIbaS64z4wbmTORSEp2T8tIstHBfGqVxiYxh3mxTN 0hgHtcVxPosfi/0YdmxpVCYwfw4RM5PVjpwQlL82ZIqh091YaJ5/BYEKVOq92Qi3FZxj liIMq6T1bQH7HlStva0ozCKviRrzKZvGqzlOvgKBADDTaV1naKBjxTwPABJ99WkOVWtH kvFSl/PTjPW+NQ4AZL6x/hziUxn29juoxXKO03Vc4fciagPhn5eeFI0SpwiOVFgY63K+ IGPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=vFVe2MMsNepK8ITOherF7VyG+AUjHNsGimes9TMrIc0=; b=t/1JnAjKtTkx+zrC7twPtnPrGkFxsIepVdlihl3Lq4TqnNsxlYhJ/4PuC/h0dC22JX HRbE9gPWACYBG6XRy9kVXdnvfJOKKLbwzGD3vW731BC+O7SPWjB4ovWEBzYS13+vq7Br H3rq2gAg9zMgtmn/JFL1WMr50dVQcQzN+jEged/P1XjfJUdcX5Duo2SNYs81zgqK8zjo XJRbfW1Oy0zzJeOqp9DttSAuI0SrHSbaglTgqtvzPyd1Z89z08xuBzqlZq951hJLx2GC XI1h5v88wznqhJJFPQXYbbbgkeYCoCBhxWLfqp0uMJYqn7dSC6k7GTH/d+S8Xq8Zy0gl 067A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id u58si8109081qta.40.2017.09.14.11.09.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:09:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYa3-0003Hu-6Q for patch@linaro.org; Thu, 14 Sep 2017 14:09:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088P-9P for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJb-00083i-EE for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJb-0007iP-5b for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJO-0005o6-O3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:38 +0100 Message-Id: <1505411573-27848-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/18] target/arm: Get PRECISERR and IBUSERR the right way round X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For a bus fault, the M profile BFSR bit PRECISERR means a bus fault on a data access, and IBUSERR means a bus fault on an instruction access. We had these the wrong way around; fix this. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 1505137930-13255-4-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 668e367..1741e0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6430,15 +6430,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_PRECISERR_MASK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); break; case EXCP_DATA_ABORT: env->v7m.cfsr[M_REG_NS] |= - (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); env->v7m.bfar = env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, - "...with CFSR.IBUSERR and BFAR 0x%x\n", + "...with CFSR.PRECISERR and BFAR 0x%x\n", env->v7m.bfar); break; } From patchwork Thu Sep 14 17:52:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112595 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1050935qgf; Thu, 14 Sep 2017 10:57:49 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAB+73ktEz9V5WvZu+3Ur2JpjlVXcqONVlkKD6mk4Nj2EtzaUq/U169+vybkcQFcW876wUc X-Received: by 10.55.52.135 with SMTP id b129mr4002082qka.308.1505411869794; Thu, 14 Sep 2017 10:57:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411869; cv=none; d=google.com; s=arc-20160816; b=GTw/y97vz1L/QjLWlrGWpnKeJYf6xiCOFlqYGI//5bbAeWTvSr5RVotOcjqzWNmBc4 Xfmrq2esrD8kPsHrr2+HGmqZ8pK5udXSDnoVY1NdYeshHmdCAyC4tIFRH6hF7F2gWxPh SInhj7kU1Fk5ek98gS0BC9hHOJ+GYrTh45PopSM3yUmn6tk3Nb9H9RSjJpfrgEUY+zKO Mug9gzX1WeZhOr6FMJ445OQpesVSjruuwXuU6WRT3qDz4zakzNfhmKpmzD7s91yKHS+d BiWrtCMzERyI0beJYf/8HjMoMNzjkU/ok4iOvrajPKAoGRpnEWEFO2RQlCC3VCz+022K az1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=WfpHH9EjnVUK5Qo8FfxPoGh4iV34US+lBjxGl9LDCcA=; b=FbJjE75XUM5F+181/78bkkDHlqFe28JmBhG219Uj/7uc4xUi+lh70zO3Z8Z5bzsDCG lpawV9q39kt3LuGNIrkIHmLGhpdHtzGt8d+xwDIW/tSKzLO/UwcDBzpmH0eKyucW4yzb yhzrlJicIgrjKLaV8LmKy4YBBgoxrfFBNf7zGsrBdqRr8jLb00YNFg1mCyP80NDlRffR 6BX83p3aTP4EdHgJ8gkNyog5TebL18PEpFkpbUq2YL2/G9wAzOPCbumZXuO521qDViB9 vYaVDM9G0btC5NU64KKWJJMqQgxkAgRI37EOIjuH+5r1Dz1b0gwMznjfcazrjy8SnSex b7Ew== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g9si9335346qtf.204.2017.09.14.10.57.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 10:57:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49198 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYOZ-0004mc-Nu for patch@linaro.org; Thu, 14 Sep 2017 13:57:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46581) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088B-1L for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00082M-U3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007yZ-MW for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJP-0005oX-CQ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:39 +0100 Message-Id: <1505411573-27848-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/18] nvic: Don't apply group priority mask to negative priorities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In several places we were unconditionally applying the nvic_gprio_mask() to a priority value. This is incorrect if the priority is one of the fixed negative priority values (for NMI and HardFault), so don't do it. This bug would have caused both NMI and HardFault to be considered as the same priority and so NMI wouldn't correctly preempt HardFault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1505137930-13255-5-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1fecfd6..d3e2056 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -152,8 +152,12 @@ static void nvic_recompute_state(NVICState *s) } } + if (active_prio > 0) { + active_prio &= nvic_gprio_mask(s); + } + s->vectpending = pend_irq; - s->exception_prio = active_prio & nvic_gprio_mask(s); + s->exception_prio = active_prio; trace_nvic_recompute_state(s->vectpending, s->exception_prio); } @@ -329,7 +333,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque) assert(vec->enabled); assert(vec->pending); - pendgroupprio = vec->prio & nvic_gprio_mask(s); + pendgroupprio = vec->prio; + if (pendgroupprio > 0) { + pendgroupprio &= nvic_gprio_mask(s); + } assert(pendgroupprio < running); trace_nvic_acknowledge_irq(pending, vec->prio); From patchwork Thu Sep 14 17:52:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112599 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1054266qgf; Thu, 14 Sep 2017 11:00:48 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDNkjSThjKZnE1rd82PLVWeaZ7+iCi2FYwPSBTNPVcppJn3Wz96yIpdnyGCKP9Lkn5CVro5 X-Received: by 10.55.109.66 with SMTP id i63mr3654993qkc.19.1505412048486; Thu, 14 Sep 2017 11:00:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412048; cv=none; d=google.com; s=arc-20160816; b=VV6t9OAvlGG9irV+sCpwSwpWuZGYOzJ0ZAdKvEL8RgyKh0tQ3xz70+uQwMUdclO4kY C9YeeVcX4Z5oRR4V2GwGycPENDP9p+3oz++xO+b/5P5qvDp/G1/pgUshHXj/DValH8wv jgmGj+vAIZCL9Ie9eslLx6h12X46IRTbT5+mUwE867xzCBmYPhLY3M/4mBHUqUvJ70DT y3VeSLFRYW76da8qCO1F0mGh9gvzP8ezQUJNrMs/TksWSFKSNJRIe+h4kl6rESlev2u8 gwlYdPnFrLmmrnkx7/q6yJ0GcYuuCURTCbs0LoaH1FuxvR8SnLO5VIVM3QYZGbRKwVrr Xdwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=FZag1dnxQeKSVBlCOBUJiIAB3QC09+TIrKpoMrHQdw4=; b=AKUjAmdmC/Wjv0cIam1U5orxHnp7XeHxvx71sQXPXpbn79UXYf+ME+rV+RBsQJjj2X +0MnD7Ct2T0Z0mLDqgdxKN5uDoom8kEasHUzl7XqxwsV9ewoDQzuVc4pKNzJkxQsgwzK twovmrDLu5XN7h/u/7gNd1sF7SFq0J0HuPntGJuogW8rtOZQHeonRd53tlhiauYiuKTe TUsy1weQzr/IwG/tPwa2+ktqmWqjL+kyug8PerCj4lq4wtdA0VUIil1wyxtVop4+2u9R Kyo64mK6F/U/EduunV5kCDe09b+jnMVHBbGRTcTjXNPv60ajBN5kWpmhuF6UBu2FBIBW xkrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a51si18518046qte.286.2017.09.14.11.00.47 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:00:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49216 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYRS-0000iD-6y for patch@linaro.org; Thu, 14 Sep 2017 14:00:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088D-1q for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00082S-Tt for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007vb-Mp for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJQ-0005p0-2T for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:40 +0100 Message-Id: <1505411573-27848-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/18] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In do_v7m_exception_exit(), there's no need to force the high 4 bits of 'type' to 1 when calling v7m_exception_taken(), because we know that they're always 1 or we could not have got to this "handle return to magic exception return address" code. Remove the unnecessary ORs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-id: 1505137930-13255-6-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 1741e0d..fdd5cc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6306,7 +6306,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check\n"); return; @@ -6348,7 +6348,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " "failed exception return integrity check\n"); return; From patchwork Thu Sep 14 17:52:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112600 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1055260qgf; Thu, 14 Sep 2017 11:01:31 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDbv01x+AXrRpBpX7MUqJ4//xGvfPZ5MXUpSIHekbVwbrBs0mycs9Az/Z4B/V72pas0QcxS X-Received: by 10.55.146.195 with SMTP id u186mr3767384qkd.14.1505412091909; Thu, 14 Sep 2017 11:01:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412091; cv=none; d=google.com; s=arc-20160816; b=Rjz0DjM+wZygu/uCC6CSkiZCNRnHu12U2XMZXWevz0EXfktG+Hexu4zoOXxqY3sQpu 0uO2C3Nl+Adt8zoDLN22o6pohsilNRzyFyac5rahFWGyM+0GCMPCxHcOE6tDRX08Z9TF 9qkNPpnqZkmgX6pWp2QTHDwYmyDgn8i+WhQVuAciSNrYSjHOebsa7ExMRpIxK+9lAbQn Ks0iiGLxHHC3qR4VyMzEhgp7yRypigLZ8zz9VlsR83iVfxvgi3oGynLKLJWIDMDnXlNe NBnvfdtWoWEVO5rQXV9+1blMMhTLRuq5rx6qn2IKylXsTs9tJaxEby06sNaP/59+yinb xhYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=qUhUZjMzY8/iM1BLyK5zFb3CbE8zsb9HPRdHVSzVUKY=; b=CWzLI3J3+SwOT38C+hPGBFNsCFoZ5R13sFWT8NV1m0rMZ2+xbIsi1zH0XW4C9lfTdw poRW4l3uMR1M6dLPvK+u/jNT0vIeBYSwa0prbhbqO0Vh9Yg7w8SGM+bjuFf2PivUgwIy 2pvnPzpjrKVgIFlFMCiGtYJ1B4tDfy5ZVNOqsyuIBW3VbtLSluR/X64ySCjNDmAr5vXy 44qaa+W8eB0xbP5G4oNxHP8LOk8mYXFsfvo9IkIeQlPyLFpsKVru/O2RlFsn23jsibNe MeTRmCMeuBBPJxQE6FzgmbxbZaoBVMv4PsGZ+bxV3s45G1p1hUxSsh8xprtW1WvzAo2s yVtQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m9si1714937qkl.317.2017.09.14.11.01.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:01:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYS9-0001st-Ir for patch@linaro.org; Thu, 14 Sep 2017 14:01:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJb-00087X-LJ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00081M-GM for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007x0-8U for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJQ-0005pS-O2 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:41 +0100 Message-Id: <1505411573-27848-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/18] target/arm: Add and use defines for EXCRET constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org --- target/arm/internals.h | 10 ++++++++++ target/arm/helper.c | 14 +++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/target/arm/internals.h b/target/arm/internals.h index a315354..18be370 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) +/* Bit definitions for v7M exception return payload */ +FIELD(V7M_EXCRET, ES, 0, 1) +FIELD(V7M_EXCRET, RES0, 1, 1) +FIELD(V7M_EXCRET, SPSEL, 2, 1) +FIELD(V7M_EXCRET, MODE, 3, 1) +FIELD(V7M_EXCRET, FTYPE, 4, 1) +FIELD(V7M_EXCRET, DCRS, 5, 1) +FIELD(V7M_EXCRET, S, 6, 1) +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/helper.c b/target/arm/helper.c index fdd5cc6..a502e4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6242,7 +6242,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) " previous exception %d\n", type, env->v7m.exception); - if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { + if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); } @@ -6255,7 +6255,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es = type & 1; + int es = type & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { env->v7m.faultmask[es] = 0; } @@ -6491,12 +6491,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } - lr = 0xfffffff1; + lr = R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_S_MASK | + R_V7M_EXCRET_DCRS_MASK | + R_V7M_EXCRET_FTYPE_MASK | + R_V7M_EXCRET_ES_MASK; if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { - lr |= 4; + lr |= R_V7M_EXCRET_SPSEL_MASK; } if (!arm_v7m_is_handler_mode(env)) { - lr |= 8; + lr |= R_V7M_EXCRET_MODE_MASK; } v7m_push_stack(cpu); From patchwork Thu Sep 14 17:52:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112603 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1060387qgf; Thu, 14 Sep 2017 11:05:43 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDylWP25H1/8YJ5qgjaNrjL3wo410ScI63L+PwzGtjiVczTLaP7PzB701n4Lr7eBzP8z0Sr X-Received: by 10.200.47.184 with SMTP id l53mr27717964qta.120.1505412343083; Thu, 14 Sep 2017 11:05:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412343; cv=none; d=google.com; s=arc-20160816; b=0ar1/EuOdjBxy4uJ+XwYi25YI26bA6jK8/H/XGl/92IKd92YJk728mFrPn7rBVXBUB ss9ulJuiY5utoLG0Oryag3Q0NZZs1qOnjopbk4WhiQorf4gJiKWaOsFdwpkgEy858Sxn MIJU35fvMgH8v/hh27pZ0tffldWCGqegOgXKldN+ijMGuM+IfGAtVnPvY5JJheEWlJjD EAq10QS0vSddPvzheyC0UeqfDa6jvZw8PRmzhQKaB9yIA2ykq54klSsdRG3sVyqdCIyx rJbhQf7sMsqQD3ZPB7ZScbdeEM2GeOUJebo98X1TUSF8QmHL75kAlmDsvE/4+YX+7jiO k/Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=mlKuDkyaqjZFq4vTqvdfBvQ1LrREd/6PpEoVpNygboY=; b=uTJEgn5YPic8+roWsxeLsr9Scl4Qzs9UJdzEO4jeZCOR1DVnT2yTItxaC++LLrgulD oqKWVULvcwCCFGGuu3ygRCaMXhRTVozzhVo30ZYzvsYbxB+oheGqQbjz5bvnvJVPAClP K7xJwGI0q1orU1PPf3TD/mkQCLpa/VKsAmmYNH+5fjuIitU3Yhtwu9IpdKaxkXfh/1IG Q8H6oJ5eajAALlaH7REHq8RaAtY/UScm+2OPQpXk2RLjOwIUONYXF7tr1Popx2ZjZQxQ w/pCio4xxhppA1mDVgW+WXto9fF9BKy06Ekaa/9RcuFX6hbC3o0DvZYZ77kHZ8dGvG5I MW9w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m6si11687503qtc.386.2017.09.14.11.05.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:05:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49255 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYWD-00086i-30 for patch@linaro.org; Thu, 14 Sep 2017 14:05:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJb-00087n-Q0 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00081F-E2 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007iP-6a for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJR-0005pt-D8 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:42 +0100 Message-Id: <1505411573-27848-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/18] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the v7M and v8M ARM ARM, the magic exception return values are referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_* constants to define bits within them. Rename the 'type' variable which holds the exception return value in do_v7m_exception_exit() to excret, making it clearer that it does hold an EXC_RETURN value. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index a502e4e..4f41841 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6212,7 +6212,7 @@ static void v7m_push_stack(ARMCPU *cpu) static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env = &cpu->env; - uint32_t type; + uint32_t excret; uint32_t xpsr; bool ufault = false; bool return_to_sp_process = false; @@ -6233,18 +6233,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * the target value up between env->regs[15] and env->thumb in * gen_bx(). Reconstitute it. */ - type = env->regs[15]; + excret = env->regs[15]; if (env->thumb) { - type |= 1; + excret |= 1; } qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 " previous exception %d\n", - type, env->v7m.exception); + excret, env->v7m.exception); - if ((type & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { + if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " - "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); + "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", + excret); } if (env->v7m.exception != ARMV7M_EXCP_NMI) { @@ -6255,7 +6256,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es = type & R_V7M_EXCRET_ES_MASK; + int es = excret & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { env->v7m.faultmask[es] = 0; } @@ -6283,7 +6284,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) g_assert_not_reached(); } - switch (type & 0xf) { + switch (excret & 0xf) { case 1: /* Return to Handler */ return_to_handler = true; break; @@ -6306,7 +6307,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check\n"); return; @@ -6341,14 +6342,14 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the - * exception return type specified then this is a UsageFault. + * exception return excret specified then this is a UsageFault. */ if (return_to_handler != arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " "failed exception return integrity check\n"); return; From patchwork Thu Sep 14 17:52:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112605 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1064508qgf; Thu, 14 Sep 2017 11:09:03 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCYm/h6LSZToQFgUEszJEY222WEUCpLnAlbSI5D1Ly4N/k+VhDzeo0GKTGLvaCBVjLmqDvU X-Received: by 10.200.0.207 with SMTP id d15mr12812219qtg.165.1505412543744; Thu, 14 Sep 2017 11:09:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412543; cv=none; d=google.com; s=arc-20160816; b=RZeO00bmXi3QxvSrXz2xtgI9shI0OFKEXhuXZ4iiLrlTT1gWPjOTpgwJT+YXDUmagM f2Us57brZKY5EqoFoXseAmculMCC+x0xcgauZR2lZt30gzgEdHWuzj2VioQY8qeivWCf 1Trpy0Rm5xj98+6AZv99/cMTrudpM6kNDJTQ5kC+KBwJRUYGHEgmWizfX1V18SlJVvRl XEkG65hot8f1mwA2tJ57vT7nB4GC9dZMdWb8uNJypQyMMQIR9dpbVHREwDxtWGWrqu8B uQ+Ofd0eZIvblarSJWWLI5Obkq/HERkaelN6wL7zbnbNPC56Q1y+mYilLTZB7IWroRGy NdNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=FJn2PmHE/rbGY309/prMBwqHr5jyXJdLlKMHKNtKKyI=; b=DmInO0d1a4bpnWvIjQZFKqGzGQntVLMd+WtT3QWdCZB3K1LJ6B/3H8tZ/eHwhaSAdU vbx9ynNJ7GwmrcjAoXxSIO9Jx5hcHLwooOLAEkQRi4BhcxVVOuU+xZiQp3AytbOUK1Yf +p09JYbqjDppf8wNrwo3hTt6bnw6w6Al1Q1xtF6bsOFehQcQnY62hm227uAvqg2zphDE a1E8Qw/fYjDiHIjgsSnfjLhrTnZMCxpttl5AILi655W6wK54ifKdKcPsKPV+DCAn6Nm7 qQjKNxvJiFGory6HGkMnqFa6IBfIQSBw1y53aY1QKXdxmjkbC3/ynOiWNfpf3IBOYXD5 JW8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h67si6373204qkd.359.2017.09.14.11.09.03 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:09:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49271 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYZR-0002a0-Ls for patch@linaro.org; Thu, 14 Sep 2017 14:09:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJb-000879-8o for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-00080I-V3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJZ-0007vb-NL for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJS-0005qK-1V for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:30 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:43 +0100 Message-Id: <1505411573-27848-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/18] xlnx-ep108: Rename to ZCU102 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The EP108 is a early access development board. Now that silicon is in production people have access to the ZCU102. Let's rename the internal QEMU files and variables to use the ZCU102. There is no functional change here as the EP108 is still a valid board option. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/Makefile.objs | 2 +- hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 16 deletions(-) rename hw/arm/{xlnx-ep108.c => xlnx-zcu102.c} (85%) -- 2.7.4 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index a2e56ec..5ee6f7d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -13,7 +13,7 @@ obj-y += omap1.o omap2.o strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o -obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-zcu102.c similarity index 85% rename from hw/arm/xlnx-ep108.c rename to hw/arm/xlnx-zcu102.c index c339cd4..e9702ed 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-zcu102.c @@ -1,5 +1,5 @@ /* - * Xilinx ZynqMP EP108 board + * Xilinx ZynqMP ZCU102 board * * Copyright (C) 2015 Xilinx Inc * Written by Peter Crosthwaite @@ -25,16 +25,16 @@ #include "exec/address-spaces.h" #include "qemu/log.h" -typedef struct XlnxEP108 { +typedef struct XlnxZCU102 { XlnxZynqMPState soc; MemoryRegion ddr_ram; -} XlnxEP108; +} XlnxZCU102; -static struct arm_boot_info xlnx_ep108_binfo; +static struct arm_boot_info xlnx_zcu102_binfo; -static void xlnx_ep108_init(MachineState *machine) +static void xlnx_zcu102_init(MachineState *machine) { - XlnxEP108 *s = g_new0(XlnxEP108, 1); + XlnxZCU102 *s = g_new0(XlnxZCU102, 1); int i; uint64_t ram_size = machine->ram_size; @@ -47,7 +47,7 @@ static void xlnx_ep108_init(MachineState *machine) } if (ram_size < 0x08000000) { - qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for EP108", + qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102", ram_size); } @@ -108,18 +108,18 @@ static void xlnx_ep108_init(MachineState *machine) /* TODO create and connect IDE devices for ide_drive_get() */ - xlnx_ep108_binfo.ram_size = ram_size; - xlnx_ep108_binfo.kernel_filename = machine->kernel_filename; - xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline; - xlnx_ep108_binfo.initrd_filename = machine->initrd_filename; - xlnx_ep108_binfo.loader_start = 0; - arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo); + xlnx_zcu102_binfo.ram_size = ram_size; + xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename; + xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline; + xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename; + xlnx_zcu102_binfo.loader_start = 0; + arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } static void xlnx_ep108_machine_init(MachineClass *mc) { mc->desc = "Xilinx ZynqMP EP108 board"; - mc->init = xlnx_ep108_init; + mc->init = xlnx_zcu102_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; @@ -130,7 +130,7 @@ DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) static void xlnx_zcu102_machine_init(MachineClass *mc) { mc->desc = "Xilinx ZynqMP ZCU102 board"; - mc->init = xlnx_ep108_init; + mc->init = xlnx_zcu102_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; From patchwork Thu Sep 14 17:52:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112604 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1060413qgf; Thu, 14 Sep 2017 11:05:44 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAzml4jynyPTxbfGw3VFdPtEScULENVIZCuYbZC7lK/Kn4CCJcCV4nt1fzhQ1KxvICLoqBC X-Received: by 10.55.139.65 with SMTP id n62mr3798653qkd.94.1505412344207; Thu, 14 Sep 2017 11:05:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412344; cv=none; d=google.com; s=arc-20160816; b=JtfwdWDtFwD9N1YruL3x1bbAMVfnqgMDfHRh+CKCNCBQR4AJ5kgIkt1c/zNIrtPdAI 5lnroziueRm8bmtYO3u0dHwYRNWNvvmbvrnoQX0V1BOMawPYebK4ru4eD/NDt4Tga2yA aY3kOwk/6ouFl9ABIxiqx8c/I1S1fwljcMVRZb0QqVbQ4ggsV1ff127K9LAgALM9ZMEL IsqBYOa5aGFbzNkvscNwf5pZhevOU2FVyXssxJKs6k38iiKz3TzuKmKS19pG21VPEEf4 78d80Y7/nL4MOhSrXfbxcR1quPx2O7W8cLeyhhAuC0Juwt718C7hRMbfHaNv4gESIGn9 JxlA== ARC-Message-Signature: i=1; a=rsa-sha256; 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/18] xlnx-zcu102: Manually create the machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis In preperation for future work let's manually create the Xilnx machines. This will allow us to set properties for the machines in the future. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index e9702ed..5b1f184 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -26,15 +26,24 @@ #include "qemu/log.h" typedef struct XlnxZCU102 { + MachineState parent_obj; + XlnxZynqMPState soc; MemoryRegion ddr_ram; } XlnxZCU102; +#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") +#define ZCU102_MACHINE(obj) \ + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) + +#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108") +#define EP108_MACHINE(obj) \ + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE) + static struct arm_boot_info xlnx_zcu102_binfo; -static void xlnx_zcu102_init(MachineState *machine) +static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { - XlnxZCU102 *s = g_new0(XlnxZCU102, 1); int i; uint64_t ram_size = machine->ram_size; @@ -116,19 +125,56 @@ static void xlnx_zcu102_init(MachineState *machine) arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } -static void xlnx_ep108_machine_init(MachineClass *mc) +static void xlnx_ep108_init(MachineState *machine) +{ + XlnxZCU102 *s = EP108_MACHINE(machine); + + xlnx_zynqmp_init(s, machine); +} + +static void xlnx_ep108_machine_instance_init(Object *obj) { +} + +static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Xilinx ZynqMP EP108 board"; - mc->init = xlnx_zcu102_init; + mc->init = xlnx_ep108_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; } -DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) +static const TypeInfo xlnx_ep108_machine_init_typeinfo = { + .name = MACHINE_TYPE_NAME("xlnx-ep108"), + .parent = TYPE_MACHINE, + .class_init = xlnx_ep108_machine_class_init, + .instance_init = xlnx_ep108_machine_instance_init, + .instance_size = sizeof(XlnxZCU102), +}; -static void xlnx_zcu102_machine_init(MachineClass *mc) +static void xlnx_ep108_machine_init_register_types(void) { + type_register_static(&xlnx_ep108_machine_init_typeinfo); +} + +static void xlnx_zcu102_init(MachineState *machine) +{ + XlnxZCU102 *s = ZCU102_MACHINE(machine); + + xlnx_zynqmp_init(s, machine); +} + +static void xlnx_zcu102_machine_instance_init(Object *obj) +{ +} + +static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Xilinx ZynqMP ZCU102 board"; mc->init = xlnx_zcu102_init; mc->block_default_type = IF_IDE; @@ -136,4 +182,18 @@ static void xlnx_zcu102_machine_init(MachineClass *mc) mc->ignore_memory_transaction_failures = true; } -DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) +static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { + .name = MACHINE_TYPE_NAME("xlnx-zcu102"), + .parent = TYPE_MACHINE, + .class_init = xlnx_zcu102_machine_class_init, + .instance_init = xlnx_zcu102_machine_instance_init, + .instance_size = sizeof(XlnxZCU102), +}; + +static void xlnx_zcu102_machine_init_register_types(void) +{ + type_register_static(&xlnx_zcu102_machine_init_typeinfo); +} + +type_init(xlnx_zcu102_machine_init_register_types) +type_init(xlnx_ep108_machine_init_register_types) From patchwork Thu Sep 14 17:52:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112602 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1059382qgf; Thu, 14 Sep 2017 11:04:54 -0700 (PDT) X-Google-Smtp-Source: AOwi7QC6AkKhYXQlGMnaqe26L1NmdIU1BX5ZPe6Blyvj349X4j9Rjj2UyqbtQSyZL26xh3F+Ei2m X-Received: by 10.55.86.134 with SMTP id k128mr4170091qkb.56.1505412294063; Thu, 14 Sep 2017 11:04:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412294; cv=none; d=google.com; s=arc-20160816; b=jwdpFQ6GIkyuQaeBQPvM/4o66RPC6hJA2F4J4bAXL6gh9Bp6oIphVtR8/B1tc3Q4Yb sXWAZY2iMob3hI47K8fxLsy30dswljtY18jC/61fVMES7NEZXex6wXxbhGl5xqTUBbwH E4PH0qlDS1pPPWkXqK/Zmp72ymf39VlBPQJGuTOVn9C0Tr7VtIDWQlXQH/AZaszC7CVZ 4U6ff4ZybjraBNeHaEHjLhszr9WD0iu6vFxISKmJxxlmT/D2YSyNSd4QhASdduas2GQ3 4lWSp5W2f+pVDHlcAM9to0xa8gly/F8TVX52l9JqW8dfMqkTnRJhluHRwECkkh6Dy4+W 8ckg== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b45si8770476qtk.535.2017.09.14.11.04.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:04:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYVQ-0007L1-06 for patch@linaro.org; Thu, 14 Sep 2017 14:04:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00085o-1A for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-0007yS-0O for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007vb-Pf for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJT-0005rC-Aj for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:45 +0100 Message-Id: <1505411573-27848-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/18] xlnx-zcu102: Add a machine level secure property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add a machine level secure property. This defaults to false and can be set to true using this machine command line argument: -machine xlnx-zcu102,secure=on This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 5b1f184..bd573c4 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -30,6 +30,8 @@ typedef struct XlnxZCU102 { XlnxZynqMPState soc; MemoryRegion ddr_ram; + + bool secure; } XlnxZCU102; #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") @@ -42,6 +44,20 @@ typedef struct XlnxZCU102 { static struct arm_boot_info xlnx_zcu102_binfo; +static bool zcu102_get_secure(Object *obj, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + return s->secure; +} + +static void zcu102_set_secure(Object *obj, bool value, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + s->secure = value; +} + static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { int i; @@ -69,6 +85,8 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), "ddr-ram", &error_abort); + object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", + &error_fatal); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); @@ -134,6 +152,10 @@ static void xlnx_ep108_init(MachineState *machine) static void xlnx_ep108_machine_instance_init(Object *obj) { + XlnxZCU102 *s = EP108_MACHINE(obj); + + /* EP108, we don't support setting secure */ + s->secure = false; } static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) @@ -169,6 +191,16 @@ static void xlnx_zcu102_init(MachineState *machine) static void xlnx_zcu102_machine_instance_init(Object *obj) { + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + /* Default to secure mode being disabled */ + s->secure = false; + object_property_add_bool(obj, "secure", zcu102_get_secure, + zcu102_set_secure, NULL); + object_property_set_description(obj, "secure", + "Set on/off to enable/disable the ARM " + "Security Extensions (TrustZone)", + NULL); } static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) From patchwork Thu Sep 14 17:52:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112591 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1046354qgf; Thu, 14 Sep 2017 10:53:09 -0700 (PDT) X-Google-Smtp-Source: AOwi7QA6pkiBX4800DzqVQcbFT3kuW08FBT1DqDXTH7cQTMJcvUugdmKdcDs/pPpDcejp8bZ5EEo X-Received: by 10.55.182.65 with SMTP id g62mr3990745qkf.45.1505411589232; Thu, 14 Sep 2017 10:53:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411589; cv=none; d=google.com; s=arc-20160816; b=p3JXPMXvns9ojJE5syKT0If3iMhtEF5dMeHHkuzAsmJkeqK/SQpWDepXf40ydsBagK Un8l4U/xEMA3e71wMUreG37AlsvuJ7zsw/JAckgpKFfOonlZnrHRnywG8q5pAoVFxFOs +Ak/+e3YtayVP3Thlleq7e236okB3TTZCeeEXSQEHQr2XDI5xANwpe5SezErJ6EKCHDr qbM0y2tk4001intvtMiDO27kUlHad6d0K9TCFl8uhF77FwqeMSWrLVObaATOMFiaPAo5 WVDbW4XKMxhJNn2KJSNfvE8JIioPE3n3e8d2n4KBpYsWT3y5N8oQfn0bhjpaPAs/1zNY pS/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=XLEdjdVFJ8B3DpaKPEWZ+qd6852aHFzasshIcN7HWUg=; b=lalRIjHWyM+WoBx9pomSv32D+9kqCjJxRHmzxAOA10LjV/pjAxEHUG7bGSeBgFt3qX eBub32knI8C1u+kaYwxJ+SAr2FidWfUuGxaj4eNIHUvjf6Dsossyai/B3L3dtnXFUXdV BX00e6pju9js5OgNu3536eJaVW3ZtK2nCsWfmaHHwG2SbpFnuU6qND33q6zxWX9X5Fhr I7mDzhrTvvu1XspAhboTIbixmtUavjXPePJbyxQzJK2+Q3xho4Eo3RtBZARXuKHqvxtY kbAgjLTbH8pDmr2yt3ELhMCVgr2BUEanGkNr948XiIWY36n8ewtlKkAxv2wrdY73qAbJ 4LBw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d3si14123400qta.198.2017.09.14.10.53.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 10:53:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49179 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYK2-00088b-Tw for patch@linaro.org; Thu, 14 Sep 2017 13:53:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJZ-00085b-OF for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJY-0007xk-Fz for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007iP-7e for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJT-0005rd-Vp for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:46 +0100 Message-Id: <1505411573-27848-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/18] xlnx-zcu102: Add a machine level virtualization property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add a machine level virtualization property. This defaults to false and can be set to true using this machine command line argument: -machine xlnx-zcu102,virtualization=on This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++- hw/arm/xlnx-zynqmp.c | 3 ++- 3 files changed, 33 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c2931bf..6eff81a 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -91,6 +91,8 @@ typedef struct XlnxZynqMPState { /* Has the ARM Security extensions? */ bool secure; + /* Has the ARM Virtualization extensions? */ + bool virt; /* Has the RPU subsystem? */ bool has_rpu; } XlnxZynqMPState; diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index bd573c4..42deefd 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -32,6 +32,7 @@ typedef struct XlnxZCU102 { MemoryRegion ddr_ram; bool secure; + bool virt; } XlnxZCU102; #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") @@ -58,6 +59,20 @@ static void zcu102_set_secure(Object *obj, bool value, Error **errp) s->secure = value; } +static bool zcu102_get_virt(Object *obj, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + return s->virt; +} + +static void zcu102_set_virt(Object *obj, bool value, Error **errp) +{ + XlnxZCU102 *s = ZCU102_MACHINE(obj); + + s->virt = value; +} + static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { int i; @@ -87,6 +102,8 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) "ddr-ram", &error_abort); object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", &error_fatal); + object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization", + &error_fatal); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); @@ -154,8 +171,9 @@ static void xlnx_ep108_machine_instance_init(Object *obj) { XlnxZCU102 *s = EP108_MACHINE(obj); - /* EP108, we don't support setting secure */ + /* EP108, we don't support setting secure or virt */ s->secure = false; + s->virt = false; } static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) @@ -201,6 +219,16 @@ static void xlnx_zcu102_machine_instance_init(Object *obj) "Set on/off to enable/disable the ARM " "Security Extensions (TrustZone)", NULL); + + /* Default to virt (EL2) being disabled */ + s->virt = false; + object_property_add_bool(obj, "virtualization", zcu102_get_virt, + zcu102_set_virt, NULL); + object_property_set_description(obj, "virtualization", + "Set on/off to enable/disable emulating a " + "guest CPU which implements the ARM " + "Virtualization Extensions", + NULL); } static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 22c2a33..2b27daf 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -255,7 +255,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->apu_cpu[i]), s->secure, "has_el3", NULL); object_property_set_bool(OBJECT(&s->apu_cpu[i]), - false, "has_el2", NULL); + s->virt, "has_el2", NULL); object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, "reset-cbar", &error_abort); object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", @@ -427,6 +427,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) static Property xlnx_zynqmp_props[] = { DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), + DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, MemoryRegion *), From patchwork Thu Sep 14 17:52:47 2017 Content-Type: text/plain; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id i4si3463497qta.167.2017.09.14.10.56.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 10:56:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49192 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYMo-0002kS-OP for patch@linaro.org; Thu, 14 Sep 2017 13:55:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJY-00084n-DN for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJX-0007wf-Hh for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJX-0007iP-AR for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJU-0005s4-LL for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:47 +0100 Message-Id: <1505411573-27848-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/18] xlnx-zcu102: Mark the EP108 machine as deprecated X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The EP108 is the same as the ZCU102, mark it as deprecated as we don't need two machines. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 42deefd..519a16e 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -180,7 +180,7 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Xilinx ZynqMP EP108 board"; + mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)"; mc->init = xlnx_ep108_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; From patchwork Thu Sep 14 17:52:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112590 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1046265qgf; Thu, 14 Sep 2017 10:53:04 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBVhv1xKJKF9/vZPPcTXBQL4jdF365lEZNGFJ62XC/V/SC3KOTzyiKk80DuzH4+xPJNwHrM X-Received: by 10.55.72.81 with SMTP id v78mr3779192qka.333.1505411584356; Thu, 14 Sep 2017 10:53:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411584; cv=none; d=google.com; s=arc-20160816; b=cqnCtqcu7tSvYy20F3IADnah/dt/JRTyNDZEbC3/nIYvDfEYqCWkjUql73n3ncUEte 0QqUsSZ7rPMct0KXfLEu32cCxIVIecOmBmDzcWz3MWVWpioo01AoqON8QyRrucN8VUn8 hV3Z/DjLAp0NpYdWsP0YrK36G/c4sJll57rYQPkfri3GCLUrT/bbeFX21VFBbAr/jcx0 lMtiZV7yWDZ5z3/cKvwyhCKjIETXww61CMVKmvb1DZzglfsHzPi2xN5zQ3CrY6kfAr33 0zRb66TrWIxJ0sTNuW4jKj0wlTrzaZKvLA7d1KXE1NgiTYS5VN4UjK9r5vM6NpfNJb1t BuJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=Kp4+w1PA64/60jEM6lHLOySrmdhxmHCmIZ6+db7WWfI=; b=bCKK/VjrRfl1uDtjRkpPlt05YXVDaKO1G5fqIQ1ClgC7RE3uChMWxH76aUvpnNKyLw 4A9E8yYomvDdd4OsQtlrJGgLcht/ngVm4Z5zybHBHfk8nbQNRe/2pHObbOc48usYIdVw WaFFxSNq19hDiZiO+3cW8M07HwPunejrhyBH2DG80CWpesQg1OUQAHcOpqvS54pZiMK8 jZjfITT1n9WPckkaMgt3zWILmA4ug2nFD2yK8f+JE7aSi+53sQFyhf8h2Uu9Z/tjyt0c a5RNfv6P+q+MGrpfuHRATURf4Gk4S20MMNrLHhsCwZpZ943PGOchx/KgsnIHoIFpybk+ KWQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b3si17308144qkd.51.2017.09.14.10.53.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 10:53:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJy-000861-8d for patch@linaro.org; Thu, 14 Sep 2017 13:53:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJX-00084g-PU for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJW-0007vm-Ib for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJW-0007iP-Bb for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:34 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJV-0005sV-9U for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:48 +0100 Message-Id: <1505411573-27848-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/18] AArch64: Fix single stepping of ERET instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jaroslaw Pelczar Previously when single stepping through ERET instruction via GDB would result in debugger entering the "next" PC after ERET instruction. When debugging in kernel mode, this will also cause unintended behavior, because debugger will try to access memory from EL0 point of view. Signed-off-by: Jaroslaw Pelczar Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9017e30..1bc12d9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11348,6 +11348,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) default: gen_a64_set_pc_im(dc->pc); /* fall through */ + case DISAS_EXIT: case DISAS_JUMP: if (dc->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); From patchwork Thu Sep 14 17:52:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112597 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1053076qgf; Thu, 14 Sep 2017 10:59:53 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAsI0ygRXNQ3YsRfvDBjoUNzcyfZkyILz5IOyrtvO/zWfOwhNyiXhv4DT880gWarncuyGsO X-Received: by 10.200.56.124 with SMTP id r57mr33552128qtb.172.1505411993638; Thu, 14 Sep 2017 10:59:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411993; cv=none; d=google.com; s=arc-20160816; b=VYwxG2IZn7i+cXNZlvYSZhJkex423ZjB185U8ofFjiCvJsHYgbv4ROx0pb7ylSVkBf E9umMeqmxaeDzjr+26aklg17D0vwtpamE5NxmbSjZYeSs5uSOSs8gsZ0dAcau/AKXBX+ SAj2Qa/W4FTtKs1LIlDgaXeIsvwdoXT6DG9tpfw7ANGpqGSX7bsB/ZcQp+GaaJKrxxSt OHKFiTVZtqgc7ZIrNhIKQ9N81WmYK6ph/BRFKGVv7FzmDY63cntC6xLe+vWzYyhK7aAe l5g6dz5UWJA/HdtPv5bBHH9rQnNP6tFrq9lJ3yg1lCFRDNZSoDEGEhsQnRRusmcZSZE9 TyEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=RCleniZg43hTOweItpWw51s5Otf4O7uMxVg567EwyNQ=; b=nG8A8gro0gM3ZrJT26kawSIIEnZK/1LOVjWZFCtihf92d279+gPDhNRUGGSICLeDD6 vp7r1XvMC8x+FyfF2wfSCIhIHANhcWHMBLpsHarzmspT4WqcQ1AdP6yUHnE12VdpdKkB JZ1s0gfaOHRWgaxnNKQIT5yRVDoMmEpt23oaQ+ml7LexoFTuptOq8aGRM7sn5swqHzQo jweme005YCR8JTdLlIA1jKiY/N9G2n5VE3uvce0Isk4GxSki39nn5wXXetqirYLUbqX0 qFh5cwDirSJ9uapBnWm7qsPbYsKCYpm81Au/WQJX9vFFPkPCziV0vF51Ot3ZgwjcLINv BB0w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n94si17737270qte.174.2017.09.14.10.59.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 10:59:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49206 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYQZ-0007Lu-Bt for patch@linaro.org; Thu, 14 Sep 2017 13:59:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJY-00084m-6B for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJX-0007wN-6n for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJW-0007vb-Vd for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJV-0005t0-U7 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:49 +0100 Message-Id: <1505411573-27848-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/18] target/arm: Avoid an extra temporary for store_exclusive X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Instead of copying addr to a local temp, reuse the value (which we have just compared as equal) already saved in cpu_exclusive_addr. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20170908163859.29820-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) -- 2.7.4 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1bc12d9..083568c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1894,7 +1894,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, } static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, - TCGv_i64 inaddr, int size, int is_pair) + TCGv_i64 addr, int size, int is_pair) { /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] * && (!is_pair || env->exclusive_high == [addr + datasize])) { @@ -1910,13 +1910,8 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, */ TCGLabel *fail_label = gen_new_label(); TCGLabel *done_label = gen_new_label(); - TCGv_i64 addr = tcg_temp_local_new_i64(); TCGv_i64 tmp; - /* Copy input into a local temp so it is not trashed when the - * basic block ends at the branch insn. - */ - tcg_gen_mov_i64(addr, inaddr); tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); tmp = tcg_temp_new_i64(); @@ -1927,27 +1922,24 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, } else { tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); } - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, + cpu_exclusive_val, tmp, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data == MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, rt), - cpu_reg(s, rt2)); + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, + cpu_reg(s, rt), cpu_reg(s, rt2)); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, rt), - cpu_reg(s, rt2)); + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, + cpu_reg(s, rt), cpu_reg(s, rt2)); } } else { - TCGv_i64 val = cpu_reg(s, rt); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val, - get_mem_index(s), + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, + cpu_reg(s, rt), get_mem_index(s), size | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } - - tcg_temp_free_i64(addr); - tcg_gen_mov_i64(cpu_reg(s, rd), tmp); tcg_temp_free_i64(tmp); tcg_gen_br(done_label); From patchwork Thu Sep 14 17:52:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112593 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1049121qgf; Thu, 14 Sep 2017 10:55:56 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDKZfMCPq3aut7heMQbf6qAQdVanFsud1PhlnHYoMue21Yu+gGARUIDk2/2YLASfeC+5tkr X-Received: by 10.55.188.131 with SMTP id m125mr3384814qkf.12.1505411756863; Thu, 14 Sep 2017 10:55:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411756; cv=none; d=google.com; s=arc-20160816; b=ZdC3eiDQjW2gbwjhjS5EASmXK6di4iDuPia7a2heG6O2ehgBHyoFsAfB6ZDBvivls+ Ctf13ndvGqmq5wgBehDgJvoruuSPWHtbPmXRphYar0M+a7Or6whYt7kPhaiJ/Pnvc484 4rpDW9O+fEfPXConOn6UIZOAACho3I29TYKHCcrk43Tg2sN8Hyx+I7uwnTb03d3MADRb ysQXTpg5PI17c5AoXBcACrk6u9t8Mg7rFWdm72j0oT9BFUssO6uFNJAurbBFKXU/1FqA 3ZU7mqRk3kCc23hEiFYMce6f90dPL5t9vZyw2AWcBaF6/8zBz5mIwXHpTkbOqJCYB5mH D63g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=OU+aO2myF8dmTLB0SCs3ZTMYc8XnxP/TP3k22Oan6Ig=; b=eJnu//YnZgoE3wF4Z2KgEt5XAnpZzUDYM9WuwH0xQJ04tdeE8CUA75vBvBAggwEyc0 5E3e/MKkTkDmPBllGhi763IehB+dZDGuHsRwdxJR/S7lrYfjH93XJ/RbO/TMVXrmEv2o UntgGsQbKMAdXKDyuLQAkWz8pf7WXckhJJMqooIlgeBs8n4RADPwPlKsbzIiBi5/2CER Cq8KKNrO7qkCxw+HYv4QU+A0yba03hzXHO0nRjiUcSOIcV2cojGFT9W1DVNTerkN9xrg +3LmXDU1nYLuKwgOBUdyl+kBLAxRyieIzaHLVN0CzRa9rhv6UTbeGJOe9x+3eEsxE9Cw kSJg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/18] hw/pci-host/gpex: Set INTx index/gsi mapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Pranavkumar Sawargaonkar To implement INTx to gsi routing we need to pass the gpex host bridge the gsi associated to each INTx index. Let's introduce irq_num array and gpex_set_irq_num setter function. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Tushar Jagad Signed-off-by: Eric Auger Tested-by: Feng Kan Reviewed-by: Andrew Jones Message-id: 1505296004-6798-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/pci-host/gpex.h | 3 +++ hw/pci-host/gpex.c | 10 ++++++++++ 2 files changed, 13 insertions(+) -- 2.7.4 diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 68c9348..aef38b8 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -51,6 +51,9 @@ typedef struct GPEXHost { MemoryRegion io_ioport; MemoryRegion io_mmio; qemu_irq irq[GPEX_NUM_IRQS]; + int irq_num[GPEX_NUM_IRQS]; } GPEXHost; +int gpex_set_irq_num(GPEXHost *s, int index, int gsi); + #endif /* HW_GPEX_H */ diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 83084b9..41a884d 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -43,6 +43,16 @@ static void gpex_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(s->irq[irq_num], level); } +int gpex_set_irq_num(GPEXHost *s, int index, int gsi) +{ + if (index >= GPEX_NUM_IRQS) { + return -EINVAL; + } + + s->irq_num[index] = gsi; + return 0; +} + static void gpex_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci = PCI_HOST_BRIDGE(dev); From patchwork Thu Sep 14 17:52:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112601 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1056013qgf; Thu, 14 Sep 2017 11:02:07 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCHRSf8TiAgMiNyYwRfbc9skKM9NamTC6rnZadjbjXPxM6LnBoWPlDKKJwJ1I78m6/sMrXP X-Received: by 10.237.63.248 with SMTP id w53mr9231352qth.290.1505412127387; Thu, 14 Sep 2017 11:02:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412127; cv=none; d=google.com; s=arc-20160816; b=OGVohf7wJpXAxoBHNxEAh7U0dmKFyAy1/dorQcvYECnxtJ+tf5QaRyEaBIReiblL34 Q6kbWBj8GpoG3I/72z9k+TO67z/1dy3cgr1ziKUY0AXCActTycoilo9xda5Y+gDV2Ocd LUjSOrqO2bIwEc6fL7W3V+rIMgLHH4VXAzVMaGYq5ghSAllKtAI37JxRgD5OC+7cdoKC +P1ncW0Ihx8w3hE22KYaUwlby+ah93o64ujaJ61hXLjOGCkMbsxtt/dogx/7zliQbEwj LOPE/6H8aUGOpBuPzisvlzEJ1OIVXFojVqx2uHMUacDAE6nN9GQMf4cNRG29sqJaE7lk Vg9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=K5T9GoY7BT05y5Pfgmku+ekBOprSmOAjT6+1DB368AA=; b=ULvIawdatlOXmOwk444MIZzdJwM4GC2a5vsFRyVitB41J9jLP3Gs7ucFnbU0RkAIAo 8wtUKWLIuOewNWRqaELgrwbk6/Isc5oHsuoKY2OMrGpf0ULITmg7PLgECKQv+QAxwHu9 LgJbvhzt/MAM3Qv2Mvdvwm9xcl8leNTYrsO4jYTmA98lg9O6SGJakCmmDKX0vqQeyJXK a32+qzK2x99FK5gPSCXmSGq2tT6z8RRIhLDpvapPyg1ddrJoQbtzxr8FLXTc4R/S2UTB K4LSmj8mOKVIwsNZ371sRZSqy10f+76Lv/23s5J9/mU3oq8qsDiLLU3lzGBMHMSjSnqu PW7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t3si5735288qtb.375.2017.09.14.11.02.07 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:02:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYSj-0002pI-BS for patch@linaro.org; Thu, 14 Sep 2017 14:02:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJZ-000854-8p for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJY-0007xy-HX for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007x0-As for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJX-0005th-9k for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:35 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:51 +0100 Message-Id: <1505411573-27848-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/18] hw/arm/virt: Set INTx/gsi mapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Pranavkumar Sawargaonkar Let's provide the GPEX host bridge with the INTx/gsi mapping. This is needed for INTx/gsi routing. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Tushar Jagad Signed-off-by: Eric Auger Reviewed-by: Andrew Jones Tested-by: Feng Kan Message-id: 1505296004-6798-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index fe96557..cfd834d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1057,6 +1057,7 @@ static void create_pcie(const VirtMachineState *vms, qemu_irq *pic) for (i = 0; i < GPEX_NUM_IRQS; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } pci = PCI_HOST_BRIDGE(dev); From patchwork Thu Sep 14 17:52:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112592 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1046463qgf; Thu, 14 Sep 2017 10:53:15 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCaoJeIYAMnsNKPfVPCxZQmyqXpCbhGK4AhqS/ySAq+YNhUYWtm37JsjLQymkdz7QmqFYyw X-Received: by 10.200.3.4 with SMTP id q4mr30241992qtg.200.1505411595864; Thu, 14 Sep 2017 10:53:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505411595; cv=none; d=google.com; s=arc-20160816; b=x3nnZsi57SChfKvtZKhJZOAcLMo3Gz5wSUojFVk5JI0OuBWu2irCR6i1cH6pz4eg0g w6iTuUGLSNST4s9AQcxgfvKHntjsOteIvTL4D5VV+Y+/Zz7tXd5TUeayTkN5HgbHX/Dp 0nNkWyKK7j6V/eTzpVXDi2N3iNJ0rJPdCSsginZhAr6uqKZc/uGnmsZogoeiOPtLrIUd tfGu7fSGkzxYrUaiSYxt7LGKlSBJRqYkyFaEcGbRJidfU5aFzEImwSIh3AxeEn7Zmf+V 7G5ZwxFv0t6qEPqAkZO1oZbjFMf7mRcwAY7+DsqSiH9sA8f9PRCuKagJ90y+m6auSJuf fOmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=99Cym6sDFkuXNIO61ZffK2XT6+Qff92KTmIUkyDq+tg=; b=UPJBv/PWpxWhz4dzFBhV8B+Rr/z0gv9RcQh+fn+0FUsPaQ2ocqH1JbW8N9FbypaOzA fHRlFKxRjwCWNhQiHMR6BCwN5r1HxTZ1hCerlJBv+Qiqxl6p4Ew2cxqcUz/uSmT8E5gh rFJ4RMd7gRiggoEYnBDzrmtIt3ms6g1MADarKXCHVKQhJCaxTsBQkgZH/xBFgK+6fWHB 5UQDfW+ZUHC263D7OHoOo6N+diZA36hs5uimnSMQixVN2kTmN7gKyKS/kh/z/wLdBhQi hbevK5565l13HTVi4QeIiS45ghI9q+kkFZ5jkXb07kzbyxD8jnZER51nQYPkhcc6ML+8 x5qA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Pranavkumar Sawargaonkar Now we are able to retrieve the gsi from the INTx pin, let's enable intx_to_irq routing. From that point on, irqfd becomes usable along with INTx when assigning a PCIe device. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Tushar Jagad Signed-off-by: Eric Auger Reviewed-by: Andrew Jones Tested-by: Feng Kan Message-id: 1505296004-6798-4-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/pci-host/gpex.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.7.4 diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 41a884d..be25245 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -53,6 +53,17 @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi) return 0; } +static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) +{ + PCIINTxRoute route; + GPEXHost *s = opaque; + + route.mode = PCI_INTX_ENABLED; + route.irq = s->irq_num[pin]; + + return route; +} + static void gpex_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci = PCI_HOST_BRIDGE(dev); @@ -77,6 +88,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) &s->io_ioport, 0, 4, TYPE_PCIE_BUS); qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus)); + pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); qdev_init_nofail(DEVICE(&s->gpex_root)); } From patchwork Thu Sep 14 17:52:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 112598 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1054119qgf; Thu, 14 Sep 2017 11:00:41 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBqnOW9Z2ULPo3KxerhJ0jB3YQ8zyNYBiD3CmqrRR7XR/6MtY0rSnSh5wKLAENyIFHXidy1 X-Received: by 10.55.98.214 with SMTP id w205mr3688174qkb.355.1505412040065; Thu, 14 Sep 2017 11:00:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505412040; cv=none; d=google.com; s=arc-20160816; b=Dn370KBdUJOiSV6VKX4r7bhk2wYBMbobBytBPri4dqaE22FRIIpfcZhjW9hOqEWQ17 xLH4/yFpltLo4mOh+c5Bci5ROxF5RJNSxrxJqps/TBrLAAdNpYiK5Am7jTXxcsSjaz82 pwcOyjGWhEfiRtsU9nyDwCBjAn9IbD5IoCJoK6S0+0hH8lRAO/ZnTezsx6pKBWJ0CnB+ cRwOMs2lQjPEO+sJJi3KWoxVyWWY0bkNxAROty0+LNbuGPiEAdrwOeXdogUL8K6IvIoS udwkC1eP63YimOT8lO4HiigFADHCU7kHvUoqtNhL71AgJBwdEFKebATkSXN8svRgsouD eWdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=GSoJ8QP9UDeZ1ihtS4ssGN4pX7CqU4ZhPKk6DSvp8dE=; b=ovLsTX7UpmkqWH1OQKEXVlWFAHowOdRTQvgx7dXJTgsFASDJYrXUYLB0k6GgDMvyvB KGVxmYdVlfWVtKc693zV2s0v/xtrQtslVBwG+zFjm134Mifh4AN/sabtNva8CZklGPPf LDdQgKMhEa56TGMJAl6DaKfE1+RTFZqv8sIXGwHyq6t3YS9vpxDMci38BpKUiKk1RvbR uoPVvyMMs+FX0d1Ib2R1qAfrKj+W9nCwC8QvVShmCINssPrWohtTAX09trHXm3/YgM6h hdoJW3I4/wiu69/W/Wws2MnEl9CtgfG5bxpsXhaomundcXqIwn9k2DolpHTAFm6woanw UJFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i34si17328807qtb.207.2017.09.14.11.00.39 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 14 Sep 2017 11:00:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49211 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYRK-0000IC-24 for patch@linaro.org; Thu, 14 Sep 2017 14:00:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00086k-QL for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-00080Q-VS for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJZ-0007yZ-Nm for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJY-0005uU-J4 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:36 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:53 +0100 Message-Id: <1505411573-27848-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/18] mps2-an511: Fix wiring of UART overflow interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fix an error that meant we were wiring every UART's overflow interrupts into the same inputs 0 and 1 of the OR gate, rather than giving each its own input. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 1505232834-20890-1-git-send-email-peter.maydell@linaro.org --- hw/arm/mps2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index abb0ab6..769cff8 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -287,8 +287,8 @@ static void mps2_common_init(MachineState *machine) cmsdk_apb_uart_create(uartbase[i], qdev_get_gpio_in(txrx_orgate_dev, 0), qdev_get_gpio_in(txrx_orgate_dev, 1), - qdev_get_gpio_in(orgate_dev, 0), - qdev_get_gpio_in(orgate_dev, 1), + qdev_get_gpio_in(orgate_dev, i * 2), + qdev_get_gpio_in(orgate_dev, i * 2 + 1), NULL, uartchr, SYSCLK_FRQ); }