From patchwork Wed Jun 17 21:33:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 217646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 825DBC433E0 for ; Wed, 17 Jun 2020 21:33:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BBAD21852 for ; Wed, 17 Jun 2020 21:33:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727015AbgFQVdk (ORCPT ); Wed, 17 Jun 2020 17:33:40 -0400 Received: from gloria.sntech.de ([185.11.138.130]:48414 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726758AbgFQVdj (ORCPT ); Wed, 17 Jun 2020 17:33:39 -0400 Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=phil.sntech) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jlfgX-00063V-FC; Wed, 17 Jun 2020 23:33:29 +0200 From: Heiko Stuebner To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, heiko@sntech.de, christoph.muellner@theobroma-systems.com, Heiko Stuebner Subject: [PATCH v4 2/3] dt-bindings: net: ethernet-phy: add enet-phy-clock-out-frequency Date: Wed, 17 Jun 2020 23:33:25 +0200 Message-Id: <20200617213326.1532365-3-heiko@sntech.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200617213326.1532365-1-heiko@sntech.de> References: <20200617213326.1532365-1-heiko@sntech.de> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Heiko Stuebner Some ethernet phys have a configurable clock output, so add a generic property to describe its target rate. Suggested-by: Andrew Lunn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 9b1f1147ca36..4dcf93f1c555 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -84,6 +84,11 @@ properties: the turn around line low at end of the control phase of the MDIO transaction. + enet-phy-clock-out-frequency: + $ref: /schemas/types.yaml#definitions/uint32 + description: + Frequency in Hz to set an available clock output to. + enet-phy-lane-swap: $ref: /schemas/types.yaml#definitions/flag description: From patchwork Wed Jun 17 21:33:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 217645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3800FC433E1 for ; Wed, 17 Jun 2020 21:33:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B47D2186A for ; Wed, 17 Jun 2020 21:33:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727050AbgFQVdl (ORCPT ); Wed, 17 Jun 2020 17:33:41 -0400 Received: from gloria.sntech.de ([185.11.138.130]:48420 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726993AbgFQVdj (ORCPT ); Wed, 17 Jun 2020 17:33:39 -0400 Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=phil.sntech) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1jlfgX-00063V-TK; Wed, 17 Jun 2020 23:33:29 +0200 From: Heiko Stuebner To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, andrew@lunn.ch, f.fainelli@gmail.com, hkallweit1@gmail.com, linux@armlinux.org.uk, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, heiko@sntech.de, christoph.muellner@theobroma-systems.com, Heiko Stuebner Subject: [PATCH v4 3/3] net: phy: mscc: handle the clkout control on some phy variants Date: Wed, 17 Jun 2020 23:33:26 +0200 Message-Id: <20200617213326.1532365-4-heiko@sntech.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200617213326.1532365-1-heiko@sntech.de> References: <20200617213326.1532365-1-heiko@sntech.de> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Heiko Stuebner At least VSC8530/8531/8540/8541 contain a clock output that can emit a predefined rate of 25, 50 or 125MHz. This may then feed back into the network interface as source clock. So follow the example the at803x already set and introduce a vsc8531,clk-out-frequency property to set that output. Signed-off-by: Heiko Stuebner --- drivers/net/phy/mscc/mscc.h | 9 ++++ drivers/net/phy/mscc/mscc_main.c | 87 +++++++++++++++++++++++++++++--- 2 files changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index fbcee5fce7b2..a3afc35c3eab 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -218,6 +218,13 @@ enum rgmii_clock_delay { #define INT_MEM_DATA_M 0x00ff #define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x)) +#define MSCC_CLKOUT_CNTL 13 +#define CLKOUT_ENABLE BIT(15) +#define CLKOUT_FREQ_MASK GENMASK(14, 13) +#define CLKOUT_FREQ_25M (0x0 << 13) +#define CLKOUT_FREQ_50M (0x1 << 13) +#define CLKOUT_FREQ_125M (0x2 << 13) + #define MSCC_PHY_PROC_CMD 18 #define PROC_CMD_NCOMPLETED 0x8000 #define PROC_CMD_FAILED 0x4000 @@ -360,6 +367,8 @@ struct vsc8531_private { */ unsigned int base_addr; + u32 clkout_rate; + #if IS_ENABLED(CONFIG_MACSEC) /* MACsec fields: * - One SecY per device (enforced at the s/w implementation level) diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 5d2777522fb4..2f06cfa2f539 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -432,6 +432,18 @@ static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, return led_mode; } +static void vsc8531_dt_clkout_rate_get(struct phy_device *phydev) +{ + struct vsc8531_private *priv = phydev->priv; + struct device *dev = &phydev->mdio.dev; + struct device_node *of_node = dev->of_node; + + if (!of_node) + return; + + of_property_read_u32(of_node, "enet-phy-clock-out-frequency", + &priv->clkout_rate); +} #else static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) { @@ -444,6 +456,10 @@ static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, { return default_mode; } + +static void vsc8531_dt_clkout_rate_get(struct phy_device *phydev) +{ +} #endif /* CONFIG_OF_MDIO */ static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, @@ -1508,6 +1524,37 @@ static int vsc85xx_config_init(struct phy_device *phydev) return 0; } +static int vsc8531_config_init(struct phy_device *phydev) +{ + struct vsc8531_private *vsc8531 = phydev->priv; + u16 val; + int rc; + + rc = vsc85xx_config_init(phydev); + if (rc) + return rc; + + switch (vsc8531->clkout_rate) { + case 0: + val = 0; + break; + case 25000000: + val = CLKOUT_FREQ_25M | CLKOUT_ENABLE; + break; + case 50000000: + val = CLKOUT_FREQ_50M | CLKOUT_ENABLE; + break; + case 125000000: + val = CLKOUT_FREQ_125M | CLKOUT_ENABLE; + break; + default: + return -EINVAL; + } + + return phy_write_paged(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO, + MSCC_CLKOUT_CNTL, val); +} + static int vsc8584_did_interrupt(struct phy_device *phydev) { int rc = 0; @@ -1981,6 +2028,32 @@ static int vsc8514_probe(struct phy_device *phydev) vsc8531->base_addr, 0); } +static int vsc8531_probe(struct phy_device *phydev) +{ + struct vsc8531_private *vsc8531; + int rate_magic, rc; + u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY, + VSC8531_LINK_100_ACTIVITY}; + + rate_magic = vsc85xx_edge_rate_magic_get(phydev); + if (rate_magic < 0) + return rate_magic; + + rc = vsc85xx_probe_helper(phydev, default_mode, + ARRAY_SIZE(default_mode), + VSC85XX_SUPP_LED_MODES, + vsc85xx_hw_stats, + ARRAY_SIZE(vsc85xx_hw_stats)); + if (rc < 0) + return rc; + + vsc8531 = phydev->priv; + vsc8531->rate_magic = rate_magic; + vsc8531_dt_clkout_rate_get(phydev); + + return 0; +} + static int vsc8574_probe(struct phy_device *phydev) { struct vsc8531_private *vsc8531; @@ -2136,14 +2209,14 @@ static struct phy_driver vsc85xx_driver[] = { .phy_id_mask = 0xfffffff0, /* PHY_BASIC_FEATURES */ .soft_reset = &genphy_soft_reset, - .config_init = &vsc85xx_config_init, + .config_init = &vsc8531_config_init, .config_aneg = &vsc85xx_config_aneg, .read_status = &vsc85xx_read_status, .ack_interrupt = &vsc85xx_ack_interrupt, .config_intr = &vsc85xx_config_intr, .suspend = &genphy_suspend, .resume = &genphy_resume, - .probe = &vsc85xx_probe, + .probe = &vsc8531_probe, .set_wol = &vsc85xx_wol_set, .get_wol = &vsc85xx_wol_get, .get_tunable = &vsc85xx_get_tunable, @@ -2160,14 +2233,14 @@ static struct phy_driver vsc85xx_driver[] = { .phy_id_mask = 0xfffffff0, /* PHY_GBIT_FEATURES */ .soft_reset = &genphy_soft_reset, - .config_init = &vsc85xx_config_init, + .config_init = &vsc8531_config_init, .config_aneg = &vsc85xx_config_aneg, .read_status = &vsc85xx_read_status, .ack_interrupt = &vsc85xx_ack_interrupt, .config_intr = &vsc85xx_config_intr, .suspend = &genphy_suspend, .resume = &genphy_resume, - .probe = &vsc85xx_probe, + .probe = &vsc8531_probe, .set_wol = &vsc85xx_wol_set, .get_wol = &vsc85xx_wol_get, .get_tunable = &vsc85xx_get_tunable, @@ -2184,14 +2257,14 @@ static struct phy_driver vsc85xx_driver[] = { .phy_id_mask = 0xfffffff0, /* PHY_BASIC_FEATURES */ .soft_reset = &genphy_soft_reset, - .config_init = &vsc85xx_config_init, + .config_init = &vsc8531_config_init, .config_aneg = &vsc85xx_config_aneg, .read_status = &vsc85xx_read_status, .ack_interrupt = &vsc85xx_ack_interrupt, .config_intr = &vsc85xx_config_intr, .suspend = &genphy_suspend, .resume = &genphy_resume, - .probe = &vsc85xx_probe, + .probe = &vsc8531_probe, .set_wol = &vsc85xx_wol_set, .get_wol = &vsc85xx_wol_get, .get_tunable = &vsc85xx_get_tunable, @@ -2208,7 +2281,7 @@ static struct phy_driver vsc85xx_driver[] = { .phy_id_mask = 0xfffffff0, /* PHY_GBIT_FEATURES */ .soft_reset = &genphy_soft_reset, - .config_init = &vsc85xx_config_init, + .config_init = &vsc8531_config_init, .config_aneg = &vsc85xx_config_aneg, .read_status = &vsc85xx_read_status, .ack_interrupt = &vsc85xx_ack_interrupt,