From patchwork Thu Sep 21 14:51:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113270 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp1975898edb; Thu, 21 Sep 2017 07:53:12 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBLA4zO0ZGE8enSpbrg8NIBVMYRrhqfcPtZ+lIlwvtY85HBeDi+9NV/PxEYlmhbFscpOpEE X-Received: by 10.80.165.3 with SMTP id y3mr1490737edb.251.1506005592219; Thu, 21 Sep 2017 07:53:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506005592; cv=none; d=google.com; s=arc-20160816; b=P7FXTaznHn21ISwxuq7iW9d56qI+lJVM/30Mh6gU2IB/nW7G2i3vruxRRt+l1oDPXd c+cEF61VYCTx5JSkn5qvbdCLLkJP9/3O1UfUIW+PFjUtL1zzHTufEfKgMxYAiQwflCV4 sS+ces8nQAZhGt/F+8+zme1bt1EaFGIjaKiBYOM6Zu/VBNeHoL5M13fldhWqgy6RvinI Tr0Qp7rtUbcXsdr7Id6loj+opNl7RM7cX/Tj7Hftmoy0P3si0L3GvxMix7c6259a3xQP 2Gux8y1XQTpmz2xa1OhRuX0kTVVBvQaO1REaTcvlDX1LE9OmkWCywRpbQkk6AzrwT48Q wOyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=o2M+1xFxvAfixom3L3ZLehlnBJ3BkOc9vbXNcjDr+lk=; b=B/sAlswlI5MaufiGFc4K/161PxyxWQfyr35azjZx7XuDDhi7yV5w4/HdC9HPDJ8oze DED8eQ7YowdUoNrzny54A612DPnDaaUCC2fZks4qjmfIuQ6VSuVRdgCQh6IpvbcD7yxf wdjLO84SR85Q594RvTYfw6+A9YYewlAf7bHqwLsHqNfg4Nt3pbsrxOaGoFOZzBgXeGQJ hT6m3AeWlCTPX5qzCtRC3kl3tGJ+2+634Yy4+1rNW9VHxiTZexm/EYBOYPvhCze2+c+W ASRVhrvZ14D19FQgJAMW4R3G+UObCc4OHFP48B3GJIJK45PAisCLVKB6uFiuJ3nusBLd iVJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=aU4m6LLh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id q2si1870978edq.55.2017.09.21.07.53.11; Thu, 21 Sep 2017 07:53:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=aU4m6LLh; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id A09BCC22050; Thu, 21 Sep 2017 14:52:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 99C6EC2205A; Thu, 21 Sep 2017 14:52:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 757A9C22062; Thu, 21 Sep 2017 14:51:58 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 7B534C2200B for ; Thu, 21 Sep 2017 14:51:55 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEprua007898; Thu, 21 Sep 2017 09:51:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506005513; bh=mYNad7hAHpUYwuf59LDjsC/2LBlYNOq0Kg4UBERJVRA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aU4m6LLhCkQVOSyFopKIJN0XaI4yOm2Cp0urFf8EQcIW5ETdUfxNGHLgKTbfckLWO VpiGhtl5KiqV7CfQ5aHh90haUVY+J4S4TeMC7tMoP8g03gTDctrZP/0OOLFLfPD/oo ZD587Et88+HTYtCNFVFcA4/vbHZxLN7Zx1bb6rsI= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEpr8O019616; Thu, 21 Sep 2017 09:51:53 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 09:51:53 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 09:51:53 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEppr6022202; Thu, 21 Sep 2017 09:51:52 -0500 From: Jean-Jacques Hiblot To: , , , Date: Thu, 21 Sep 2017 16:51:34 +0200 Message-ID: <1506005496-8635-4-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> References: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 3/5] mmc: omap_hsmmc: Add support for DMA (ADMA2) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I The omap hsmmc host controller can have the ADMA2 feature. It brings better read and write throughput. On most SOC, the capability is read from the hl_hwinfo register. On OMAP3, DMA support is compiled out. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_mmc.h | 12 ++- drivers/mmc/omap_hsmmc.c | 203 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 211 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 77278a3..128cd81 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -29,7 +29,10 @@ struct hsmmc { #ifndef CONFIG_OMAP34XX - unsigned char res0[0x100]; + unsigned int hl_rev; + unsigned int hl_hwinfo; + unsigned int hl_sysconfig; + unsigned char res0[0xf4]; #endif unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ @@ -52,6 +55,9 @@ struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ + unsigned char res5[0x10]; + unsigned int admaes; /* 0x154 */ + unsigned int admasal; /* 0x158 */ }; struct omap_hsmmc_plat { @@ -64,6 +70,7 @@ struct omap_hsmmc_plat { /* * OMAP HS MMC Bit definitions */ +#define MADMA_EN (0x1 << 0) #define MMC_SOFTRESET (0x1 << 1) #define RESETDONE (0x1 << 0) #define NOOPENDRAIN (0x0 << 0) @@ -80,6 +87,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) #define DE_DISABLE (0x0 << 0) @@ -119,6 +127,7 @@ struct omap_hsmmc_plat { #define SDBP_PWRON (0x1 << 8) #define SDVS_1V8 (0x5 << 9) #define SDVS_3V0 (0x6 << 9) +#define DMA_SELECT (0x2 << 3) #define ICE_MASK (0x1 << 0) #define ICE_STOP (0x0 << 0) #define ICS_MASK (0x1 << 1) @@ -148,6 +157,7 @@ struct omap_hsmmc_plat { #define IE_DTO (0x01 << 20) #define IE_DCRC (0x01 << 21) #define IE_DEB (0x01 << 22) +#define IE_ADMAE (0x01 << 25) #define IE_CERR (0x01 << 28) #define IE_BADA (0x01 << 29) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 9f38687..3cac6ea 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -71,11 +72,45 @@ struct omap_hsmmc_data { int wp_gpio; #endif #endif + u8 controller_flags; +#ifndef CONFIG_OMAP34XX + struct omap_hsmmc_adma_desc *adma_desc_table; + uint desc_slot; +#endif +}; + +#ifndef CONFIG_OMAP34XX +struct omap_hsmmc_adma_desc { + u8 attr; + u8 reserved; + u16 len; + u32 addr; }; +#define ADMA_MAX_LEN 63488 + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) +#endif + /* If we fail after 1 second wait, something is really bad */ #define MAX_RETRY_MS 1000 +/* DMA transfers can take a long time if a lot a data is transfered. + * The timeout must take in account the amount of data. Let's assume + * that the time will never exceed 333 ms per MB (in other word we assume + * that the bandwidth is always above 3MB/s). + */ +#define DMA_TIMEOUT_PER_MB 333 +#define OMAP_HSMMC_USE_ADMA BIT(2) + static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); @@ -242,6 +277,11 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) return -ETIMEDOUT; } } +#ifndef CONFIG_OMAP34XX + reg_val = readl(&mmc_base->hl_hwinfo); + if (reg_val & MADMA_EN) + priv->controller_flags |= OMAP_HSMMC_USE_ADMA; +#endif writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, &mmc_base->capa); @@ -269,8 +309,8 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, - &mmc_base->ie); + IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC | + IE_CC, &mmc_base->ie); mmc_init_stream(mmc_base); @@ -322,6 +362,118 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } } + +#ifndef CONFIG_OMAP34XX +static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_adma_desc *desc; + u8 attr; + + desc = &priv->adma_desc_table[priv->desc_slot]; + + attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + if (!end) + priv->desc_slot++; + else + attr |= ADMA_DESC_ATTR_END; + + desc->len = len; + desc->addr = (u32)buf; + desc->reserved = 0; + desc->attr = attr; +} + +static void omap_hsmmc_prepare_adma_table(struct mmc *mmc, + struct mmc_data *data) +{ + uint total_len = data->blocksize * data->blocks; + uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN); + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + int i = desc_count; + char *buf; + + priv->desc_slot = 0; + priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) + memalign(ARCH_DMA_MINALIGN, desc_count * + sizeof(struct omap_hsmmc_adma_desc)); + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + while (--i) { + omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); + buf += ADMA_MAX_LEN; + total_len -= ADMA_MAX_LEN; + } + + omap_hsmmc_adma_desc(mmc, buf, total_len, true); + + flush_dcache_range((long)priv->adma_desc_table, + (long)priv->adma_desc_table + + ROUND(desc_count * + sizeof(struct omap_hsmmc_adma_desc), + ARCH_DMA_MINALIGN)); +} + +static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + char *buf; + + mmc_base = priv->base_addr; + omap_hsmmc_prepare_adma_table(mmc, data); + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + val = readl(&mmc_base->hctl); + val |= DMA_SELECT; + writel(val, &mmc_base->hctl); + + val = readl(&mmc_base->con); + val |= DMA_MASTER; + writel(val, &mmc_base->con); + + writel((u32)priv->adma_desc_table, &mmc_base->admasal); + + flush_dcache_range((u32)buf, + (u32)buf + + ROUND(data->blocksize * data->blocks, + ARCH_DMA_MINALIGN)); +} + +static void omap_hsmmc_dma_cleanup(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->con); + val &= ~DMA_MASTER; + writel(val, &mmc_base->con); + + val = readl(&mmc_base->hctl); + val &= ~DMA_SELECT; + writel(val, &mmc_base->hctl); + + kfree(priv->adma_desc_table); +} +#else +#define omap_hsmmc_adma_desc +#define omap_hsmmc_prepare_adma_table +#define omap_hsmmc_prepare_data +#define omap_hsmmc_dma_cleanup +#endif + #if !CONFIG_IS_ENABLED(DM_MMC) static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) @@ -332,6 +484,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; #endif struct hsmmc *mmc_base; unsigned int flags, mmc_stat; @@ -405,6 +559,14 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, flags |= (DP_DATA | DDIR_READ); else flags |= (DP_DATA | DDIR_WRITE); + +#ifndef CONFIG_OMAP34XX + if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && + !mmc_is_tuning_cmd(cmd->cmdidx)) { + omap_hsmmc_prepare_data(mmc, data); + flags |= DE_ENABLE; + } +#endif } writel(cmd->cmdarg, &mmc_base->arg); @@ -414,7 +576,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, start = get_timer(0); do { mmc_stat = readl(&mmc_base->stat); - if (get_timer(0) - start > MAX_RETRY_MS) { + if (get_timer(start) > MAX_RETRY_MS) { printf("%s : timeout: No status update\n", __func__); return -ETIMEDOUT; } @@ -441,6 +603,41 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, } } +#ifndef CONFIG_OMAP34XX + if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && + !mmc_is_tuning_cmd(cmd->cmdidx)) { + u32 sz_mb, timeout; + + if (mmc_stat & IE_ADMAE) { + omap_hsmmc_dma_cleanup(mmc); + return -EIO; + } + + sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20); + timeout = sz_mb * DMA_TIMEOUT_PER_MB; + if (timeout < MAX_RETRY_MS) + timeout = MAX_RETRY_MS; + + start = get_timer(0); + do { + mmc_stat = readl(&mmc_base->stat); + if (mmc_stat & TC_MASK) { + writel(readl(&mmc_base->stat) | TC_MASK, + &mmc_base->stat); + break; + } + if (get_timer(start) > timeout) { + printf("%s : DMA timeout: No status update\n", + __func__); + return -ETIMEDOUT; + } + } while (1); + + omap_hsmmc_dma_cleanup(mmc); + return 0; + } +#endif + if (data && (data->flags & MMC_DATA_READ)) { mmc_read_data(mmc_base, data->dest, data->blocksize * data->blocks); From patchwork Thu Sep 21 14:51:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113271 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp1976816edb; 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[81.169.180.215]) by mx.google.com with ESMTP id z11si1089785edh.217.2017.09.21.07.54.07; Thu, 21 Sep 2017 07:54:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=wQVAtFtx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 7312EC2208A; Thu, 21 Sep 2017 14:53:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 48B8BC22046; Thu, 21 Sep 2017 14:52:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1CCFC22046; Thu, 21 Sep 2017 14:52:01 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 3C693C2200A for ; Thu, 21 Sep 2017 14:51:58 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEpt9B005525; Thu, 21 Sep 2017 09:51:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506005515; bh=UvYeT3jm6DXxVhoq3tfLffoypOogDrMkGjFxori84dI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wQVAtFtxKl1C/q8QMY/UnyWS7Xhy8fnxwLn5zxtI5rhBl++adBV2EMrwSj5YGcIlL GHHsinnUW5F62iHjyfvANTVdUCvgqkCnUIR7iBsujGSrqGU5VJ5De47SckZQs+aybf j3gWkyQcH9/rp7g9xc0KhZi94tQ32fmqgmVQPRMM= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEptWL028024; Thu, 21 Sep 2017 09:51:55 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 09:51:55 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 09:51:55 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEprb7009818; Thu, 21 Sep 2017 09:51:54 -0500 From: Jean-Jacques Hiblot To: , , , Date: Thu, 21 Sep 2017 16:51:35 +0200 Message-ID: <1506005496-8635-5-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> References: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 4/5] mmc: omap_hsmmc: Enable Auto command (CMD12) enable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Instead of sending STOP TRANSMISSION command from MMC core, enable the auto command feature so that the Host Controller issues CMD12 automatically when last block transfer is completed. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini --- drivers/mmc/omap_hsmmc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 3cac6ea..fcda0e2 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -492,6 +492,10 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, ulong start; mmc_base = priv->base_addr; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + return 0; + start = get_timer(0); while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { if (get_timer(0) - start > MAX_RETRY_MS) { @@ -548,7 +552,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, if (data) { if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { - flags |= (MSBS_MULTIBLK | BCE_ENABLE); + flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE); data->blocksize = 512; writel(data->blocksize | (data->blocks << 16), &mmc_base->blk); From patchwork Thu Sep 21 14:51:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113272 Delivered-To: patch@linaro.org Received: by 10.80.163.150 with SMTP id s22csp1977210edb; Thu, 21 Sep 2017 07:54:34 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBdgWSRfNKWFIWw0jhYn8U41TXiau02aX3VEuAPP46jQrYcV4zBIYcBfFaOGAmL5qO/pmzk X-Received: by 10.80.194.74 with SMTP id t10mr1472688edf.199.1506005674783; Thu, 21 Sep 2017 07:54:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506005674; cv=none; d=google.com; s=arc-20160816; b=ryQM7WHxvyTR4rO6MtJxY85Bqs+vKMSbt5QW4NQZoUf4RKgMjJdAdiRP0I2KNCE7Cd iXX20z3uvtck+YRIDW8E4Qv7K6kAys86O/xsq3HCagcfqYLPusxegBgn1sHHFW8tg4NK T79j04rMieNPkwt5SGXYDfsH7Raqb/H/Y99u+qsN3f9fK4Wi7j2U9UQp23BeRxKtXbjZ gTw3JHEom29Wbf2DbIEcXIWqgyYK3NGC2bA0L4sRRb25IvTiTu7KozijQ9wZRTnhp40u a9EjQgCCAMnPxoCXjZ/o4cgLRSV8ib4th3HBLi5Z0VYpyv80m1NETwQJHZezKB9juWYe dEjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=g+4iQ1u4lR0N4zVb9tTgLQMUZYvyitYB/ZzK+sJ91HM=; b=YXrYqRUJYdWZrmiEwpBs8BQ8h/MUXHkJVmb0pW0VEZvUwFSxEce1ZlF4LMkYNNaRIB T4gOulmZo2LAUxLUlVohTc1PEoaiUyp+Buq5bBV3OcTMlF4YzgOYH8Aml6WUm1nmFgeD YI7MIBs1w5rHp8iugQioWW+m3bpyNxTTqce6gzSrGfRjdw23Id51Z3PiIOZug2ApBCrB J+T0YcDr00dANcI6ocdo4C+pGXk8P0QBWADGyFvLSUMn2btNceeCKG2YvSk9tuRyc9Mn E8H5q+wDz61r8lsJeD6dkjd4OXtDpljpNk3WzeeQfk4PHbZViCE9AJ+3oAt404WBgsE7 e2Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=P/Lgf0AE; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 35si1530149edk.487.2017.09.21.07.54.34; Thu, 21 Sep 2017 07:54:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=P/Lgf0AE; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 5A999C2208E; Thu, 21 Sep 2017 14:53:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A8FBAC21FE5; Thu, 21 Sep 2017 14:52:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1D23C2202E; Thu, 21 Sep 2017 14:52:03 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 31C23C21E48 for ; Thu, 21 Sep 2017 14:52:00 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LEpwBD001778; Thu, 21 Sep 2017 09:51:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506005518; bh=c8PJJGERbDCoJGEON2IYWWwRYrO6RKr48AOGE4O7s0Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P/Lgf0AEeUBZR5/7yeiDNP2dLDolZtMghaPc7ywVlLN0mgTx+n8hegN7Uiq5AJrYo KK+sjPQMXAXrZwvXa//6F3MTA7G6qg3QG/1Ml+g+4lEtwmImauLPPTd/MGJzNhShSs KnjH+JD0WSZD3xwbLfsYlXK4mGMPfMYEVu4nfTRc= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEpw2T019674; Thu, 21 Sep 2017 09:51:58 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 09:51:57 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 09:51:57 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LEpu6T022243; Thu, 21 Sep 2017 09:51:57 -0500 From: Jean-Jacques Hiblot To: , , , Date: Thu, 21 Sep 2017 16:51:36 +0200 Message-ID: <1506005496-8635-6-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> References: <1506005496-8635-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 5/5] mmc: omap_hsmmc: Fix incorrect bit operations for disabling a bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I omap_hsmmc driver uses "|" in a couple of places for disabling a bit. While it's okay to use it in "mmc_reg_out" (since mmc_reg_out has a _mask_ argument to take care of resetting a bit), it's incorrectly used for resetting flags in "omap_hsmmc_send_cmd". Fix it here by using "&= ~()" to reset a bit. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_mmc.h | 6 ++---- drivers/mmc/omap_hsmmc.c | 7 ++++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 128cd81..bf9de9b 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -90,10 +90,9 @@ struct omap_hsmmc_plat { #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) +#define DE_ENABLE (0x1 << 0) #define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) +#define ACEN_ENABLE (0x1 << 2) #define DDIR_OFFSET (4) #define DDIR_MASK (0x1 << 4) #define DDIR_WRITE (0x0 << 4) @@ -134,7 +133,6 @@ struct omap_hsmmc_plat { #define ICS_NOTREADY (0x0 << 1) #define ICE_OSCILLATE (0x1 << 0) #define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) #define CEN_ENABLE (0x1 << 2) #define CLKD_OFFSET (6) #define CLKD_MASK (0x3FF << 6) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fcda0e2..1c3d1a5 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -294,7 +294,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) dsor = 240; mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE); start = get_timer(0); @@ -542,7 +542,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, /* enable default flags */ flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | - MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); + MSBS_SGLEBLK); + flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); if (cmd->resp_type & MMC_RSP_CRC) flags |= CCCE_CHECK; @@ -809,7 +810,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) } mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE);