From patchwork Thu Sep 21 16:49:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 113871 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2244460qgf; Thu, 21 Sep 2017 09:49:57 -0700 (PDT) X-Received: by 10.98.211.72 with SMTP id q69mr6363207pfg.308.1506012597241; Thu, 21 Sep 2017 09:49:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506012597; cv=none; d=google.com; s=arc-20160816; b=HCOMsfQ7uNt1muZxPkQPT5t3oPUXDPH284AGbx+nfMF/yTGPcNyg6H7e0cirUimkDF LgGSlW6SNxuZWjB5MTKgV3b3DbqRQXTQi0ViEawMHhTd8CfSdcpdxtDMheMt0PMA7IOA O1vSkPzsGGP/K1ORM5TnQdg6xba7jIM6c+wDnqaGaQQ6z3lkm2nKSlbVc+e4rmhW+p5V 8+7snFgYWWylNb/Qkk7GhQdESsAOUgvn6tFfHuK6kB7sFHfyi6uQIeACgcvatcQXfmr3 XZv756N/YYSoZtwvaRcL79IfQMucX72VmQitBWS/DG9GmjhipSakmYcSCcz3kE5ViElK 5lKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Rx6gbuzzqKyqb1MIioYD1IlkFilzlDyADulu9UCwVsg=; b=TiWyG/jL2Tbdmr0jv/imQcIPGxqikeiptq7eCuh5BGAXHWqUcQ0IQ++63P2FYPSu5p l12RFm4HM+mqPRcobWQvcVfDQTn02/W/dRHK7dOkwMbjpDXJkucCZqLLCG8zK+YsX/tP rBHxflEWEYqD0+cSRmIhMmI98Ai35ZB16IGiheVk2Gak1MFLE1h4On4NbxQpyBaCFpB6 QYxfNPCpIWm/NbXwNPiU71DY2AVQkNG2sIOq+Kxhikl4ZehTUYW7AsciYjXSaDOwPLoo lFQgDfatZ+MU0PuWI/Znca0JC7wi4cJ37tLmx7cCAFdS+hIfGKfGEnmOdnAIYP5tSFUx 3xkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PbOWUSLf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3si1289159pli.371.2017.09.21.09.49.56; Thu, 21 Sep 2017 09:49:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PbOWUSLf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751892AbdIUQtw (ORCPT + 26 others); Thu, 21 Sep 2017 12:49:52 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:45405 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751861AbdIUQts (ORCPT ); Thu, 21 Sep 2017 12:49:48 -0400 Received: by mail-wm0-f48.google.com with SMTP id q124so3600777wmb.0 for ; Thu, 21 Sep 2017 09:49:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rx6gbuzzqKyqb1MIioYD1IlkFilzlDyADulu9UCwVsg=; b=PbOWUSLffaNyDG4sy2V0z8Y49AQ6M186burxTLUCxoKH7Rh6Jux7pFe4f4kslnSVd/ 7LKuPlo1PAcGkxPBEOf88gQW5iLr8j5diM6zuA66FaQfCpFvhdrrqp/3dGVGQna70Arm WC1jxq+oNjyD/gSkaHjGGOLa/gPHg6Sombasc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rx6gbuzzqKyqb1MIioYD1IlkFilzlDyADulu9UCwVsg=; b=jdSy4VrCA79xVfUJcwq3qM7JAtsYQytOSSmFI3XJYerVqh/g8ZTC4XRfUHwIJ6cHZf 2NmzdYH1KEzz2ELftnu+Z+hyf2ZrN0NMPnfEgcliqmM4pywcNLXoNtCjyADoWas7+Bar dsnxAxh7igAv5kp06i/bL1U/iaYSMq2LTAtioBqOAWLuZiXB/1irDpHi3aUStthEzNmK I/T2NPmnD+uDnfjIwFRDy5NRB7RTZQrGH7x0NwSFQskrx91tabkGfWxkULg4meG5S/FI QNFl+HLCGTiQWmCsCRcF7eVywr8c48OCB+hCLnO+6eFrmyfWO0ohNOwcnp9FVLAWWWiW mHfg== X-Gm-Message-State: AHPjjUil0ktS99nAa4500x+gILZ0RiB8UilCbfm8ykc9dsrN0f4WrDch DewBJ+q5R5XyB7LqIGrCpBQyqarQ1pY= X-Google-Smtp-Source: AOwi7QAsCU69LSkXyKmI1HKT+B4EsK+elQa8MwlzvGoF6Cmq+IxossrFnsPgQbrzJL5MgOTveOliOA== X-Received: by 10.80.226.12 with SMTP id n12mr1865113edl.290.1506012586887; Thu, 21 Sep 2017 09:49:46 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id i16sm993311edj.29.2017.09.21.09.49.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 09:49:46 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 3/7] mailbox: qcom: Move the apcs struct into a separate header Date: Thu, 21 Sep 2017 19:49:36 +0300 Message-Id: <20170921164940.20343-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move the structure shared by the APCS IPC device and its subdevices into a separate header file. Signed-off-by: Georgi Djakov --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 11 +---------- include/linux/mailbox/qcom-apcs.h | 34 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 10 deletions(-) create mode 100644 include/linux/mailbox/qcom-apcs.h diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index fd9055eacf42..50c7f6c54b74 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -20,16 +20,7 @@ #include #include #include - -#define QCOM_APCS_IPC_BITS 32 - -struct qcom_apcs_ipc { - struct mbox_controller mbox; - struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS]; - - struct regmap *regmap; - unsigned long offset; -}; +#include static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, diff --git a/include/linux/mailbox/qcom-apcs.h b/include/linux/mailbox/qcom-apcs.h new file mode 100644 index 000000000000..7e48fa2372dc --- /dev/null +++ b/include/linux/mailbox/qcom-apcs.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LINUX_QCOM_APCS_H_ +#define _LINUX_QCOM_APCS_H_ + +#define QCOM_APCS_IPC_BITS 32 + +/** + * struct qcom_apcs_ipc - APCS shared struct + * + * @mbox: mailbox controller + * @mbox_chans: array of the available communication channels + * @offset: mailbox IPC register offset + * @regmap: register map used to access APCS registers + */ +struct qcom_apcs_ipc { + struct mbox_controller mbox; + struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS]; + unsigned long offset; + struct regmap *regmap; +}; + +#endif /* _LINUX_QCOM_APCS_H_ */ From patchwork Thu Sep 21 16:49:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 113876 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2245599qgf; Thu, 21 Sep 2017 09:51:08 -0700 (PDT) X-Received: by 10.98.57.129 with SMTP id u1mr6275695pfj.197.1506012668476; Thu, 21 Sep 2017 09:51:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506012668; cv=none; d=google.com; s=arc-20160816; b=RSAs8+7gLac43gsRSXY2Qh7LNepBe8AMgrOhVgRb9hu0daGUlJneD5RzoCKnt3/BBn ZCHJlJa72YFuFm4jhfI3dDlXtC5wUAGgsdoRfYoIG83cZ+EMGzbTCyagvxBoJtejtAQV 3OVUoy1uqiiGzpk0MnqE4tKNSB2zAit1994m3KEy+SY0IFTtJIi3DJ4Ck5ls4Kk0o0eI xhL49QLFEtjqhz6dP2RRDjjHdJa5CAL5u/1+PG+wQkEck4Xt+SPSSDjcOe9FeuSfw4Rb OZjMy4pBNHohlr+dZzOdwlRobV9lLO/5aVDFNVNLuEGHJjV/+R+qR2qJf6KKURKjDssj OqdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tvRW2ZSF2XUBLk395jXryNnxHAWgY9ROCgPUaZMbC8w=; b=FVjGKH+dOtdg/9EnG4ryfEgN1R18EU69EFZtQMWJhVqqt0++KwHj1a4udClcf9i61w /xeMDn5IMI3k1heu6bQno6DZv/xp507lCWDAXd/3EpCvaxFapZqZfPPx6Nz8AjotAKpR fRb2IEU0toQt1TzihLytkbB76hiv27G0LN8EADtCiIVe9XwUJK31RsFS/f8TZds8prYW +ABadWfABhspQvEBLTfAkBCEIo4yZeRqM2ejsZ2LHND14Q8KWOP4vxyleFsU8ij5eXKv XDyk2xgyKFGjkhtCArzPXtMT0gFSAAyPtnd4CDZn1332WfWyyDivU6X8dqodgUnKysNl zfMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b0Zcf9RD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si1310791pli.46.2017.09.21.09.51.08; Thu, 21 Sep 2017 09:51:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b0Zcf9RD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752007AbdIUQvE (ORCPT + 26 others); Thu, 21 Sep 2017 12:51:04 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:49812 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751894AbdIUQtx (ORCPT ); Thu, 21 Sep 2017 12:49:53 -0400 Received: by mail-wm0-f44.google.com with SMTP id r74so3554156wme.4 for ; Thu, 21 Sep 2017 09:49:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tvRW2ZSF2XUBLk395jXryNnxHAWgY9ROCgPUaZMbC8w=; b=b0Zcf9RDIC0Z3oZ1s9sgkofgD01KIrBN86LEizAIsR/mVXQxRYo0GNaPIW9hAfCjop ofy5cQ5SZyua4B5s01KSolIYhZxXk/oMWdZqKJ1LjXh0y/aguM1D+45bXb3mvivd4gHh +Ney5sDf2VjVVMUX5tZnpC/IIdbA+m9arof9Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tvRW2ZSF2XUBLk395jXryNnxHAWgY9ROCgPUaZMbC8w=; b=lWhSvSk5PX8ywIhK1F9ODTnuK/2nMxXTvTBA4HDxysyh7pz30HOK13b1XA+vEy0X+a OCr7XwHhIEmZOzYhHIqMQzxUPr7V4PZ6X4HTVcY6xKiNNZl5FZHNc0CjzZXMkJ/SeY+h akVRnmLKy/AbAMt0N9NhUp0EOavCwWVWA+JYKS40cuuQOC/UfzXkVQRPJ/mKd6ybOLs8 wpkkisq5qaGQ/pAUmR/wE8wGDvivA0x0uPLbHhNX50YfWxpyKWwFnaSTBeVV+ZGKwG7i AdPW0vq3NR7A07QynUvZ3mm3lF/C6Endu/QBzm2dsyXOgWID8IPL1BLQVC2igXRFGY/s MaNA== X-Gm-Message-State: AHPjjUiUl/8ScSWAmC0fYoko5mU7NcYw95HNex5lyr5lC/t65cEOR6F3 lsVoNFBqbjYjl0oR1iaWnAV+9Q== X-Google-Smtp-Source: AOwi7QAypNwlOOYlEjOs0ajb8tXIb9ZkYNxbcZlTSqM44NPoySFxbp9jq8FxQW0tBkX12A4ZD8YP8w== X-Received: by 10.80.241.22 with SMTP id w22mr1865215edl.188.1506012591954; Thu, 21 Sep 2017 09:49:51 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id i16sm993311edj.29.2017.09.21.09.49.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 09:49:51 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 6/7] dt-bindings: clock: Document qcom,apcs binding Date: Thu, 21 Sep 2017 19:49:39 +0300 Message-Id: <20170921164940.20343-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device-tree binding documentation for the Qualcom APCS clock controller. This clock controller is a mux and half-integer divider and provides the clock for the application CPU. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,apcs.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt diff --git a/Documentation/devicetree/bindings/clock/qcom,apcs.txt b/Documentation/devicetree/bindings/clock/qcom,apcs.txt new file mode 100644 index 000000000000..8083bcc33ebe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,apcs.txt @@ -0,0 +1,27 @@ +Qualcomm APCS Clock Controller Binding +-------------------------------------- +The APCS hardware block provides a combined mux and half-integer divider +functionality. It is used for a main CPU clock mux on MSM8916 platforms. + +Required properties : +- compatible : shall contain only one of the following: + + "qcom,msm8916-apcs-clk" + +- clocks : shall be the phandle to the main input CPU PLL clock + +- #clock-cells : must be set to <0> + +Example: + + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + + apcs_clk: apcs_clk { + compatible = "qcom,msm8916-apcs-clk"; + clocks = <&a53pll>; + #clock-cells = <0>; + }; + }; From patchwork Thu Sep 21 16:49:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 113874 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2244838qgf; Thu, 21 Sep 2017 09:50:20 -0700 (PDT) X-Received: by 10.98.198.78 with SMTP id m75mr6327325pfg.76.1506012620518; Thu, 21 Sep 2017 09:50:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506012620; cv=none; d=google.com; s=arc-20160816; b=si9yQHXNOxQOLlVtjyPc+YiBw7l/I8AsB8GyciPOhzczoS91xWJLnYJ83NTa7BeQEv nKfh1DzhgPxFQuwI39GGwtsTDbn0XoDfWRuyOxJMF7cIL4mq4Tz15VxAdUIXEw0QIa73 xXgJod2qQ7JRPxuWISLhOYfknLCF51FnrbwTvwVtsbfgiR7snBJwdd22F5dLTeahiLoC KDJGRLb2Fxzh2Q2YYara84D+o78vKSlYzIiqS8jviGKaJaLBdgVkqLUev2z830MHihW3 ABSluwFqkiTZCb7040eT/BP8tj6pl41UVl3nSgJjONsoivbvjSK4bsb5iKFKFw7zmbv4 BKTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=j66LXEhXSnaMdSXfOE/mlR3g95FPmyUZTmIucpMCrV0=; b=cF8N+oHz1RxlOD/lQ8KnuzLVQdLM4H4ARPslLAWqM4uFitKElfF81IgLVnSKAGbB4R YfkKx5QFqYN9UE7gjJkNUrclkKhW0IR+lgTTtQlnVVIIKsL8Nq0nSflksn9jvx2c/Wfp PjQFucLeP97x0S7aGGEVX/qBCaeibr+0Th/pBaARm9RowILz2evPFePmlaYfl8/OWKs4 L05tQYbtZlfPUFSeUKDd/b1KBCa6gavR5rLgC3AXectKatFMT6n4Th3ArhJ/VauokUo8 NAFvhj00LvOOeHSOsCpk7QdgnXrWJaPLqLEG+o7zM1Gp1uVqMGucfB4M0a89f5sG3V6N rwUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JfFZ435H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v67si1240168pfd.527.2017.09.21.09.50.20; Thu, 21 Sep 2017 09:50:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JfFZ435H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751946AbdIUQuS (ORCPT + 26 others); Thu, 21 Sep 2017 12:50:18 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:47422 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751902AbdIUQtz (ORCPT ); Thu, 21 Sep 2017 12:49:55 -0400 Received: by mail-wm0-f50.google.com with SMTP id r136so3582853wmf.2 for ; Thu, 21 Sep 2017 09:49:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j66LXEhXSnaMdSXfOE/mlR3g95FPmyUZTmIucpMCrV0=; b=JfFZ435Hg6yJDoD7LpF/EWwUeRh6/gkBAWnfq+i7t1ZshZOD7EHl3VCYrwAvEi0+DO pL9BchqiRevncZV/54tAeQvWWvGF4DweDKukCAg6zZUGnxg+MQwQFT5WZFKsaeRY6IfV Zl55eE0HxL5w/p4+Iq1mkdFShTXIaFR7i1Oxo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j66LXEhXSnaMdSXfOE/mlR3g95FPmyUZTmIucpMCrV0=; b=UCb620PAGJj7ZfpBea57EkL3J/QSSsULeO7bgPAUO/d4LDo4WjFFVu37X1lUP899cz Gd6oZJhZfx3hYJYzWb5PGt7GQVRvWqt2RZZr9UNAs/6RFV3kZxRSAPcZ1rWO/LG+aRzO wr2hCu9qz8qTQFWs4UgukYA40L8vzCU6a+Oni1Rqb7pnRg7RERirsFUbnW+osFbpKJhp A7dXUutFmqUI1EOtB97otTUcOxn5JkH8PH95GnrIL7LKaGScrWZP3DOBw0LIAUeEQl9X 2GcNbMYdg7JBy4l877tvY25Nno411tA2yWehOVGnVW7MZcNi76Ha/LU+42al1/t6f1bU EZgw== X-Gm-Message-State: AHPjjUiChIlqeLhhfJFcWHWtln7Lr/Ks6nM04eITQbno/0rsiOn1xp// pTsWXMqyeigEA4RTG2e2fljVmLKRNiY= X-Google-Smtp-Source: AOwi7QAwVVpCxbxqlfe9Jitt+Q2bTjpmznC1WLZUGGYiN3ivJ9zVrcX5FfxmADdbnNrEx26bs5psTA== X-Received: by 10.80.165.82 with SMTP id z18mr1848074edb.172.1506012593628; Thu, 21 Sep 2017 09:49:53 -0700 (PDT) Received: from mms-0441.qualcomm.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id i16sm993311edj.29.2017.09.21.09.49.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Sep 2017 09:49:52 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 7/7] clk: qcom: Add APCS clock controller support Date: Thu, 21 Sep 2017 19:49:40 +0300 Message-Id: <20170921164940.20343-8-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apcs-msm8916.c | 172 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 184 insertions(+) create mode 100644 drivers/clk/qcom/apcs-msm8916.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 81ac7b9378fe..255023b439c9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -22,6 +22,17 @@ config QCOM_A53PLL Say Y if you want to support higher CPU frequencies on MSM8916 devices. +config QCOM_CLK_APCS_MSM8916 + bool "MSM8916 APCS Clock Controller" + depends on COMMON_CLK_QCOM + depends on QCOM_APCS_IPC + default ARCH_QCOM + help + Support for the APCS Clock Controller on msm8916 devices. The + APCS is managing the mux and divider which feeds the CPUs. + Say Y if you want to support CPU frequency scaling on devices + such as msm8916. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ac38c2b21847..9b49fe77654a 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -33,5 +33,6 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o +obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c new file mode 100644 index 000000000000..c297d9cb34b2 --- /dev/null +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2017, Linaro Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A53 PLL is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = __mux_div_set_src_div(md, 4, 3); + + return notifier_from_errno(ret); +} + +static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_regmap_mux_div *a53cc; + struct qcom_apcs_ipc *apcs; + struct clk_init_data init = { }; + int ret; + + apcs = dev_get_drvdata(dev->parent); + + if (IS_ERR(apcs->regmap)) { + ret = PTR_ERR(apcs->regmap); + dev_err(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + init.name = "a53mux"; + init.parent_names = gpll0_a53cc; + init.num_parents = ARRAY_SIZE(gpll0_a53cc); + init.ops = &clk_regmap_mux_div_ops; + init.flags = CLK_SET_RATE_PARENT; + + a53cc->clkr.hw.init = &init; + a53cc->clkr.regmap = apcs->regmap; + a53cc->reg_offset = 0x50; + a53cc->hid_width = 5; + a53cc->hid_shift = 0; + a53cc->src_width = 3; + a53cc->src_shift = 8; + a53cc->parent_map = gpll0_a53cc_map; + + a53cc->pclk = devm_clk_get(dev, NULL); + if (IS_ERR(a53cc->pclk)) { + ret = PTR_ERR(a53cc->pclk); + dev_err(dev, "failed to get clk: %d\n", ret); + return ret; + } + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + ret = devm_clk_register_regmap(dev, &a53cc->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &a53cc->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, a53cc); + + return 0; + +err: + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + return ret; +} + +static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev) +{ + struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev); + + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +static const struct of_device_id qcom_apcs_msm8916_clk_of_match[] = { + { .compatible = "qcom,msm8916-apcs-clk" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_apcs_msm8916_clk_of_match); + +static struct platform_driver qcom_apcs_msm8916_clk_driver = { + .probe = qcom_apcs_msm8916_clk_probe, + .remove = qcom_apcs_msm8916_clk_remove, + .driver = { + .name = "qcom_apcs_msm8916_clk", + .of_match_table = qcom_apcs_msm8916_clk_of_match, + }, +}; + +static int __init qcom_apcs_msm8916_clk_init(void) +{ + return platform_driver_register(&qcom_apcs_msm8916_clk_driver); +} +core_initcall(qcom_apcs_msm8916_clk_init); + +static void __exit qcom_apcs_msm8916_clk_exit(void) +{ + platform_driver_unregister(&qcom_apcs_msm8916_clk_driver); +} +module_exit(qcom_apcs_msm8916_clk_exit); + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");