From patchwork Fri Jul 3 16:53:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231227 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2559389ilg; Fri, 3 Jul 2020 09:54:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzS+hG05s3OINKieNHC1EMLeTcKtA6CTNgiBCGsLgBWMPMmufGNMLo4w2TqAZbTdUtWl596 X-Received: by 2002:a25:8284:: with SMTP id r4mr55799883ybk.351.1593795294544; Fri, 03 Jul 2020 09:54:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795294; cv=none; d=google.com; s=arc-20160816; b=VbB0hCtd+aU+8jEWScC0UCyijC4HrL10S4yog+S6Dc+UQhnZXZMfYQib2G+45zfVZV W5L5dMxukAveXw4MxoYLbtJxX8RKYOK9XDM7f8IrBAc8f94ONVN//4TX8ZAWc0DUpdMv m4eE1vDunNICUepg7YB6l2CMsNhyiUNH8DwQMkHN/13W1Mt9Erank0klbjv3S/J5VQqx ckzq9RpgKuoI9wsOi0kh+BS6sIY1eTuxflDWbNUM1vHQSHiha6ifyc89wsMYxrJ1Ea+j vCw7elp4nFbP+OjPZJpgOAGsXykFybY1uTys9ficKQR6QvwWkYpgbjiHzvu+ADSbLIco lBHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I7r9/QjL8RuKBxpXMjuZlnSwNbq823MwcTI3Yaf9uyQ=; b=ZK2NIWmvJuq70CaRb3uj01dlUqAaI6BpWkvDif58JQp2CSloqRon4VIP72Jp2YVFEF EJk6ZyRIcNKhRtdancEX9yS2YN1TXfDtaRv3v7ZW2iPaJ8vQD+lAk9N0WSfafDbGTltC gCt7ssaGYAJ4pdqNCid+73eJoIs8zquVSlO9w+3es5E4R1pA2Z38USr2PkDGSjdPFZtd TwhtEEv1V4jQVm/03Mm+btNaMs9KYughqdZEOitzRxAGOirCaSyGrHqG/a4VqgJocVoh Rbcvdt0qQXldps3KRzx2C0FXe7PQ3J0M4+9iOc15zjJq9Euc6tWruNOud2+nYZYpsGVu iKlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QqMnKaq2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d93si12166616ybi.258.2020.07.03.09.54.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:54:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QqMnKaq2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrOxh-0004S3-Tw for patch@linaro.org; Fri, 03 Jul 2020 12:54:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx2-0004Rk-57 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:12 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46057) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx0-0005dm-Ca for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:11 -0400 Received: by mail-wr1-x432.google.com with SMTP id s10so33382521wrw.12 for ; Fri, 03 Jul 2020 09:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=I7r9/QjL8RuKBxpXMjuZlnSwNbq823MwcTI3Yaf9uyQ=; b=QqMnKaq2Lr9LgyPgpIG3mRvCf2u2bWUfVV8lhIgkYVYjD8y+nsM/lZzrdcp7ijiAvh im/ExmavNO6GM10W5yzPttOQHQkE81eD3xSoH+Y4lds0HSlx9sqaS8i4eE3FD8YKYZs3 tR2kWzDvODxosMFVZ1qZQB7QXjFX2lw9ZAZvwf5B7nOojT6gMQaKUlJv6Giwx+45TZ15 djsSZcuY7wv0IYUfTKOeOlTX2LAWR55QcsLLM2ZRmITz8XgE5FrS66q1wU052/IlOf/7 JmXjUuLnklCOrC2IhN3JGxktLqQtAApOcOAjajyNTRnmUunrF2T+zMGFSuAOcdLChBAU 7nJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I7r9/QjL8RuKBxpXMjuZlnSwNbq823MwcTI3Yaf9uyQ=; b=eSVFdjNrRntoiNIuzwOKwLjGmXXIboz8DjERkhxLWCRJecgJIbtKATxlVg79ejcsdY YPNtJ1it11J35NNlaWHSv4Z198PLHTjiyWkZbM74i0xdHOyvKAhhALTyfK724RG36pNw vZHg7ooZTUvPL5j64zhg9/ijzA4Uhooomhq3JWV3DXwsVheMPv5JyQOvsUn4JfmSyerZ qCby22CFu5UNGbbIAMdCuuWClnWlUBtu9vHk4wIu/6QSM6cB4sBr8HWTbSvyPpiZltKh 2yByHKIuojHk7EqzcdTfhKdhK5sydW6lDFmLXL6eW/D6LEfCH1TA8xaTsnQZEti2WKP2 jVOw== X-Gm-Message-State: AOAM531v9oUAhLRep+hGsIQWeHeHrxUYjxo2v4qwcfEYL0IIh/NGjca/ Kda0i1MJ1REAbm9rCwloXE4Rkb6sMkalzQ== X-Received: by 2002:adf:a3d0:: with SMTP id m16mr1823354wrb.232.1593795248424; Fri, 03 Jul 2020 09:54:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/34] Add a phy-num property to the i.MX FEC emulator Date: Fri, 3 Jul 2020 17:53:32 +0100 Message-Id: <20200703165405.17672-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Christophe Dubois We need a solution to use an Ethernet PHY that is not the first device on the MDIO bus (device 0 on MDIO bus). As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but only one MDIO bus on which the 2 related PHY are connected but at unique addresses. Signed-off-by: Jean-Christophe Dubois Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/net/imx_fec.h | 1 + hw/net/imx_fec.c | 24 +++++++++++++++++------- hw/net/trace-events | 4 ++-- 3 files changed, 20 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 7b3faa40194..9f03034b893 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -268,6 +268,7 @@ typedef struct IMXFECState { uint32_t phy_advertise; uint32_t phy_int; uint32_t phy_int_mask; + uint32_t phy_num; bool is_fec; diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index eefedc252de..2c148040414 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -280,12 +280,16 @@ static void imx_phy_reset(IMXFECState *s) static uint32_t imx_phy_read(IMXFECState *s, int reg) { uint32_t val; + uint32_t phy = reg / 32; - if (reg > 31) { - /* we only advertise one phy */ + if (phy != s->phy_num) { + qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n", + TYPE_IMX_FEC, __func__, phy); return 0; } + reg %= 32; + switch (reg) { case 0: /* Basic Control */ val = s->phy_control; @@ -331,20 +335,25 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) break; } - trace_imx_phy_read(val, reg); + trace_imx_phy_read(val, phy, reg); return val; } static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) { - trace_imx_phy_write(val, reg); + uint32_t phy = reg / 32; - if (reg > 31) { - /* we only advertise one phy */ + if (phy != s->phy_num) { + qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n", + TYPE_IMX_FEC, __func__, phy); return; } + reg %= 32; + + trace_imx_phy_write(val, phy, reg); + switch (reg) { case 0: /* Basic Control */ if (val & 0x8000) { @@ -926,7 +935,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, extract32(value, 18, 10))); } else { - /* This a write operation */ + /* This is a write operation */ imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); } /* raise the interrupt as the PHY operation is done */ @@ -1315,6 +1324,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp) static Property imx_eth_properties[] = { DEFINE_NIC_PROPERTIES(IMXFECState, conf), DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1), + DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/net/trace-events b/hw/net/trace-events index e6875c4c0f6..5db45456d92 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -413,8 +413,8 @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" # imx_fec.c -imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]" -imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]" +imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" +imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" imx_phy_update_link(const char *s) "%s" imx_phy_reset(void) "" imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" From patchwork Fri Jul 3 16:53:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231229 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2560943ilg; Fri, 3 Jul 2020 09:57:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4IOOAD+88RlN3T3AE6aiWSH91H2crcz9+fzb3IIdKC3bYsCmmLeJFboj9Dwi4pTYc5RX8 X-Received: by 2002:a25:c306:: with SMTP id t6mr57622731ybf.297.1593795445775; Fri, 03 Jul 2020 09:57:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795445; cv=none; d=google.com; s=arc-20160816; b=D2ZPsia5fMrX8IW1UKk8EkRhy99DZfchm8FsxS+gT0LWbt7NGf/kAH3zlp5t1uZIrf LqKrjpSIKcovNq6Fx71d3klBZ7+3iNKgYe8M6GJnfxxrCileT4Kc/ih78acam0V9L8Dl Oeo6PFXXgmWfGqxCqXjEBR5IZGbKs8iKF3D/DtAjq0qBAHxRcxE7Bov54815QfVPVIkK uFLMUmUBMh2alkOlK66unpNIXYL9xyoreG0ssnmjhtpcZ4mUA8TZiknIbx2CLjBsLO2b ApDx9oWU88dUts/PdcGoNaKKUMFbkXvpxLRUa4nNKe8rb72rppVTp4CzVPSI0nqOZvjx Rldg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=V7NsJejd61OpIth+3pGg1pvBG9TXuRoNl2pNDC28re4=; b=UkwLDBsKi2w+GdaHJI5srH7fPB84my56vdxpffZ2tysS//k+3rorcJEriq78aHP4QV g8LZV0jo5YDaC5pMtIR36GPP0figUr0TYiUEdXL0V4JiQWUsBmpj1nG9pIxa4lpseRxD /DibjQMqqrS4ZafNQ6mqs59esLdm7EHYzJDNGhIwcclSPcjStuSnObhAvmLjxEQSoENP 33/OsMIO5B/aTAEO2kXPAhBbitq2igqolEm7tEfq3u8S2RK1P0PjFIwiYFrHZhusdv6O WMgABrx3BVba6xZqIQb6dylSCg8A0mjmkIukVj6QqwVogF5t+WfMS8GvOd+Igv9Lmu0S mt1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dOawTcEU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l2si18798158ybt.63.2020.07.03.09.57.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:57:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dOawTcEU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP09-0008G6-7S for patch@linaro.org; Fri, 03 Jul 2020 12:57:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx3-0004S6-DI for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:13 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:43466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx1-0005dq-Nn for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:13 -0400 Received: by mail-wr1-x42f.google.com with SMTP id j4so30986269wrp.10 for ; Fri, 03 Jul 2020 09:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V7NsJejd61OpIth+3pGg1pvBG9TXuRoNl2pNDC28re4=; b=dOawTcEUOANfu1qkRi1pyjIWUyRD9xe1ObNVFhhbxKA/VNye68sEpIm0WhMLGcMsq/ xKCP2Z+HgJA4E18ejo6avqO2MedLGxzpgTuaxSP6hxkaDJbeB4tXbEcJZb6ufiWtbzqo 7JJnlrdoaPLX7pfNrQQFqoQRHx2XAZgVkNUY83lVfNo3xhYf//2aQRYqdK4WFGZrWPj7 2SCnGfqDCXVX13FpF0QvHwfJEhoWlgK8uXk7XTat0WaPrfPoQ+QMYgd5UzSFat6Az9lN AwvcaW/GlONsR5tBU/1Hddy3SUUvHd662YJWP3zpiq31DZC5G2c9LRKb5mJD4W9edI3T gDEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V7NsJejd61OpIth+3pGg1pvBG9TXuRoNl2pNDC28re4=; b=APPrQA+bwfOOOCyYldOIaMRwe5kq0A000BlCdpRuIjCJ0R4LaIVl31r72vyfsFYzsh a8d2/VmICcTOaglhwC3B/bCVHa5DR19ooeSnFuWz5WlE0iMOLbGsMcJprQ6kSmyn/069 pqV9nORQ/HokRvGRhpWaE6J1zTN8ZQeQXtY/YVhJR+FTVZEEtQUQeelBMph2yc0XNI0L Gzhx9PJzVtCXNY71Hl7s9QruJ1WsYfUDbCtxCSAl5COq7Dka4dVXa+ZwKDxeEa0I3TTD nWu00AEY1b9nPSeL+jk5UOSQQr0b196Z6/lOyJPHJSVaQJDX31DZ+69KkFLG/5321iJb Ew0g== X-Gm-Message-State: AOAM5301zgdO+MnAWceavt6cSevPxIwO7UdggbQ+9z/lQ9H89Kf+VyJV rv4Nlfra1gjl7YhYzFjGBJQtWqJgfeRzGg== X-Received: by 2002:a5d:68cc:: with SMTP id p12mr37212242wrw.111.1593795249550; Fri, 03 Jul 2020 09:54:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/34] Add the ability to select a different PHY for each i.MX6UL FEC interface Date: Fri, 3 Jul 2020 17:53:33 +0100 Message-Id: <20200703165405.17672-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Christophe Dubois Add properties to the i.MX6UL processor to be able to select a particular PHY on the MDIO bus for each FEC device. Signed-off-by: Jean-Christophe Dubois Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 2 ++ hw/arm/fsl-imx6ul.c | 10 ++++++++++ 2 files changed, 12 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 37c89cc5f92..fcbaf3dc861 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -87,6 +87,8 @@ typedef struct FslIMX6ULState { MemoryRegion caam; MemoryRegion ocram; MemoryRegion ocram_alias; + + uint32_t phy_num[FSL_IMX6UL_NUM_ETHS]; } FslIMX6ULState; enum FslIMX6ULMemoryMap { diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 6446034711e..51b2f256ec8 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -427,6 +427,9 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_ENET2_TIMER_IRQ, }; + object_property_set_uint(OBJECT(&s->eth[i]), + s->phy_num[i], + "phy-num", &error_abort); object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX6UL_ETH_NUM_TX_RINGS, "tx-ring-num", &error_abort); @@ -607,10 +610,17 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); } +static Property fsl_imx6ul_properties[] = { + DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), + DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), + DEFINE_PROP_END_OF_LIST(), +}; + static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + device_class_set_props(dc, fsl_imx6ul_properties); dc->realize = fsl_imx6ul_realize; dc->desc = "i.MX6UL SOC"; /* Reason: Uses serial_hds and nd_table in realize() directly */ From patchwork Fri Jul 3 16:53:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231225 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2559107ilg; Fri, 3 Jul 2020 09:54:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqvHv7cetiiKCWUCV5IRbSh/G12/h2EM+2uzNb/Kq1gkVe+b8QQrOpm8M3PDupJy3Re2uo X-Received: by 2002:a25:8284:: with SMTP id r4mr55797483ybk.351.1593795268237; Fri, 03 Jul 2020 09:54:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795268; cv=none; d=google.com; s=arc-20160816; b=Tmf6ZUgLJyCmn7tyigYjJzzBWYKVqxUuOCuJPPkz6G48krgZSMkHkC/QhWUieJamKD ugYClqvJ0u0rT60l43LIKFIdpSgEuGPJLGR8z9fjk73NWnSjgpNk6dQbprhQyXJ9RpJG FP5G3InU4QWFHzDlR/PUStdP+f0UeDEfm5/8F6uHhvC1Tnah2i+zGeNdJaYTX/3fOjOC PcHh6LuJgO9TVfzkuJmBsmKLv8nfeD0YWloSbGsNBWZCcpu+8bVgYwoRxdLXAPEHaLaU G139rEbK4iC8dGzp18Y520mrGWG09M3cbBNYgDQoiSGADlVzRkfMMU/pyJ9jSdARVjTm /yrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=tVDQEPi+TS63vgwsfA18+eSs84y3JoHZ/7TtH2x5MrM=; b=pAQu95lZkjA2gZsekQoUB4VyXmPgpfVibJXxAOzF6cOd+/wNoHSxIHh9SgAxljAQoa R9tR0fR8vI0REbPMsr2kvkw6swgHauIjHyRGa3xgNnR8v1wLHd6leyR3dFUheazCAjxk L9A9BdnunhN4xmFxVMNLVo+s393QQjmYwMo+ocw1OI5xim1kciN2g/iAPIITMFNo0CO3 sQHEjXHJ1vpwG9IiQn4jQAwgEGN/NRuYjZTY8vDxBpDyMXV/wXtcdfeSG6nxJawOu2TC jLq7GpJjxUX6olOWIZnHgllrERUOw3Q72RNxM6gA/Fl57ffs/nha7yWg6B817fvugfZV U+dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tW4eUXgl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a4si2023419ybr.383.2020.07.03.09.54.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:54:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tW4eUXgl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54536 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrOxH-0004Vc-Hz for patch@linaro.org; Fri, 03 Jul 2020 12:54:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49880) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx3-0004Sk-Qj for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:13 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:35270) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx2-0005e2-B1 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:13 -0400 Received: by mail-wm1-x344.google.com with SMTP id l2so33240435wmf.0 for ; Fri, 03 Jul 2020 09:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tVDQEPi+TS63vgwsfA18+eSs84y3JoHZ/7TtH2x5MrM=; b=tW4eUXglfEFCNyUou4Nboc2Ti5A+uELaeV5qx/R8yn2comBfaofNIibICAJmvhhmyo jnRDm2kUJFICcSwUCwklaF5zev2+MuCYPQYnaQlnDWXcTv2ciNpnvw1edki0nr/WdDp1 BQl/WVlIaVqW8rcyKZ9fz96yFior8RVPsq39fTOcwCBiPPjEzU0qosrLTCPykOzkkA2e iZqp3COzIxnMYBAvEpbwvWoi3x3BjoPJBilSQrlmqXzkbv9ZvvErHVXwl+GcbSpg/1Go Y8ahuOFy0UVU9VwVEaNt7GFHi/7YyvO3IoxFOl97ULWqz7gRSNqEZxuyGIgFIh7HYE/j w6Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tVDQEPi+TS63vgwsfA18+eSs84y3JoHZ/7TtH2x5MrM=; b=qNx6XMN9YrsbEpTOFRsffXIwf3kLU9AzIhZFUMr+Mdj7hkP69F2wFTaWoy250Ss7XN fhn2n534b3Nw6uVaTVP6QrtgQhIbE0wumMNFg7ZP95lV35K8UtRtyiD7fz6Z2HJciNmx rzr1yHLFAZ3C2yegfJCftRBIhHzoN5Q7CMFCE2aEsU4RyaQJeZlcJ8gEteAOa9BcWPrL 9Zy9/E3IWzawTUbC5HtuoXFkcRmp9JhZpZbMgAQIafEps5YV0rPOZP0PARB5oApD3m/3 6eB6o0JENMFrruemypEsw3W/dUde3i8VlPeGa1Qh9sddr9zZmknPPLt+ZlVJUmNXHpei RwCw== X-Gm-Message-State: AOAM533kHsrN+9uLQhyQtZ1hhYdovSh7ddsKif63Cwadxl/DlDrcNF0D sXM4TK/wgDir29B8le/s3FVIM67ng3L/yA== X-Received: by 2002:a1c:3dc3:: with SMTP id k186mr39359357wma.66.1593795250638; Fri, 03 Jul 2020 09:54:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/34] Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board. Date: Fri, 3 Jul 2020 17:53:34 +0100 Message-Id: <20200703165405.17672-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Christophe Dubois The i.MX6UL EVK 14x14 board uses: - PHY 2 for FEC 1 - PHY 1 for FEC 2 Signed-off-by: Jean-Christophe Dubois Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/mcimx6ul-evk.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.20.1 diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 2f845cedfce..9033d3f8f38 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -40,6 +40,8 @@ static void mcimx6ul_evk_init(MachineState *machine) s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL)); object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); + object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal); + object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal); qdev_realize(DEVICE(s), NULL, &error_fatal); memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR, From patchwork Fri Jul 3 16:53:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231226 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2559139ilg; Fri, 3 Jul 2020 09:54:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwua1RC9qio+4MBHDBitCNjN2mz5nYXBG7HfpCVD6F8ijog+kfULv1lRdS2tS/0/arit0n0 X-Received: by 2002:a25:7c87:: with SMTP id x129mr55719685ybc.130.1593795271443; Fri, 03 Jul 2020 09:54:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795271; cv=none; d=google.com; s=arc-20160816; b=JSOhbyU/fbCbTFGMg0sADTlEv9D6BhZ0gz7KvJXUO+DrSLlmlcCT4+1zQlSQWoPmsc z2BBu2iLpbfn7f8wlxwoHynysMD6qa+AzN76sSk6FGTTP2VwCQRd8TpXyXFyoJsxPHRw A/vuyfGBrsBw1PzBUbhj6Irzu7jU6Kydsrw3gSUHRiIAQ7a0hyv6kbUYy+YW/tMDC9pN qyn2hl7FOytS98Li6q7t5GEkdyJKNxTjM/v+ICto4hQp0Mq0i2o83bdSr+C6XS4pm4bv S3Kh4cR5XI/ULtfQ+oLyf89TymTHCKl9yV7HUG48ILaoqpCkrNJVaJhN8hK569KkJX9o bWIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UmfUqdz533axEYBvzdXLChRzYDtVznAZewi3we7ufag=; b=CP5IPHfa6MI0M3dIysug94RpBitInp0HEkp6bxhQ0g5mLILmUsltGoHIYbQA+mZlb8 ioc+8MhEm2ocjn6LbXlQGPBc2WLTyPDUe+Kc1fc9jQULk984c1FbyVooLkUFGrpmobvt Wpmr8NZe2kNLAA0VCQAKV3Bl7SaaZ3o+Lq7BKMwZTcHpRlFnCp20VmNa4yRTrQN1VsMA PeiHkaghJl+akSjArinqquLXCrYSDMYwPOk60f8oSwNkwoYqnQR3+QRVUqzEpuS6Tg7u vTiei3O4PNsR9PQOHcS1fVxgRe+45ErabK6O/NMzgXnlbhEBiHekOv9xGKX+qjCXCRWD FJiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YI000V4P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j82si11991297ybj.1.2020.07.03.09.54.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:54:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YI000V4P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrOxK-0004b6-RR for patch@linaro.org; Fri, 03 Jul 2020 12:54:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx5-0004WI-Ko for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:15 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:37376) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx3-0005eJ-JF for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:15 -0400 Received: by mail-wm1-x332.google.com with SMTP id o2so34724247wmh.2 for ; Fri, 03 Jul 2020 09:54:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UmfUqdz533axEYBvzdXLChRzYDtVznAZewi3we7ufag=; b=YI000V4PXmcecu3NTOaXgqVUj58QkGSH1rllGbMSzOiOFhbXC5v84neUxzQgJ++pE+ prmE3lIxijqHt7B+uqcEGURmctdtmUzqMriLWbkeQQ0MHF1Xeqp7x8+WIIIXmF60d6/p o2i3OkshQpnUsTrq0qrV9VIyEtwPmLhk5VUl1gzzsWVp3QfPQv4r8/KceklSUW0uxKXh vVuQFSLKZLwJqCnKnpMjX5MTbnMzToj4fZvTT5kRIhRSrFIJ6Wb9HPOJrDLh2yVY+TsP t+1SU5h/jkBGoIf4mqAkIXs2kNz0V9pXCtn1PUdJRoO8OFouthgKvjoF3OYzZxjpKzbJ 5QFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UmfUqdz533axEYBvzdXLChRzYDtVznAZewi3we7ufag=; b=JXtesrx1uRhGqbFbZioP08JiZ3oACIbbd8h43RdmY3w/9cfCuxP1EMbkZ7kGHCaYT9 v+wu2QWsZZUPIT2WkPMQnVS4u/LIptXSN8vqECCtfJhK/+ffPh4JMJv7Wk877Fz3HKKu hcvglsT+PIhgtGvB4J1Bj4iHFFhSskL6FQSZBPyiMhlL/f5N7OgieGQ2839LFlBAsnaP mDCDquYAVWt6nZDjx6p0YHdBfx+RBxNpR0ZkMKERSJKYO+Hwr3/19hufS78H+r1kOjPb lnjX1+NoBFFtU2RmpwBFH4PBOfnNz5YtTWf7biuINz+f7IqFPvxTkVwiPqq8qIholjfc QPRw== X-Gm-Message-State: AOAM530urf/RNRgsVZwppiyW8rqCLGqUv9VeC1HFPgQkCPwBwI1S67eK H1lvhlSGaVK2PGNAoRN+BoixvtIoMAYcSA== X-Received: by 2002:a1c:1f09:: with SMTP id f9mr39394557wmf.137.1593795251848; Fri, 03 Jul 2020 09:54:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/34] qdev: Introduce DEFINE_PROP_RESERVED_REGION Date: Fri, 3 Jul 2020 17:53:35 +0100 Message-Id: <20200703165405.17672-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger Introduce a new property defining a reserved region: ::. This will be used to encode reserved IOVA regions. For instance, in virtio-iommu use case, reserved IOVA regions will be passed by the machine code to the virtio-iommu-pci device (an array of those). The type of the reserved region will match the virtio_iommu_probe_resv_mem subtype value: - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0) - VIRTIO_IOMMU_RESV_MEM_T_MSI (1) on PC/Q35 machine, this will be used to inform the virtio-iommu-pci device it should bypass the MSI region. The reserved region will be: 0xfee00000:0xfeefffff:1. On ARM, we can declare the ITS MSI doorbell as an MSI region to prevent MSIs from being mapped on guest side. Signed-off-by: Eric Auger Reviewed-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Message-id: 20200629070404.10969-2-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/exec/memory.h | 6 +++ include/hw/qdev-properties.h | 3 ++ include/qemu/typedefs.h | 1 + hw/core/qdev-properties.c | 89 ++++++++++++++++++++++++++++++++++++ 4 files changed, 99 insertions(+) -- 2.20.1 diff --git a/include/exec/memory.h b/include/exec/memory.h index 7207025bd49..84ee5b7a01f 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -51,6 +51,12 @@ extern bool global_dirty_log; typedef struct MemoryRegionOps MemoryRegionOps; +struct ReservedRegion { + hwaddr low; + hwaddr high; + unsigned type; +}; + typedef struct IOMMUTLBEntry IOMMUTLBEntry; /* See address_space_translate: bit 0 is read, bit 1 is write. */ diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 49c6cd24607..944e3f2e0cd 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -19,6 +19,7 @@ extern const PropertyInfo qdev_prop_string; extern const PropertyInfo qdev_prop_chr; extern const PropertyInfo qdev_prop_tpm; extern const PropertyInfo qdev_prop_macaddr; +extern const PropertyInfo qdev_prop_reserved_region; extern const PropertyInfo qdev_prop_on_off_auto; extern const PropertyInfo qdev_prop_multifd_compression; extern const PropertyInfo qdev_prop_losttickpolicy; @@ -184,6 +185,8 @@ extern const PropertyInfo qdev_prop_pcie_link_width; DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *) #define DEFINE_PROP_MACADDR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr) +#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f) \ + DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion) #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto) #define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index ce4a78b687a..15f5047bf1d 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -58,6 +58,7 @@ typedef struct ISABus ISABus; typedef struct ISADevice ISADevice; typedef struct IsaDma IsaDma; typedef struct MACAddr MACAddr; +typedef struct ReservedRegion ReservedRegion; typedef struct MachineClass MachineClass; typedef struct MachineState MachineState; typedef struct MemoryListener MemoryListener; diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 71f8aca7c60..ca7771f3072 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -15,6 +15,7 @@ #include "chardev/char.h" #include "qemu/uuid.h" #include "qemu/units.h" +#include "qemu/cutils.h" void qdev_prop_set_after_realize(DeviceState *dev, const char *name, Error **errp) @@ -578,6 +579,94 @@ const PropertyInfo qdev_prop_macaddr = { .set = set_mac, }; +/* --- Reserved Region --- */ + +/* + * Accepted syntax: + * :: + * where low/high addresses are uint64_t in hexadecimal + * and type is a non-negative decimal integer + */ +static void get_reserved_region(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + ReservedRegion *rr = qdev_get_prop_ptr(dev, prop); + char buffer[64]; + char *p = buffer; + int rc; + + rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u", + rr->low, rr->high, rr->type); + assert(rc < sizeof(buffer)); + + visit_type_str(v, name, &p, errp); +} + +static void set_reserved_region(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + ReservedRegion *rr = qdev_get_prop_ptr(dev, prop); + Error *local_err = NULL; + const char *endptr; + char *str; + int ret; + + if (dev->realized) { + qdev_prop_set_after_realize(dev, name, errp); + return; + } + + visit_type_str(v, name, &str, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + ret = qemu_strtou64(str, &endptr, 16, &rr->low); + if (ret) { + error_setg(errp, "start address of '%s'" + " must be a hexadecimal integer", name); + goto out; + } + if (*endptr != ':') { + goto separator_error; + } + + ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high); + if (ret) { + error_setg(errp, "end address of '%s'" + " must be a hexadecimal integer", name); + goto out; + } + if (*endptr != ':') { + goto separator_error; + } + + ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type); + if (ret) { + error_setg(errp, "type of '%s'" + " must be a non-negative decimal integer", name); + } + goto out; + +separator_error: + error_setg(errp, "reserved region fields must be separated with ':'"); +out: + g_free(str); + return; +} + +const PropertyInfo qdev_prop_reserved_region = { + .name = "reserved_region", + .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0", + .get = get_reserved_region, + .set = set_reserved_region, +}; + /* --- on/off/auto --- */ const PropertyInfo qdev_prop_on_off_auto = { From patchwork Fri Jul 3 16:53:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231230 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2560967ilg; Fri, 3 Jul 2020 09:57:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAYJCawKGjboMXd52OAeZEdpPkV/3wEwd0ZhKZLoRn6VvrF3lgdnaFYjpYdAiDRl5o+iZe X-Received: by 2002:a25:388d:: with SMTP id f135mr57932911yba.201.1593795447629; Fri, 03 Jul 2020 09:57:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795447; cv=none; d=google.com; s=arc-20160816; b=SYDz0bB2Fifft31qGbN89+jJYtVTWhOAN+N/Kq0D1s/GyVFco9S7gnut+GACcZwcvD L/e2zVp5SVamLnsitkBt98KUvKos/12kXiCan6UWblo8CZXiTgVrKFY7QEzpxcqXWn5t eCCahxHIQq1XW/LRh2TJ3VWruNBcoiE/HoeNJDxNQ5Ck/XHCRGRFyzTS33VW6CDXmJii zR/YEtQI99+XEs2aFUP7XvFj7OJDSJX3z5W287jKo/x84WTc5pBHe3YEmEGxaoLjrGEq eJFbwmg37eRSB/VobfsexxJj9SHvsMIvr6cDVOofgp2X8ZuUWn8RWtfKgNf4WBN36Nzr zCzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LYLM5KGT9ESWwhVMJu2xp0OBpJry26+3A943JgtnOhc=; b=hJIgqKrFGIayt2XW0191fk3AFiKnFCrEieXr7sgtZ5/9WHYhO0MaMt+c7e9VI9XGiJ l0fteod98HiMLx/4+nkA05b5blKmUte6ajnsYPwM3TXWiQS1XXoLjVpLCAGM4X4n/Zcx vCzFFjxihz2t/6iAptwmc5g5ij1lL/LOxk6p3KvbsiAH7b3EIdIjD8GJiOAKRWrlRktY BCHdMuGXsHqspaveL7D0T7F1AUkn45SUbSnatYBXuHXCehrD0Is6DaVXdmUQEGF+QLHN jrd98juL7X3FAPQzLbvHFqxC+wV63y/7gcVyhaVQ28YzQFRrlBusPRYYmi/b8wuzStop 2k5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x1RYuHWP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i192si11414981yba.341.2020.07.03.09.57.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:57:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x1RYuHWP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP0B-0008KK-2m for patch@linaro.org; Fri, 03 Jul 2020 12:57:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx6-0004YW-Ql for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:16 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:36648) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx4-0005ec-Hp for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:16 -0400 Received: by mail-wr1-x42f.google.com with SMTP id k6so33436727wrn.3 for ; Fri, 03 Jul 2020 09:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LYLM5KGT9ESWwhVMJu2xp0OBpJry26+3A943JgtnOhc=; b=x1RYuHWPOfwN4mQFQfRipxF3gev/0yf3915T6bUuoarDBrPK3ULey33iLpOXdmPuD6 QWHJTyXD7kE26pChuAXjzOz5IrSnTD1hcndrK3gNBn2UsU84o1v9p7g+Qb5S7BiFyNvK VkE+6C+0iqks0V8hVvnasaZEx75vC7UPTKHR+D8ugfdu64FvHlZ2uXXiZ7eQAg5n62Uf 83S86gnFcyhiFJErYZtRrGRbcsnYeXGXWcm3o6wZrDujLnisdvJsGVvlvKLm0cxv17Ov C/1r+ETbgoMy200fozLGrA0IVasTz7W4ge53Fi/kqwSEWHzlArn/rZBQPTtGMq35vvk1 RmhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LYLM5KGT9ESWwhVMJu2xp0OBpJry26+3A943JgtnOhc=; b=CA4H4DTKZvrRDRvurVK0i4kVDYYdi/9I2DSDy780898JceH4JyMwpgorpo6Dq1fibx 2P3HhgIYh7Y2cmo14JJ+c1waAM6Z0bgB2oR0HQDa3WUtBQz6ZCZO/RBERtTywhhDw8+f A04VjKnlx99KYf4DQCC0jow6jYEQvE3S/+6Flj8gv4TdcAVei1KnMygAM1VaN/xmnJZs QWELr0D2gXk5JZaKiCF7HNq8GnVwnZicpZQwPz5F9nUkToH1cXHRgYgn8+anpFW8a3CA 0Cp5GYAexfvb1N3O7diWf8HkKZm4RdLuVmCg/C7DqVHymm1TZbkxpXsBrA+rVtDaypVI 8qlw== X-Gm-Message-State: AOAM531Vw9VwZQbUXReJDEBmBMesPtBfikltOdZV3u/iv6IP9wLdEQvp ZiZvd62ho9hIFENmwApey7oTWG+8iIFL4w== X-Received: by 2002:a05:6000:128e:: with SMTP id f14mr41045305wrx.276.1593795252965; Fri, 03 Jul 2020 09:54:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/34] virtio-iommu: Implement RESV_MEM probe request Date: Fri, 3 Jul 2020 17:53:36 +0100 Message-Id: <20200703165405.17672-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger This patch implements the PROBE request. At the moment, only THE RESV_MEM property is handled. The first goal is to report iommu wide reserved regions such as the MSI regions set by the machine code. On x86 this will be the IOAPIC MSI region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS doorbell. In the future we may introduce per device reserved regions. This will be useful when protecting host assigned devices which may expose their own reserved regions Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker Reviewed-by: Michael S. Tsirkin Message-id: 20200629070404.10969-3-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/virtio/virtio-iommu.h | 2 + hw/virtio/virtio-iommu.c | 94 ++++++++++++++++++++++++++++++-- hw/virtio/trace-events | 1 + 3 files changed, 93 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h index e653004d7ca..49eb105cd84 100644 --- a/include/hw/virtio/virtio-iommu.h +++ b/include/hw/virtio/virtio-iommu.h @@ -53,6 +53,8 @@ typedef struct VirtIOIOMMU { GHashTable *as_by_busptr; IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX]; PCIBus *primary_bus; + ReservedRegion *reserved_regions; + uint32_t nb_reserved_regions; GTree *domains; QemuMutex mutex; GTree *endpoints; diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 483883ec1d9..2cdaa1969bb 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -38,6 +38,7 @@ /* Max size */ #define VIOMMU_DEFAULT_QUEUE_SIZE 256 +#define VIOMMU_PROBE_SIZE 512 typedef struct VirtIOIOMMUDomain { uint32_t id; @@ -378,6 +379,65 @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, return ret; } +static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep, + uint8_t *buf, size_t free) +{ + struct virtio_iommu_probe_resv_mem prop = {}; + size_t size = sizeof(prop), length = size - sizeof(prop.head), total; + int i; + + total = size * s->nb_reserved_regions; + + if (total > free) { + return -ENOSPC; + } + + for (i = 0; i < s->nb_reserved_regions; i++) { + unsigned subtype = s->reserved_regions[i].type; + + assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED || + subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI); + prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM); + prop.head.length = cpu_to_le16(length); + prop.subtype = subtype; + prop.start = cpu_to_le64(s->reserved_regions[i].low); + prop.end = cpu_to_le64(s->reserved_regions[i].high); + + memcpy(buf, &prop, size); + + trace_virtio_iommu_fill_resv_property(ep, prop.subtype, + prop.start, prop.end); + buf += size; + } + return total; +} + +/** + * virtio_iommu_probe - Fill the probe request buffer with + * the properties the device is able to return + */ +static int virtio_iommu_probe(VirtIOIOMMU *s, + struct virtio_iommu_req_probe *req, + uint8_t *buf) +{ + uint32_t ep_id = le32_to_cpu(req->endpoint); + size_t free = VIOMMU_PROBE_SIZE; + ssize_t count; + + if (!virtio_iommu_mr(s, ep_id)) { + return VIRTIO_IOMMU_S_NOENT; + } + + count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free); + if (count < 0) { + return VIRTIO_IOMMU_S_INVAL; + } + buf += count; + free -= count; + + return VIRTIO_IOMMU_S_OK; +} + static int virtio_iommu_iov_to_req(struct iovec *iov, unsigned int iov_cnt, void *req, size_t req_sz) @@ -407,15 +467,27 @@ virtio_iommu_handle_req(detach) virtio_iommu_handle_req(map) virtio_iommu_handle_req(unmap) +static int virtio_iommu_handle_probe(VirtIOIOMMU *s, + struct iovec *iov, + unsigned int iov_cnt, + uint8_t *buf) +{ + struct virtio_iommu_req_probe req; + int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req)); + + return ret ? ret : virtio_iommu_probe(s, &req, buf); +} + static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) { VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); struct virtio_iommu_req_head head; struct virtio_iommu_req_tail tail = {}; + size_t output_size = sizeof(tail), sz; VirtQueueElement *elem; unsigned int iov_cnt; struct iovec *iov; - size_t sz; + void *buf = NULL; for (;;) { elem = virtqueue_pop(vq, sizeof(VirtQueueElement)); @@ -452,6 +524,17 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) case VIRTIO_IOMMU_T_UNMAP: tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt); break; + case VIRTIO_IOMMU_T_PROBE: + { + struct virtio_iommu_req_tail *ptail; + + output_size = s->config.probe_size + sizeof(tail); + buf = g_malloc0(output_size); + + ptail = (struct virtio_iommu_req_tail *) + (buf + s->config.probe_size); + ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf); + } default: tail.status = VIRTIO_IOMMU_S_UNSUPP; } @@ -459,12 +542,13 @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) out: sz = iov_from_buf(elem->in_sg, elem->in_num, 0, - &tail, sizeof(tail)); - assert(sz == sizeof(tail)); + buf ? buf : &tail, output_size); + assert(sz == output_size); - virtqueue_push(vq, elem, sizeof(tail)); + virtqueue_push(vq, elem, sz); virtio_notify(vdev, vq); g_free(elem); + g_free(buf); } } @@ -667,6 +751,7 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) s->config.page_size_mask = TARGET_PAGE_MASK; s->config.input_range.end = -1UL; s->config.domain_range.end = 32; + s->config.probe_size = VIOMMU_PROBE_SIZE; virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX); virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC); @@ -676,6 +761,7 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP); virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS); virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO); + virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE); qemu_mutex_init(&s->mutex); diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 6427a0047df..23109f69bbf 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -74,3 +74,4 @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d" virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d" virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64 +virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64 From patchwork Fri Jul 3 16:53:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231228 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2560347ilg; Fri, 3 Jul 2020 09:56:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymk/ooLcrUjFWqPDUtSQnobeJ3I5NarczUkb5MgxP85zPp2JpSXUHdGi1UIWeEtnCYYqer X-Received: by 2002:a25:bf8c:: with SMTP id l12mr64452438ybk.447.1593795383456; Fri, 03 Jul 2020 09:56:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795383; cv=none; d=google.com; s=arc-20160816; b=jNAu0Rcm+hIA8U8Lqeo4sH8JvhAkAqMlJdjKzp2cwO+PfzL5y3eycZs2dGITtgmeUH UNyH6ycQmElTgqOIv71Oe1gBi4UzBHzgeMX1OidNqrWlc7kh6HbID3RokH0/avIzNzDA pNpJdedswH8Hn2ImW79Tb2+Tqnxe1lfdETBellnYE3r5Nle5rmZ9wpSqeCd/N0/IDbHY AZ7KjK6g/jbt933WhNqSVce91ryeViXIcgGygNWUh1W+I7gCPEJJZSpevzOvAEkXhhqH sQJAGoCxTkUEMtiSQfLreoa2uCqdmnQ1HxPUxiYMQGgP7UbFAmNoUYc43TFucG+eeEbz V3aQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=295eK5ijKQ0QsX4O3HxBkZyowFWTTmfTtCLGUV8KWHM=; b=C94VKyLg/akKYUHnHF3A7DEH5AJhl5KAQILuQQkk+Q2KjMpxbycF71bn6L2E7DsmE0 dzPF3l1wJSAzfKIaRyv2MU0w6yuM9TTOVlYMufIKT9wGOdN0jh5MUyEjvVq0VOE08SsP lRbLNbsPcdUS/VhMiWVM/HRmtBHgiqI71Kr/vrht5GFtSTB2pgJhdJt+m6Bh05I6pqQH YqRjgAZ+TvfdsS7jw5iFVPVJRvQvdAwoixYWx6hQsbOOPL4ngAghooB2jeCXFjA0LorG mOZujDYatjyA67gfjhske/rkYSPieiWCvkepQ1OW+rkssdZ6ngsYl/xa9ABlLJMUZJr/ i5Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qybWWgB8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 124si1948040ybb.302.2020.07.03.09.56.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:56:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qybWWgB8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrOz8-0008QS-Sp for patch@linaro.org; Fri, 03 Jul 2020 12:56:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx7-0004aM-Nm for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:17 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:41079) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx5-0005en-QS for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:17 -0400 Received: by mail-wr1-x42e.google.com with SMTP id z15so22143991wrl.8 for ; Fri, 03 Jul 2020 09:54:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=295eK5ijKQ0QsX4O3HxBkZyowFWTTmfTtCLGUV8KWHM=; b=qybWWgB86TqW4QOm8y+5eXTZA46C91bZTu64AVBPwyZIN/m7O1vqmvpJ3baou6DAGp jteupGK1EpJeAbpYE8cWX3qSajs7nafmeZj37jFpTf9IzIGMRVnuGqdHM8i1dgwegiPk 0bnbeqg2lFtr8Yc6ObgJlmZ7Z5TRmx0MEkXNxiDhxl4Fk+X9KQMF+CATlMaQhtzAaoBg t3XI/nRv4dKwOOTbvDxGo27UosGWNf5AaFX4JSRNERIiH1uKI4F9axKC+z2uh6wfJAhm ZjZUWGYTfnxeuEcHt64wrUsbIIlHGD2U7FL/DgLj6enirg+9+MKgQTYWhybSWkaBDWD1 LgZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=295eK5ijKQ0QsX4O3HxBkZyowFWTTmfTtCLGUV8KWHM=; b=VUyojpHAqYfW0cuJ7dA4IncsSvQZnkwrOqyDBxeBl5PBNNtViywSoP16oPJVDBmcft 4YEjNcPgUjEKDGv2+NM/lrGvhUTborj0exF79i7b/atxZRjNAK+5ENrLke1ITVVUnWW5 9e0k2h3Cy3OXBR7U+UhzysEKiEHH+tXPn9aUjNfjzmiA00MRC/n9PUq8Vupz9isAo/dt +6KYXwU1N8pffLoP1G6loe9jhHLaHw30nMcyXVK5vCHGnXcqMcDDkmnRsYfXW9Nh+VHF 3k24DH1Q02EUduvwJK0KRqSoX+YRv9wGTv5eDMKsavQN8ZQVZiqqPcpc77L/UnrPMk9L +1JQ== X-Gm-Message-State: AOAM531b/2dvxaJxUwjynMaZB8/J69rISXt0yoPw43fWku2uMjeCVwTi VDD2hd6NiJsErBn+Q8PF2u6Jso9E2dRwig== X-Received: by 2002:adf:8444:: with SMTP id 62mr35980364wrf.278.1593795254148; Fri, 03 Jul 2020 09:54:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/34] virtio-iommu: Handle reserved regions in the translation process Date: Fri, 3 Jul 2020 17:53:37 +0100 Message-Id: <20200703165405.17672-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger When translating an address we need to check if it belongs to a reserved virtual address range. If it does, there are 2 cases: - it belongs to a RESERVED region: the guest should neither use this address in a MAP not instruct the end-point to DMA on them. We report an error - It belongs to an MSI region: we bypass the translation. Signed-off-by: Eric Auger Reviewed-by: Peter Xu Reviewed-by: Jean-Philippe Brucker Reviewed-by: Michael S. Tsirkin Message-id: 20200629070404.10969-4-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.20.1 diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 2cdaa1969bb..b39e836181e 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -607,6 +607,7 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, uint32_t sid, flags; bool bypass_allowed; bool found; + int i; interval.low = addr; interval.high = addr + 1; @@ -640,6 +641,25 @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, goto unlock; } + for (i = 0; i < s->nb_reserved_regions; i++) { + ReservedRegion *reg = &s->reserved_regions[i]; + + if (addr >= reg->low && addr <= reg->high) { + switch (reg->type) { + case VIRTIO_IOMMU_RESV_MEM_T_MSI: + entry.perm = flag; + break; + case VIRTIO_IOMMU_RESV_MEM_T_RESERVED: + default: + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING, + VIRTIO_IOMMU_FAULT_F_ADDRESS, + sid, addr); + break; + } + goto unlock; + } + } + if (!ep->domain) { if (!bypass_allowed) { error_report_once("%s %02x:%02x.%01x not attached to any domain", From patchwork Fri Jul 3 16:53:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231232 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2561778ilg; Fri, 3 Jul 2020 09:58:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwd926hkfBjJYws6XbuLrEgyvFBTs4ljZocJkMI4VTkUQFggU/94MFb3B9uGOQ3N7N31MHW X-Received: by 2002:a25:cd83:: with SMTP id d125mr56765401ybf.38.1593795515949; Fri, 03 Jul 2020 09:58:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795515; cv=none; d=google.com; s=arc-20160816; b=YvHo7F9uN5qw1U1LDFrQCU4+Z5y5k6Wfifuck1CNm4oo+dMOraIwZqMEtuOIiwErHv ivQ6fF7iEc/heUaZa7KK/k8/4RKqqTLdTS2Xx9+C020sLWJ1MnJFCpEMZV2/ym7HgJaN tDi3jGz4DuFeOILMOR4qw3YdTOTh0cUPRzWiA9djQLb0XHKJS+BHK57YmCI8/m/GXNex TjFvepsi65T5mj1Lgrt9Px+4H2oAjdPE37NV8b1DU5Mf+raghOP19gQ3dMDSPD5qH4LP OY8NEFiIjAMZPGRTE08dmzHAd18Hw3NAR8LGKvU6YmyWeBliVZ2MU8FJI/sicFZMm1a+ lhGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T17rWK5CCU0ZUANk3vqpHki4UbNYDej3t8lSuYskTdY=; b=WGNJQ7RIFomXQFCoxEZUZx//41wrWrAi08/BxvKKLgp6TBKelMK4Kdpezc9510RFAh 022yL+ONoho3qgZdAwocclg0BYoBgpXAtgf9/Suw2TWeszfK9JiCSzYEp/YkGPSTKAIc MmATKzmQmOQCBobVGVZjPF9qvVHqlEAIwWK6OpO28RyyWGQ/id3AnJ5heCRGjYByHSe1 UyyxjAcYR7M1l6JdpZM8RmoSitPETYBleurRKxEBwYwivTiPVFlRZo+u6q+FoYjn+UpN 3VQ3jeUajm2kjXvR+Ee2MuvqQN2gaOoMUMH1QMd5YnAtOwwpjPg+pdxrW8D5/uzr1xBm I33g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LDpLqQQg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v9si10666665ybk.256.2020.07.03.09.58.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:58:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LDpLqQQg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP1H-000407-A8 for patch@linaro.org; Fri, 03 Jul 2020 12:58:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49992) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx8-0004cO-MM for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:18 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:50681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx6-0005f3-Ri for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:18 -0400 Received: by mail-wm1-x32d.google.com with SMTP id l17so32636679wmj.0 for ; Fri, 03 Jul 2020 09:54:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=T17rWK5CCU0ZUANk3vqpHki4UbNYDej3t8lSuYskTdY=; b=LDpLqQQgCjEL9GPjFpb8U/YkdUKmHKibZZMPFcHOPyj0Qvn0oo9RuVsu9gIIE3XnPw /clCffpqEkE1G/XhHNJ9QWxXK/UzzayxrcYnrYtu9OnTmHqp2uUV9ovWmibpNWfZhae1 +6wUej3mSCKeparKNsqZLOuhwqZKHd0C8Bu7FKF7PPYKwCO016qhezBrfHDgHFqshhT7 qn5V6lxKhHGEv4O+35+y9xc3TWhZ1bXa18Fo7iUIGolZzbEsJcMcZKDpE+sBzlZrgX12 53rb7oDX6vH/fBsRkGt2V4pxMwzvWlEOX9XKZJEsOl6x63QY7MSSJ4/zY21xzzxb7GVT rcug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T17rWK5CCU0ZUANk3vqpHki4UbNYDej3t8lSuYskTdY=; b=iLz5FslZmzgk4//zCMQ6YcYBhbaL9cDt6mi/cAjil/T8ufNI/7OnEW/dx+nmv2LG94 ZOGywFdFcBtfS6ofKFVQ72zVpDMTFRJBziU+/GQvUZ7Z++Fgg3K6dMs+NylwmU4D93lt Vydl3UL0Ksf7wi0/jBJCt1QezKmiHq7dYYOBqPoi8M6OCN8ojuDzBRSGHlFPLxioxz3g eHPfBzLmldxR1qK3ZFQrcghcmcjyRuJsBn1BU5uFSHq419PR0VPD2IIfcFAn1eSk54Hc T0dMWomfUnqQHN/nHIyYiFwPuTo9Om/klrZ8q6PxEv9vhpIdeDsMSoQP+PcMuKtTgot/ 7P7g== X-Gm-Message-State: AOAM531eJ3uUoe8rvKyHuyyBFkafi06mVnTo92djW72wJH7bmkB1fzYJ /trXSwBwSpS9KPFAaKrinrZlaRYhm+jKbA== X-Received: by 2002:a7b:c5c4:: with SMTP id n4mr36674691wmk.67.1593795255133; Fri, 03 Jul 2020 09:54:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/34] virtio-iommu-pci: Add array of Interval properties Date: Fri, 3 Jul 2020 17:53:38 +0100 Message-Id: <20200703165405.17672-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger The machine may need to pass reserved regions to the virtio-iommu-pci device (such as the MSI window on x86 or the MSI doorbells on ARM). So let's add an array of Interval properties. Note: if some reserved regions are already set by the machine code - which should be the case in general -, the length of the property array is already set and prevents the end-user from modifying them. For example, attempting to use: -device virtio-iommu-pci,\ len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1 would result in the following error message: qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa, len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1: array size property len-reserved-regions may not be set more than once Otherwise, for example, adding two reserved regions is achieved using the following options: -device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\ reserved-regions[0]=0xfee00000:0xfeefffff:1,\ reserved-regions[1]=0x1000000:100ffff:1 Signed-off-by: Eric Auger Reviewed-by: Michael S. Tsirkin Reviewed-by: Jean-Philippe Brucker Reviewed-by: Peter Xu Message-id: 20200629070404.10969-5-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/virtio/virtio-iommu-pci.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.20.1 diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index 4588361d6b3..592abc9279c 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -33,6 +33,9 @@ struct VirtIOIOMMUPCI { static Property virtio_iommu_pci_properties[] = { DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0), + DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI, + vdev.nb_reserved_regions, vdev.reserved_regions, + qdev_prop_reserved_region, ReservedRegion), DEFINE_PROP_END_OF_LIST(), }; @@ -40,6 +43,7 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); + VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); @@ -54,6 +58,13 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) "-no-acpi\n"); return; } + for (int i = 0; i < s->nb_reserved_regions; i++) { + if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED && + s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) { + error_setg(errp, "reserved region %d has an invalid type", i); + error_append_hint(errp, "Valid values are 0 and 1\n"); + } + } object_property_set_link(OBJECT(dev), OBJECT(pci_get_bus(&vpci_dev->pci_dev)), "primary-bus", &error_abort); From patchwork Fri Jul 3 16:53:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231231 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2561403ilg; Fri, 3 Jul 2020 09:58:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvqQnjfUVCMzsQG66laqLVI5AuXYy5+ow9ybjBDk9Ib/QIl7qtOo01sCK850BbXJe8WdbI X-Received: by 2002:a25:2e43:: with SMTP id b3mr60102149ybn.190.1593795483584; Fri, 03 Jul 2020 09:58:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795483; cv=none; d=google.com; s=arc-20160816; b=vJqMK/2aAaGhrV2uDPTFX88EDuai6BtO/uQiY1/KfoE0brvl0w7rjpd3zfUX6Vmn7l NOeeovHSF91u/yOFxVy8yFo/wq5QYAqsrn0PbaT2hUnRAT2KaFc0jzcvtU2xSI2TbzZq 0Ka2McIy8mitfVTKtzR0XmWZY6N2cBvEYsIK/ToxeYEbSwwfq619yjcS9E4PTmizPyZB H2b+a2Eo4czhGB5Me4pVcncAjc8bHbax9FVY91Xy8K7WnM4lUJJFFSV+z/1LGb1XFd87 UcsNKUlgmH/+GwBS1cOFWyBZXwWnfTuW0N2BVWS99I2N1DnWKDQSfDh9Ez4GU10ZRvln gTkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EbbmXTpDnijCYEth67+ubP+o2i89Y7K6M4yUuCHERro=; b=jwP51+tEnTjtHVj0n8gAljiV6a5zVogzsUXYb+FL6kVPSD6ZgFWU9GrVhIbdXpT5Yy mFcLrm3jNLmwbWlkNiOBDpTuI6WTYkUU/DQ8SlY5P6ysCpWGkarGaAdLmUMr8Pfqorw9 ikKX02xjqQy+7P7liB+01r3FGhfTCXHyMfb2ENbFQs2tjTGWuk03oLmQTtigW9FUCFQ8 hW/dn6YDs7fc55wDXKwQdzzU5OR+R/DJ8Bg4d08mfTlRYPWBY6d03saRjXGwmpmuw4DB oB96sbj528K8162z6ZSxV+Gc7x/6bjeAxrJilkaAf/STYVzBTSfqVwKzNY8d4i3bpCYA Xw7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gaoqUowT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h185si11737748ybg.448.2020.07.03.09.58.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:58:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gaoqUowT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP0l-0001Gn-07 for patch@linaro.org; Fri, 03 Jul 2020 12:58:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOx9-0004ei-Is for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:19 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:55512) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx7-0005fF-Mm for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:19 -0400 Received: by mail-wm1-x32b.google.com with SMTP id g75so32622636wme.5 for ; Fri, 03 Jul 2020 09:54:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EbbmXTpDnijCYEth67+ubP+o2i89Y7K6M4yUuCHERro=; b=gaoqUowTdPGRycBYt8EcKJzHkULzCCCQxEgsTXjhwYXS+0I7wWe4xqYnl2GAQt/1Be XFNed+B61WRxpPbIZh5OY/iHQshtUaFa76sxecG6DqmMRDoKBponEJaz4WW5BTRGY39G MB6EeCDN0TI6fKaLHfBnvH/qKMqX7CS1BTnBrUqQi4NXHZSlUMYsMAxUUox8UOypMy6k EjxDYDLPnu3lApm6hZv89yuLc93fKCj95y+QYLXx8UVjTBnphVjUkKssoyUIrc1Ax8ev xkDmII+HSm/sQiV+C7HQcB1YqSTcvooiRFP/+dre6vANTcbB729E1lSvl/Tdc11/VVQE PqUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EbbmXTpDnijCYEth67+ubP+o2i89Y7K6M4yUuCHERro=; b=cheN3MOijJtBmkNpZqfbLbQknk+PzJebgTJWZXFa5zP/5+D9vw7V44BDj/lyc3Ktyn xGxaxza1bat/7O4KT1tQt//GUK5ngQWED7yIAOCIiQdnehDvU7iViK0T7TcUWIiKFtT0 c4a1abeYmirhEj6HswpLAmAnIT0Di2mrKZdKyC5c2B+ZDwkE/wH74SHmV6fftm/AQq3G LvR3L3bcphOzbpyLmhLmBI3to2vGZSDLjzvyZV65YlXQ4p1+VAV15TlN0oVWojoIeLrq DImm9Gzi2KkuvPTJo5rC69+2QgiBXQWykR2NJvKc4QHb3txwMOlW4ojcx5cegHsYV1ch x0dA== X-Gm-Message-State: AOAM531dN72Z0pm1cS2Bs3iasL1I6kQL7iUFx73uW/QDqiEt1LqOZ34+ kYebU9UZHv3qTMd4vRrWbpHeY2IfMl1emQ== X-Received: by 2002:a05:600c:2253:: with SMTP id a19mr35808184wmm.136.1593795256067; Fri, 03 Jul 2020 09:54:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs Date: Fri, 3 Jul 2020 17:53:39 +0100 Message-Id: <20200703165405.17672-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger At the moment the virtio-iommu translates MSI transactions. This behavior is inherited from ARM SMMU. The virt machine code knows where the guest MSI doorbells are so we can easily declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that setting the guest will not map MSIs through the IOMMU and those transactions will be simply bypassed. Depending on which MSI controller is in use (ITS or GICV2M), we declare either: - the ITS interrupt translation space (ITS_base + 0x10000), containing the GITS_TRANSLATOR or - The GICV2M single frame, containing the MSI_SETSP_NS register. Signed-off-by: Eric Auger Message-id: 20200629070404.10969-6-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 7 +++++++ hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 31878ddc722..a18b6b397b6 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -96,6 +96,12 @@ typedef enum VirtIOMMUType { VIRT_IOMMU_VIRTIO, } VirtIOMMUType; +typedef enum VirtMSIControllerType { + VIRT_MSI_CTRL_NONE, + VIRT_MSI_CTRL_GICV2M, + VIRT_MSI_CTRL_ITS, +} VirtMSIControllerType; + typedef enum VirtGICType { VIRT_GIC_VERSION_MAX, VIRT_GIC_VERSION_HOST, @@ -136,6 +142,7 @@ typedef struct { OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; + VirtMSIControllerType msi_controller; uint16_t virtio_iommu_bdf; struct arm_boot_info bootinfo; MemMapEntry *memmap; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index af3050bc4bd..7922f3c23a5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -600,6 +600,7 @@ static void create_its(VirtMachineState *vms) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); fdt_add_its_gic_node(vms); + vms->msi_controller = VIRT_MSI_CTRL_ITS; } static void create_v2m(VirtMachineState *vms) @@ -620,6 +621,7 @@ static void create_v2m(VirtMachineState *vms) } fdt_add_v2m_gic_node(vms); + vms->msi_controller = VIRT_MSI_CTRL_GICV2M; } static void create_gic(VirtMachineState *vms) @@ -2198,8 +2200,36 @@ out: static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { + VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { virt_memory_pre_plug(hotplug_dev, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { + hwaddr db_start = 0, db_end = 0; + char *resv_prop_str; + + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: + return; + case VIRT_MSI_CTRL_ITS: + /* GITS_TRANSLATER page */ + db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; + db_end = base_memmap[VIRT_GIC_ITS].base + + base_memmap[VIRT_GIC_ITS].size - 1; + break; + case VIRT_MSI_CTRL_GICV2M: + /* MSI_SETSPI_NS page */ + db_start = base_memmap[VIRT_GIC_V2M].base; + db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; + break; + } + resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", + db_start, db_end, + VIRTIO_IOMMU_RESV_MEM_T_MSI); + + qdev_prop_set_uint32(dev, "len-reserved-regions", 1); + qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); + g_free(resv_prop_str); } } From patchwork Fri Jul 3 16:53:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231235 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2562371ilg; Fri, 3 Jul 2020 09:59:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKIaVmqSCHX1OtYu47Pj7bhHUJf0JSZyHAvpbL7XHymTQWV/Pu+7Ex0vFkpb9zXiJcwcBT X-Received: by 2002:a25:684a:: with SMTP id d71mr1528552ybc.68.1593795572705; Fri, 03 Jul 2020 09:59:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795572; cv=none; d=google.com; s=arc-20160816; b=tlP0JAIQy1rIPNg0/AZoV3h4KHYD8z8u2wIt1gv7+eymZxSzODolNrXlDIu4fgCAP1 TAk7RWkP0d38AyT6Os2b2G9e9tbia3H4gMEyurhy7a61qANmBeYwLLDRWrNNvgTsryls 758JBqhe1a8rCJTvmpqJERAlQAG5h+l8yQq5gOD0ioRpFx+e7MO2Hhyq57G5W/f1yqMN fk/04f8K1Ab003JAre0yCxuda1xNFjjYGfIxzs4tIPZy2tlQ63a6oGxt5rjXPzY0uecH i6cbzcX1m5zyHnyoT16lYMPdYCUihPkAB/JPj69pbKPyaZH34S9VvnsggLkA9Zl6rljk ZKtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BP6j/3HoxCBLJuDgMNnWxb3Xu4bxKE76bxnjKGSc4hg=; b=g8A6GY78rfANPm/JWMiXE9NoyDpo4PGSoNRc43GcYkX9u+cIUiTUXVyYKcc8Ve3nAe MTCOoZaEiX7mYv6jjI3N8SBbPsD5z8rJ5/07NPRN0IH1ditRgRhWMwiw0zSvozZKXKOG T0Uezh6iEcA9C1EAzfBoIfJrBnPrGiRERbvnF3moJiuleoRbHq799EBbH7YauNHHIiMw 6pOMtw0ztB0uNhIfSjoiuaZ8JQxG/+uQJfvLj1xh4wg26v0TOoqqbc2uKVLGRtXgDm5Z p9FrYkNZFH3oSLTAIDP2H2zbucVK3UFrxsJfw9pmKB3BJsPsjZBRicSXhzu1CjE4ataT ArvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kJut4Eo5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e1si12964933ybp.19.2020.07.03.09.59.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:59:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kJut4Eo5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP2C-0005GB-4Z for patch@linaro.org; Fri, 03 Jul 2020 12:59:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxA-0004hH-OB for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:20 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37257) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx8-0005fP-SN for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:20 -0400 Received: by mail-wr1-x444.google.com with SMTP id a6so33423178wrm.4 for ; Fri, 03 Jul 2020 09:54:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BP6j/3HoxCBLJuDgMNnWxb3Xu4bxKE76bxnjKGSc4hg=; b=kJut4Eo5SHspIxgjriUq994rVvP3dM7w9x9sDGSehnrSs6GJ57odYtCKBIjLcMntCR SoDGx66UGDCT3K0E6G6uNfep+t+d/osNBDg6JQv6DLYWKEdjawR1ralR4y2BT4d7hNfV aj+NATFOG6knQExuN/V2AL41cwJ0Wy4wHceqecdjvTiH+b9X7v8VpdkVjkeYqg7eaUza Vg2WEv6Y0oRlKnHNR8bVx4bDCzm9vM7Ifl+kMgWXZ+26WsAcHFdsVQ00OAaIpo1Bsimf PNwV6o+nTNg28PL8APVZky4n3UevdMDc6/nQRReuwvT6wH3pj9FCImzb6VuoXO2z6v7B N2hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BP6j/3HoxCBLJuDgMNnWxb3Xu4bxKE76bxnjKGSc4hg=; b=QXESOhWpnbGKkgbu0kk3SHyQjOzsTi6uCLU2N/UjeU3eQvsfpndc0s+/LXIQiffP+5 uDRx03LvpBAqoWPwKH+/uQzsj0lAUGIbosfyqgfdRlTez/Btg+i8Dzb82TF40jwhA+hc f8fzQxOFQBGyahESieeccikc8qqTWQGzOuq6UvnUAAVtMmCGWbspXPJ5YQSpZOnX6tNp yVrZDdECdz+VL8pm/Y/pIIuW1eBJ7BEhvBE8z5rwovZg2+ZKFfkyM+FjX9gca/qkX5BH gdTtaUmyRoKhNSqm9FwnBYYyIGy6soJmYec7dFXSeBg9PojhW4iXkREXWNXwMUtwmDmX c0BQ== X-Gm-Message-State: AOAM530QmuTd7Bt8Fc1e/A9T4hpdw5+jEcQxUjqIpb8G0ezAVAynpFii Z/2zt1zlJKXp2zv2yJZs8a1dQoAUyN4HxQ== X-Received: by 2002:a5d:4b0f:: with SMTP id v15mr2685265wrq.216.1593795257154; Fri, 03 Jul 2020 09:54:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS Date: Fri, 3 Jul 2020 17:53:40 +0100 Message-Id: <20200703165405.17672-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Beata Michalska On ARMv7 & ARMv8 some load/store instructions might trigger a data abort exception with no valid ISS info to be decoded. The lack of decode info makes it at least tricky to emulate those instruction which is one of the (many) reasons why KVM will not even try to do so. Add support for handling those by requesting KVM to inject external dabt into the quest. Signed-off-by: Beata Michalska Reviewed-by: Andrew Jones Message-id: 20200629114110.30723-2-beata.michalska@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) -- 2.20.1 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7c672c78b88..3a46f54f1fd 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -39,6 +39,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; +static bool cap_has_inject_ext_dabt; static ARMHostCPUFeatures arm_host_cpu_features; @@ -245,6 +246,16 @@ int kvm_arch_init(MachineState *ms, KVMState *s) ret = -EINVAL; } + if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { + if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { + error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); + } else { + /* Set status for supporting the external dabt injection */ + cap_has_inject_ext_dabt = kvm_check_extension(s, + KVM_CAP_ARM_INJECT_EXT_DABT); + } + } + return ret; } @@ -810,6 +821,42 @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state) } } +/** + * kvm_arm_handle_dabt_nisv: + * @cs: CPUState + * @esr_iss: ISS encoding (limited) for the exception from Data Abort + * ISV bit set to '0b0' -> no valid instruction syndrome + * @fault_ipa: faulting address for the synchronous data abort + * + * Returns: 0 if the exception has been handled, < 0 otherwise + */ +static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, + uint64_t fault_ipa) +{ + /* + * Request KVM to inject the external data abort into the guest + */ + if (cap_has_inject_ext_dabt) { + struct kvm_vcpu_events events = { }; + /* + * The external data abort event will be handled immediately by KVM + * using the address fault that triggered the exit on given VCPU. + * Requesting injection of the external data abort does not rely + * on any other VCPU state. Therefore, in this particular case, the VCPU + * synchronization can be exceptionally skipped. + */ + events.exception.ext_dabt_pending = 1; + /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ + return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events); + } else { + error_report("Data abort exception triggered by guest memory access " + "at physical address: 0x" TARGET_FMT_lx, + (target_ulong)fault_ipa); + error_printf("KVM unable to emulate faulting instruction.\n"); + } + return -1; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret = 0; @@ -820,6 +867,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) ret = EXCP_DEBUG; } /* otherwise return to guest */ break; + case KVM_EXIT_ARM_NISV: + /* External DABT with no valid iss to decode */ + ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, + run->arm_nisv.fault_ipa); + break; default: qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", __func__, run->exit_reason); From patchwork Fri Jul 3 16:53:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231236 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2563082ilg; Fri, 3 Jul 2020 10:00:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkhgwmjBXo2UcAXiIenGS6A+gZTGhXSsZvYZeWyLkCyJjT+P2DzY5CCbDy16Ev1CSFCS2+ X-Received: by 2002:a5b:347:: with SMTP id q7mr56668621ybp.509.1593795627441; Fri, 03 Jul 2020 10:00:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795627; cv=none; d=google.com; s=arc-20160816; b=Y/zqXNz6yvhMkXeRrhbENGb0jL58Xp3La3PArggj068PXss/jOW7yZsUji3Y0uUtqd WY2jhB307Q1fXD1sMugmQQ+NUjBcva7lHR4b1KBbMZGpeNdenne4F/kiorjY0w4hWUxZ Pg+A03jApzvpyiIegSNwQPBkxItfsfb0LuaQt1ulRKHnrZB+ysY0TfS472q52aLm1KPt wS4aKwHcE2KKSX/LnWPHuBH0JWMhs3hrhXPo+tQwMf6myReSWY86GIZ16wKNLsApDnPY Ewn2NDUGc40EtNGZmAx4c4Ar3fFQ0+2w0ySWmvgZ7GfGcs7iGoKIdo1waHomP9w6XQvg X8Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NlF2IvGuyP8tAoSGk+B5CfV3b2rxriv6aHG+5Yn8DI4=; b=yoGevVKaCedNckz05sMKzxPT6dtIzctvv3oFM2boFgjXFZNW8aA+KqNIvqdb1cs9Yd v5SDSxzlkgW52oGu7Q4/VtNm2jI+rXANEIUyNh9J6RHSdctez4DRmE8+bm0fWJk9ATD0 BjSmQ+PE1cXiM9yQ7JsnfMxuAZ7Kw9JkKHfKK4hsI6QTz3aXTqLRxtL2bJo8K7fxO9qB tDeEmuehLBQSRRuReDDuBV4TcsA5AUk2bwpBm3G3PaIhGtTMjgkqOdK7TfKUVztrUmF5 g9xuumIUa4ku32Xxq9oq2ULZZPrC61wo6yOUI7eblk4uAakiaeUAyFAiurdTiBx1w3kA 9dmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fm44GeyI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a13si11619513ybs.401.2020.07.03.10.00.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:00:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fm44GeyI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP34-0007T2-Rz for patch@linaro.org; Fri, 03 Jul 2020 13:00:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxC-0004kM-0y for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:22 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:52975) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOx9-0005fb-VP for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:21 -0400 Received: by mail-wm1-x344.google.com with SMTP id q15so32631466wmj.2 for ; Fri, 03 Jul 2020 09:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NlF2IvGuyP8tAoSGk+B5CfV3b2rxriv6aHG+5Yn8DI4=; b=Fm44GeyIpKUPL/4dWhfE3ndfVC8mr3y5qY3t7gHW96Y0XITpymKASBlg64Yjxl/Vnk KiSbdUOTnuIjnNIv3QKLdbCkeCF7ibmkMYCVe8jOm4Phf7BYTZQma0HWfgo/EZqNgu9N n5+k0zuTFzSYwt5bP/s3QzKBYnEY0tSKSu9BHIwTypH4sia8QSCw5METqFOhqghoSHUr 1chuvCye+/x4SzaEcoOAampHXyZCFU6R3Gweali3uJPVISaiSPK8f5gJbme+DBL3O05Y xikw0lvg/qn1ETtICMT0rjwu1soV3j+AFJ1PsKaE6fDO8Ceqy8xta5ZbZZCJDJ2ARZOe u+TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NlF2IvGuyP8tAoSGk+B5CfV3b2rxriv6aHG+5Yn8DI4=; b=E/T4PniWujWh4uAIVsK//6u5CO/kbI/5oW4yoS99ll23gjOc7WG3BrAbOqtnjdBpd0 S6ObB6UYi7OrhvGalQXBhlRxLDom+c6vlmRVst+Q+DlaHv6N3uaqMEuq4Pc2Bb6qPCzo cuTnxVY84k61CWmS7mUa2qLRBz9IMTTednxS/WTsaZT1nEh099OHbWwpXd+pE1WOybX6 3zhBrbQp1r0qAJQofjOLha0pgn6oTCwguUXrjpXsSwYkPT4Rixhhd2V2FiB2coovTC9J KhMmr3+2RaM6ufCHRjBqzPvKSguceJzcZg0IRi1oQlHtw1sQSfqnfKzHKvRxjvAlh2Jo nNfA== X-Gm-Message-State: AOAM532u7NaD+bF5PVC66YaSmzDXTkDErbnPzyQ8jB2xWQ/6pZSA3s4A k0intiAB+gXc9c7bALffukX4qsR/mRSoyw== X-Received: by 2002:a7b:c313:: with SMTP id k19mr23042995wmj.67.1593795258239; Fri, 03 Jul 2020 09:54:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/34] target/arm: kvm: Handle misconfigured dabt injection Date: Fri, 3 Jul 2020 17:53:41 +0100 Message-Id: <20200703165405.17672-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Beata Michalska Injecting external data abort through KVM might trigger an issue on kernels that do not get updated to include the KVM fix. For those and aarch32 guests, the injected abort gets misconfigured to be an implementation defined exception. This leads to the guest repeatedly re-running the faulting instruction. Add support for handling that case. [ Fixed-by: 018f22f95e8a ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests') Fixed-by: 21aecdbd7f3a ('KVM: arm: Make inject_abt32() inject an external abort instead') ] Signed-off-by: Beata Michalska Acked-by: Andrew Jones Message-id: 20200629114110.30723-3-beata.michalska@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/kvm_arm.h | 10 +++++++++ target/arm/kvm.c | 30 ++++++++++++++++++++++++++- target/arm/kvm32.c | 34 ++++++++++++++++++++++++++++++ target/arm/kvm64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 124 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cf99dcca9f3..9e8ed423ea1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -573,6 +573,8 @@ typedef struct CPUARMState { uint64_t esr; } serror; + uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ + /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ uint32_t irq_line_state; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index a4ce4fd93db..adb38514bf2 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -449,6 +449,16 @@ bool kvm_arm_hw_debug_active(CPUState *cs); struct kvm_guest_debug_arch; void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); +/** + * kvm_arm_verify_ext_dabt_pending: + * @cs: CPUState + * + * Verify the fault status code wrt the Ext DABT injection + * + * Returns: true if the fault status code is as expected, false otherwise + */ +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs); + /** * its_class_name: * diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 3a46f54f1fd..8bb7318378b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -749,6 +749,29 @@ int kvm_get_vcpu_events(ARMCPU *cpu) void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (unlikely(env->ext_dabt_raised)) { + /* + * Verifying that the ext DABT has been properly injected, + * otherwise risking indefinitely re-running the faulting instruction + * Covering a very narrow case for kernels 5.5..5.5.4 + * when injected abort was misconfigured to be + * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) + */ + if (!arm_feature(env, ARM_FEATURE_AARCH64) && + unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { + + error_report("Data abort exception with no valid ISS generated by " + "guest memory access. KVM unable to emulate faulting " + "instruction. Failed to inject an external data abort " + "into the guest."); + abort(); + } + /* Clear the status */ + env->ext_dabt_raised = 0; + } } MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) @@ -833,6 +856,8 @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state) static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, uint64_t fault_ipa) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; /* * Request KVM to inject the external data abort into the guest */ @@ -847,7 +872,10 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, */ events.exception.ext_dabt_pending = 1; /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ - return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events); + if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { + env->ext_dabt_raised = 1; + return 0; + } } else { error_report("Data abort exception triggered by guest memory access " "at physical address: 0x" TARGET_FMT_lx, diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 7b3a19e9aef..0af46b41c84 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -559,3 +559,37 @@ void kvm_arm_pmu_init(CPUState *cs) { qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); } + +#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0) +#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2) +/* + *DFSR: + * TTBCR.EAE == 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE == 1 + * FS, bits [5:0] + */ +#define DFSR_FSC(lpae, v) \ + ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F))) + +#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08) + +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint32_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint32_t ttbcr; + int lpae = 0; + + if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE); + } + /* The verification is based on FS filed of the DFSR reg only*/ + return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae)); + } + return false; +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3dc494aaa7e..11692379055 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1493,3 +1493,52 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) return false; } + +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) + +/* + * ESR_EL1 + * ISS encoding + * AARCH64: DFSC, bits [5:0] + * AARCH32: + * TTBCR.EAE == 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE == 1 + * FS, bits [5:0] + */ +#define ESR_DFSC(aarch64, lpae, v) \ + ((aarch64 || (lpae)) ? ((v) & 0x3F) \ + : (((v) >> 6) | ((v) & 0x1F))) + +#define ESR_DFSC_EXTABT(aarch64, lpae) \ + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) + +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint64_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); + int lpae = 0; + + if (!aarch64_mode) { + uint64_t ttbcr; + + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { + lpae = arm_feature(env, ARM_FEATURE_LPAE) + && (ttbcr & TTBCR_EAE); + } + } + /* + * The verification here is based on the DFSC bits + * of the ESR_EL1 reg only + */ + return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == + ESR_DFSC_EXTABT(aarch64_mode, lpae)); + } + return false; +} From patchwork Fri Jul 3 16:53:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231233 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2562075ilg; Fri, 3 Jul 2020 09:59:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwiQD9GVd9KFhnkOrQBmc1+2M+dk5EIoU0XlgCgSYMPeHp70LZvjlEfNKD9o9mQWYLEBJe2 X-Received: by 2002:a25:1ec3:: with SMTP id e186mr2579234ybe.82.1593795542372; Fri, 03 Jul 2020 09:59:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795542; cv=none; d=google.com; s=arc-20160816; b=n9Zx2IXEeVZL44lY5/M3ALCEqbPq2KWtxeaerjNQFhD6g6rduhJCMl5sBT3Gl8uTCR m+VGquyrlTtri4IryOWykLo5IIMLrXdJtu3vcqGrBy4o5TEipL6lq6YChGQqlhUB26kL Pig9Mr4HvSkYPcNtCt0G/mZcvaSrdjXhnHxUHFL/sxOFN0fbXAdcBBUH0JCOdWYEotye Wkq2VEQbNlUYER0q2a6wqicIRzYQ9JfQ91uHWT8FJ+CAVVkSQPQYRtmKvYOS91kAE/Ed vr4p8cjAHtB9HfcZUB82esIVw+nwV+GtDrwBJcm/pXvwNO3vBhhHUTFNT1ltnuKHYiVi bm0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kPIFln/ZZd6iY5dygLSdbDis7siBbqefdWWfXW/oq8c=; b=BADpBZ/OQm7Jr1RAgzwwIotezRDmkkGhHusQfXahcTVvovmqJFUhv69uAjqAn/vA0k ilIs8FP7kjOSZsuNZIxoC7ShGmuoW3QYkq1AAkmn1cda6OX+uzTE/3NRzR7kwF1Zfsx6 vvHPBp0FkM6TWUnDsNGL69Tt+TR9iE75A0N7vc0SPev62+2h6GLE4ghSwCkZg6G0OelG pefqdTMETEuXHCgsIbFwzKVkE2dsdX1MSBddhMDOiADv9N6hQ01F8vU76YFnlYoIQnVR e2ZhyG98MNRAkdGn0NgJe5JjvRr/+ORSz/7XO7oPbiW98xKYEljyxBqXGTX2n6ugq9aT JmHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="D1VJ+Z/b"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g29si4852519ybj.11.2020.07.03.09.59.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:59:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="D1VJ+Z/b"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP1h-00045E-QF for patch@linaro.org; Fri, 03 Jul 2020 12:59:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50058) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxC-0004lh-Hp for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:22 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:38474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxA-0005fj-Uh for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:22 -0400 Received: by mail-wr1-x431.google.com with SMTP id z13so33425843wrw.5 for ; Fri, 03 Jul 2020 09:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kPIFln/ZZd6iY5dygLSdbDis7siBbqefdWWfXW/oq8c=; b=D1VJ+Z/b9X9wAPjRAJarSkLmuFafFb7Mns36BzzFhSdOYgJ676oripoY6GlfRqkJ8q VOpZ+uQz15mj3I2I+LqoKOtIwHdFvKNxiwNylaW/3rO7u7QCQWfER7oA8pw9QIyey+Ed 1SQtbPIVGNjl0ZCqyp+ZaOBvoit2Qk3y8HxrcW4t/yB31dTrwOe36atapLh34qLHvYPP NsM+dfmNz5GOoKU9o77UcDWON2ldNlzPMUKNQAIqJWNr8Dx34Wu7wWf//lG0R3uCESaW wc+/phlunCSIdwC1AeH/4lWFNbkNshM98w23Fv1go86xpT+1U3IvAdXzlzxa/dvaJiv/ 8J9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kPIFln/ZZd6iY5dygLSdbDis7siBbqefdWWfXW/oq8c=; b=Bz43f1gc9WNomHbXkU02gqSKq9ctKmDWfrf8igK8kEGS5FO9X3edfyJIX5aMUf/I0+ YRzooLLetHzRACW/Gv5Yj/4Wlqexc7e1NTwyzj5M4u5rmHAPfUoWA7/13RHzeRBFyG4D pgGN+XQS9FwBbBhk1B+V1XuH6b5TaQJZgiGhSYvZ7ba13w5k+VIp6HwDD8wTBhWsjXSE dbl7B9LSWqinKofGf2rRUZdSaQVbXZ5ArT1m+PhLzO4ejlUSASOzW7dDGDd1HqbXMmL2 pNu8VKw+LTXhPaZ4jEe3v0wINFJn5ZdvoC2aFQcmp0i6sx/t+y15zW6Vabcg7m43Su3c K+Rg== X-Gm-Message-State: AOAM533CEKitdvjoyfXE2jq9JGbz+dcZ/xQPfNTqvp9WSNxuRf69a5ON uCBSdU/1RrUaSbnjjJvdtdbhRCCkWimAxA== X-Received: by 2002:adf:e850:: with SMTP id d16mr39253987wrn.426.1593795259234; Fri, 03 Jul 2020 09:54:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/34] tests/acpi: remove stale allowed tables Date: Fri, 3 Jul 2020 17:53:42 +0100 Message-Id: <20200703165405.17672-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files") Signed-off-by: Andrew Jones Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Auger Message-id: 20200629140938.17566-2-drjones@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------ 1 file changed, 18 deletions(-) -- 2.20.1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 8992f1f12b7..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,19 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/DSDT", -"tests/data/acpi/pc/DSDT.acpihmat", -"tests/data/acpi/pc/DSDT.bridge", -"tests/data/acpi/pc/DSDT.cphp", -"tests/data/acpi/pc/DSDT.dimmpxm", -"tests/data/acpi/pc/DSDT.ipmikcs", -"tests/data/acpi/pc/DSDT.memhp", -"tests/data/acpi/pc/DSDT.numamem", -"tests/data/acpi/q35/DSDT", -"tests/data/acpi/q35/DSDT.acpihmat", -"tests/data/acpi/q35/DSDT.bridge", -"tests/data/acpi/q35/DSDT.cphp", -"tests/data/acpi/q35/DSDT.dimmpxm", -"tests/data/acpi/q35/DSDT.ipmibt", -"tests/data/acpi/q35/DSDT.memhp", -"tests/data/acpi/q35/DSDT.mmio64", -"tests/data/acpi/q35/DSDT.numamem", -"tests/data/acpi/q35/DSDT.tis", From patchwork Fri Jul 3 16:53:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231240 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2567244ilg; Fri, 3 Jul 2020 10:04:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwLVTH7tetus5Ne0pLZOV8jse9C0h66fbisu/UKDeAA7Zv1lr4xnqfMDngw+ZNOCgD+Anpr X-Received: by 2002:a67:d01a:: with SMTP id r26mr9380038vsi.200.1593795887656; Fri, 03 Jul 2020 10:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795887; cv=none; d=google.com; s=arc-20160816; b=S/XitQPNx/4KjF2TOA/8Ff6Vas4bcn4rA+F/z6ztYkA0oxvMbJRMzjZw1EW6HA3fLr dzrgGXmUJwL+K1sfmOJT7KECChriQsxGzV6I8ZR7N+knnbigtPJ3wNvwlSfEYDQv/sQg LlL5UP1IHqgJAmNfCFu0+sj74kglxyDE/R4ffqbzxg5HJpCeHICnppTXnQy4X+/G7M9M 21Il9qTLWHDjU2fbrvP/31OU8kcDtINSemvEq+ngRpvUWWtkhXe6EYO2ONfb7iby//Vl jQZSXXYLCtB8X9Zf9sRPcESAupHhSpRb6m0i+pmkYmKZEOosY/heWQIEvr80seWK18Hg twoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=W1X/QFKetqy4Cccjm+5hRIiHrC/Te/v1h263Fqb3yTg=; b=tAgP3UXCIWqlYHiFVujKqbTvkfRnsLAffZn2iUuvseHiWWYosl6p1od/22i4WCwFTH ngEW4lzWSJuiJwPOwRvO5ZlP4dTZLf3D6kLIqt5xxuEd9rJvkFdktKWtHZWnq8c40WFx YFCtzOEmo4ufLvuwVMsuO+BoEJmsG1ye8P36PSJClR9No3M0HuWIbVeVhZF523Q3iBxu hPaxUyaFu8pxFOKO2Fb6BaD4R7uYVxN5jh57U9SbDSRUif3M+cElTqGR6htxUXNmKkbt RHWgH/vDEz8gXY836F8CVBUWTzLXdKrQ2IoKHiH4MRcy3RCnRDz7BShovYUDsOQRoxLt l7IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XZ6oMUt8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g19si1986631uak.70.2020.07.03.10.04.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:04:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XZ6oMUt8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP7G-0003CG-Ub for patch@linaro.org; Fri, 03 Jul 2020 13:04:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxD-0004p4-SZ for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:23 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34158) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxC-0005fw-3X for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:23 -0400 Received: by mail-wr1-x42d.google.com with SMTP id f7so30413038wrw.1 for ; Fri, 03 Jul 2020 09:54:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W1X/QFKetqy4Cccjm+5hRIiHrC/Te/v1h263Fqb3yTg=; b=XZ6oMUt82NR/6x98+Unfy/x/28+AIltZsqU+UyGjszIwnwTGPuy5GIMT2dBi3Uh+rN NEvny0x3+Knlb9vM1gxD/iyyc8fYiVkUsRaza6aUst6ROCxYE/sq0Rq3QNa/zwYw6E2B aaLPZYhRIuVz2AU7j8yESBWliCTGMn5BVNTz2WwuzLOcvTP73JQY2bU2cP8/jBzTLmjJ UNr8ilwTv5tJjjWXfq3JBYfVkOK6n2Uaon+xfNseS1EOWLIZNQA7eKeKK6ZATBhQR3xz EfV3wTjPjlD3eSSBKV4WdcQUWg+4Iyv1NiFHVkqIv1DpKaqMUIdcK1ZvoKOKrzfQJaIq BuZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W1X/QFKetqy4Cccjm+5hRIiHrC/Te/v1h263Fqb3yTg=; b=Wv7w2hEuBRofkHcRPy6k9qTvibWmmBb1dUa6dASltmpHhlLUU4zMuUefk9GIXd6lfL wSR+yYWoYg/IHZg4zOhLb8GHLYwIpy2DyDSWYyzw9omi1io2irGjTBusrhmBXP/FR3LU Ecly6mecxbhVwG2/ZTl1XltgK0EFeqgbiCzfnWtEEIrSBi2BvZBrEa3gOP084VOE/IIO 5V3fMwrmLaWTiW58EAEkSa+VWKv3E0s+sIW9qSZsexgd2eLNLF89xGQ1EBjlBxhmahKT QDD9Y0oBxlY219xZ2PE8Ad8L270N3o04YtUrwePfR7Wk3zEx3Ui0clOQxKce0gxwIrKS BpBw== X-Gm-Message-State: AOAM530KRQFTSTl6aIVGbYfFQ7dT695NBu9CjKF1g001DQAfRvmvh+vz 6cN8c6G9gRUWaIsInS7pOI9ts8D+JPR9zA== X-Received: by 2002:adf:de8d:: with SMTP id w13mr37058191wrl.129.1593795260370; Fri, 03 Jul 2020 09:54:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/34] tests/acpi: virt: allow DSDT acpi table changes Date: Fri, 3 Jul 2020 17:53:43 +0100 Message-Id: <20200703165405.17672-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Signed-off-by: Andrew Jones Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Auger Message-id: 20200629140938.17566-3-drjones@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.20.1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf..32a401ae35f 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/DSDT", +"tests/data/acpi/virt/DSDT.memhp", +"tests/data/acpi/virt/DSDT.numamem", From patchwork Fri Jul 3 16:53:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231234 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2562080ilg; Fri, 3 Jul 2020 09:59:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGDbkLMenGZ4fqMeVfdE4SQhsTUUNE0Xo4NuzyOmMjjkk2XTRGbd4Bz+ULIAi/u/O1MaK7 X-Received: by 2002:a25:bfcf:: with SMTP id q15mr52563216ybm.39.1593795542824; Fri, 03 Jul 2020 09:59:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795542; cv=none; d=google.com; s=arc-20160816; b=Cfc33kOuRJ3Oh/pai69GJgMLQvTYJqzIgyGL50D/UdO5stSboUM4TQwAXfMtORKiy6 hFDib4+QuLidxFBFbNPWwZDBXaI45yx4lCFV700bfgQ8Jwezv2FI/eQoDUHh13e2L102 ZEBG8ncss2oSZSrIfcYHQE7wuRk0dTDSHJvL2b6bdmTh+OQ3qsMCaFKWfM546JbGWeY7 rRhbH+DY7Y3/R3w1lDAbTP2HVOiXTH8u+RarUNEeyU4a3E3YS53GM/U4T9nJqgBqm1Hi aibFnO+UYdp+lV4K01SoaDuvSeYh7EBb2p4Siu3JC57jz/p1WG5QEMwIziPi768uMbEE K9Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=t4lZzsSpepDD5cI4hs6XR5J1er+4ioMQ77URYxpBa+8=; b=mV1PSfnOQNa33UkamFCDq0t+iCLkL9v7+O6yjG1sN9ew07D9d77jPWZ2h2TMSELf92 yQoMAaRWjnKLYg9yTJRCPFjXOpxvG90r+n4r4pgdSQgZVeOuf7MPFaOZqy8qR1Kaucvb PwdZECwpN1zQsIJ6ovrlshNSK7qmuI+ulAmYlipSvZruGzvHITnVlJ75WICOE1Dkim3j xTz1iZ9qIVEe8A5Jx3SPcsvnRpeKEY6WZ+2l1A2iZa9YAjlUNiHns5ljOp8uz2rM20fX H7v/zjZh+1EfEHNmqBttE8MdKt6eWBPelvCoSK+KveA3FQMo9WL2PdDJK9zO2mYuaXA7 c7sA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Y/6IMKQK"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r204si12997271ybc.324.2020.07.03.09.59.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 09:59:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Y/6IMKQK"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP1i-00041p-9i for patch@linaro.org; Fri, 03 Jul 2020 12:59:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxF-0004rz-3H for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:25 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:42920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxD-0005gD-8o for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:24 -0400 Received: by mail-wr1-x429.google.com with SMTP id o11so33439868wrv.9 for ; Fri, 03 Jul 2020 09:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=t4lZzsSpepDD5cI4hs6XR5J1er+4ioMQ77URYxpBa+8=; b=Y/6IMKQKXzoF/+fEKcbdeVdW2xYF0jeP2p7X1bLZ0reDujx6u2/C7DKzKUL2NmibW0 0JeGEPY3rvkt4EKPNDbGJ/bsJsPLbEiG849/aA/rnwH/BsMNUqVZA3ilW7SS2TLabuYk ZZcbqEaXbiPGYqToQgbfxN38s9u/uU1SijmHczNsS4hTvyvxrR52oUGUW2lTLAM5HLuv 1V87M+ZyLX0ahDTwXQSIRrJO8pCDT60/5J+tzVX+2/AAE4oKGnlOzqkktDXuIZo/7ABY 3DfcQCg86ACSHyFFCUdaNREteGOv2at8d787lU6v60n2kjZ8IWwoc67Rfe0j2GPAx02k ckzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t4lZzsSpepDD5cI4hs6XR5J1er+4ioMQ77URYxpBa+8=; b=qFrkMVCVWsqyKTeevAbF9vjamadLpYwfg7J8J50rYZfQwPDug5+Fm5+UKVqQOhvH+F 6W40mT5p/hk9yn8sava6wVALzh4puVfRJXpjsp8sPHlWmDr+nDTwYzZnxA7FviXvvBE1 gcn8+EsunDJbsgPi7BoqqGBkNDH/1M6+bm6y8Nen5nrwD3jym2fxgm1X48mGqlMOd0eR fc0i/bWd8r3+Oj3HaJbOm3TUiCMspNG4u2yb3LyYGsmXvjdez6lDrKbm6PDKqvtqra+A yYPeRCiBtDB4jpHXdW5pH7HY3Dpsui2Ydh3upI9TZS1UMD3Fc9VLG9nwyCO7AD5I/V+s 5Llg== X-Gm-Message-State: AOAM532CgdIifFUlHu9YQ1BBBtKtlBVXt0KBQqTSYmCd6BfDjdmY9F74 wQ5GjWzwBA9rQrrPw3O2IvT5J8I8E5ioaQ== X-Received: by 2002:adf:dfd1:: with SMTP id q17mr35567807wrn.94.1593795261429; Fri, 03 Jul 2020 09:54:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/34] hw/arm/virt-acpi-build: Only expose flash on older machine types Date: Fri, 3 Jul 2020 17:53:44 +0100 Message-Id: <20200703165405.17672-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones The flash device is exclusively for the host-controlled firmware, so we should not expose it to the OS. Exposing it risks the OS messing with it, which could break firmware runtime services and surprise the OS when all its changes disappear after reboot. As firmware needs the device and uses DT, we leave the device exposed there. It's up to firmware to remove the nodes from DT before sending it on to the OS. However, there's no need to force firmware to remove tables from ACPI (which it doesn't know how to do anyway), so we simply don't add the tables in the first place. But, as we've been adding the tables for quite some time and don't want to change the default hardware exposed to versioned machines, then we only stop exposing the flash device tables for 5.1 and later machine types. Suggested-by: Ard Biesheuvel Suggested-by: Laszlo Ersek Signed-off-by: Andrew Jones Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Auger Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laszlo Ersek Message-id: 20200629140938.17566-4-drjones@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/virt.h | 1 + hw/arm/virt-acpi-build.c | 5 ++++- hw/arm/virt.c | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index a18b6b397b6..54bcf17afd3 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -125,6 +125,7 @@ typedef struct { bool no_highmem_ecam; bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ bool kvm_no_adjvtime; + bool acpi_expose_flash; } VirtMachineClass; typedef struct { diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 1384a2cf2ab..91f0df7b13a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -749,6 +749,7 @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, static void build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); Aml *scope, *dsdt; MachineState *ms = MACHINE(vms); const MemMapEntry *memmap = vms->memmap; @@ -767,7 +768,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) acpi_dsdt_add_cpus(scope, vms->smp_cpus); acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], (irqmap[VIRT_UART] + ARM_SPI_BASE)); - acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); + if (vmc->acpi_expose_flash) { + acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); + } acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7922f3c23a5..c78972fb797 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2510,9 +2510,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1) static void virt_machine_5_0_options(MachineClass *mc) { + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_5_1_options(mc); compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); mc->numa_mem_supported = true; + vmc->acpi_expose_flash = true; } DEFINE_VIRT_MACHINE(5, 0) From patchwork Fri Jul 3 16:53:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231237 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2563093ilg; Fri, 3 Jul 2020 10:00:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw52ZsUqeo17hnFJd0nJ+qvfne5lLfBWuNUDJDM69CPdTw4aULDcesdnW26YPMgM9L6S64+ X-Received: by 2002:a25:d786:: with SMTP id o128mr60621871ybg.244.1593795628283; Fri, 03 Jul 2020 10:00:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795628; cv=none; d=google.com; s=arc-20160816; b=UywomjMwn2cYAIGz6KvguhnlZeeP9nl/3CypwkHwV8ky6pxHM0pQfLcBZk3nN8OYbS j0YhHS+Y9KiJLVqgOgqgjJnNEfyxqFUXOxckmSPO6tn4aVaaqMNHrTln/DtL/h5HmUn5 /2ldYY8BTMbZPPDQkqJ5exWCYG3e/8NeAjPpdpriQMX0fFTONu9GwVMWvtWJw8oHyaxb kF/eOe7Zs9Lu/EDJ2lxpB6TpqwCB+W4dXsF9rIaFhHWIrl1jUwDAT0PCA9bO8cmw5YVA iBbRYdFtPWgcCvvVAk4uf2djfCuT4UO7A3Lo2x4Ler3/xkgR1U1Sptw/iJ+IcgQs6ID7 +eEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9kAWMFDfNy8onp4hyShw/LbQqFC+n+LfYN6Nfvd1C+w=; b=iMwvO0bWNHDvvpc/Jqe0zlqTQBSr2+3E8PWjqldeOf93LFBHnLYiNt62pMyO5dxsTE mdpsP+bMkAcIEl7KbgIpay1VQT5w7P5r2BTKOCuWilpMQxUnALi9DsQU1vitG2NYZG+Y 3iZhoEAhTysE5oBs0TkUpCqvV52gZUgJn25V+zQy2P7TrMSVwQf2J4goCEU/9TFOQoO0 U9tw+H4qEk0BU7lap8o7zYe55NpoxdB5+HfHpplSrfUdupdWBbm1B6XAsCfLg5/sY8TW uy7XCoXBrbu21QBUcKKt8AUMcCVvQi0N27OzFlirOi6yl5X3Ha0kJaDzG8K57PjMizvS BoSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nxj534JX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 136si11375923ybf.378.2020.07.03.10.00.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:00:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nxj534JX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP35-0007VX-K2 for patch@linaro.org; Fri, 03 Jul 2020 13:00:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxG-0004uZ-39 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:26 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36933) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxE-0005gY-7u for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:25 -0400 Received: by mail-wr1-x436.google.com with SMTP id a6so33423433wrm.4 for ; Fri, 03 Jul 2020 09:54:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9kAWMFDfNy8onp4hyShw/LbQqFC+n+LfYN6Nfvd1C+w=; b=nxj534JXbR27vnm+DlOtxxQznGjecqPPL+NlrG23Mm/6o5KOKbK7IJyShJ6h436n49 3vsB3MWMLLTvn14P5k3tMqyn1WIwkIR5XDwJxvFXykF5TLmOX2dKqXtQCXAy24CWXXPO aNYE7WMOJwWEPaTeTDvlQfpt61dhcHiMGfGaV4395pKfIRrUzBmGXMrQMrttaEQmc9dT 6Q1H12vVHfwx5gPLcjFZ6V6/RNu3cxTWdb70dskYtEzOLY8JCrDL9kaZdWVQwRXqhumx GIzYpLUvJz3lCoosEbXRsZiE5Ow4g3L2dOiPQRpzR67hO149sndNBawIly7bw/pj+7+9 JCLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9kAWMFDfNy8onp4hyShw/LbQqFC+n+LfYN6Nfvd1C+w=; b=qcKm3MkVpXpFgZlJ8xSFCtj7K0a05n6GMKB3c1MA/HyRLy5BPz9VIL+RsQZTjWAr+D Wn+cZDKAKHT7KKku+74tCdVPlY5Qq9ZCA4eUm6GlyvrKPuUuZdyXxSdDQq8Su4h7eAVX Ik81M7pUswuYLYz00HOye2pQI2Tq8VyfJUZPZjj9W6xpCZY8/mbF+DRSWUH0SwI5tG1S UeO3hdaMT6cVXGAg0g2LE8KVnW1vNrvyXu0TxtLkpkhN7mMzZWfEJVnKBD/wGemecTjm 0uAONaPvYz4dDR3eECNcPjYH6t1N3DCaqZZuqYdESf2GNL7ApVqWcFAx8OF519t4174l 70Xw== X-Gm-Message-State: AOAM530J+l0DdDiP/B/ehTEhgC5lSBh8ds3PecSXaJWsHaFEET3Dn93m /mQKC4QRuREfEW4JHPeRPvooGVAhpSPm0A== X-Received: by 2002:adf:fa81:: with SMTP id h1mr37889569wrr.266.1593795262550; Fri, 03 Jul 2020 09:54:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/34] tests/acpi: virt: update golden masters for DSDT Date: Fri, 3 Jul 2020 17:53:45 +0100 Message-Id: <20200703165405.17672-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Jones Differences between disassembled ASL files for DSDT: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of a, Mon Jun 29 09:50:01 2020 + * Disassembly of b, Mon Jun 29 09:50:03 2020 * * Original Table Header: * Signature "DSDT" - * Length 0x000014BB (5307) + * Length 0x00001455 (5205) * Revision 0x02 - * Checksum 0xD1 + * Checksum 0xE1 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -45,32 +45,6 @@ }) } - Device (FLS0) - { - Name (_HID, "LNRO0015") // _HID: Hardware ID - Name (_UID, Zero) // _UID: Unique ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0x00000000, // Address Base - 0x04000000, // Address Length - ) - }) - } - - Device (FLS1) - { - Name (_HID, "LNRO0015") // _HID: Hardware ID - Name (_UID, One) // _UID: Unique ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - Memory32Fixed (ReadWrite, - 0x04000000, // Address Base - 0x04000000, // Address Length - ) - }) - } - Device (FWCF) { Name (_HID, "QEMU0002") // _HID: Hardware ID The other two binaries have the same changes (the removal of the flash devices). Signed-off-by: Andrew Jones Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Auger Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laszlo Ersek Message-id: 20200629140938.17566-5-drjones@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 3 --- tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes 4 files changed, 3 deletions(-) diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index d6f5c617881c4247f55d4dcd06581f9693916b2f..e669508d175f1e3ddf355f8a9b0d419266cac8aa 100644 GIT binary patch delta 28 kcmdn3c~yhUCDET2!X{H9}iRuX(-<}f&0DgxFc>n+a delta 156 zcmcbrv0IbNCDP_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5 LaERl^1zUvy_;n(J diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp index 730e95a46d2cce0af011ffc051d7342beb8f1328..4cb81f692d73526542493a0c4da9c9793cc8366e 100644 GIT binary patch delta 28 kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910 delta 156 zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^ zEET2!X{H9}iRuX(-<}f&0DgxFc>n+a delta 156 zcmcbrv0IbNCDP_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5 LaERl^1zUvy_;n(J -- 2.20.1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 32a401ae35f..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/DSDT", -"tests/data/acpi/virt/DSDT.memhp", -"tests/data/acpi/virt/DSDT.numamem", From patchwork Fri Jul 3 16:53:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231241 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2567257ilg; Fri, 3 Jul 2020 10:04:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx0qxjAKGlwr97cQTb7QbhLtmGkfMvGjifbsB1to2Se0Z80clsP5hVL9Pr+gsVa9bouD8bi X-Received: by 2002:a67:1b85:: with SMTP id b127mr23882517vsb.152.1593795888573; Fri, 03 Jul 2020 10:04:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795888; cv=none; d=google.com; s=arc-20160816; b=FgbUpGUjfO+W1/nJAA7MKo2+MnCfv3nk7HwddHhyg/Op/JuBprvBBZRurGb6jQbhtM huuqbHjAn2nEtAz5MDBMyEroXel6j2+jNeNHJKM2XbGm9NyhMWeRvwrMuftrhWOuJMxX M5CV+mKEQ5N2G2WdVgF/vfVv02yj/1UhfOZIpBuzdahaE0NBpQOIgYKatvNiO5LkMjTe DEKxoFz3HxXLiGc3dqZ4OwW7YHuD5JDrRAf+KsanTDp0tgY7p9jDV317ieeuhIPkqhtF g2EqbRfiWCmYENuKLnqhe/q4QdCmJQKF9kRxEOOhzI34WAO0TBK6UJdWp+uUXshcVx6j x5NA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iUQU2oplSMWnXTckOnwpuiVAWqwg6rxiHqd3JFEyT8I=; b=PVH6TTCagvkaVYeIWf02zPfVQFN+LVTZ367VZfy3q/dVsgE71A0evnv0z/KrxyBgAg ur28zqXRPqk0hz3BH1lrGcPKCX8srBDMgMg4qaLZxM1NTH92+XLmgFvsPxJRiujgZjlc 7X3GG9CmQ850MJWgjUI2XQoeA4edYG+MC0dcPV5lzbvXPaQ0G3UrsPgfuhFZajKWELUK t9ffR3ND5AulKAgC0nccRqAcyGkjlDEVZ1p76JL6uVkMotkkwn0fUW0U2Mo4eRpI/Krm xr1fDuxkYUwlpNeG2HBc2wT4esT386BjObHMLn1NFDMrGkriDYYb+o5MZf09cLv5iOXf mb2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U96guFZB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 84si1761086vks.61.2020.07.03.10.04.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:04:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U96guFZB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP7H-0003EC-Pi for patch@linaro.org; Fri, 03 Jul 2020 13:04:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxH-0004xa-9v for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:27 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:39917) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxF-0005gj-Fj for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:27 -0400 Received: by mail-wm1-x32a.google.com with SMTP id w3so22288991wmi.4 for ; Fri, 03 Jul 2020 09:54:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iUQU2oplSMWnXTckOnwpuiVAWqwg6rxiHqd3JFEyT8I=; b=U96guFZBkr7NARRWba9BUEWURYSCfBM2X7oUjQqWA4jcfdTSNyuEWAM8YU01tHuqeZ kYvyWgG7ov8Y6wTn2+4QxHge860sOttrLlz/OHAyNrcS3eHD9N3EXzfA87+y3NR9MMA1 0hQwyKw5pCFSxsP8IH7hTbjN8S8f3lN1UU40bkR1vAcc9yef0tyLT+So5bx/AoD0kft5 5vhh0pmR10m7KhUsStMTPJexFrzRG8bFACkAoKPsUMvmkZP3yy9b3gDdE2/QfOIRGUzw gsHqaZrTa+eVtNSOeEC1IBtgn59opCj9JK0TmvjLAkl3gUIFA2kG6vbQGzNjJNEzoe9W +f6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iUQU2oplSMWnXTckOnwpuiVAWqwg6rxiHqd3JFEyT8I=; b=GX+xyss67knSA0Y92mSelWm0AvJWv4kWy1SSl4RgXcTmqr85Dxz8+qDSJhtwJ2gjSd 0Ze+MEY9NLdIg676yE889N0qSUB6xOUNu24t5Xhz859c2BZi7YN6cqBRWLvHKFi7lkQj 88SrSLaH7R8ECX3ja4RL6sktlag0oeyki2U6VKizb71jCN5v1KN+1T/djfqntYGqBg/F FnNq4jk9azdGMv9PvCP6gcNGSugL3fCUBBvuR5KNkL6cEn9ViGhnrhNp3cTatLs8c9lP WfLy9jEuNtDzM2s2U+8pQ9NcoKKReStUBdAuIT8Ux9g/4KY/66KubvPr/x/8Szvhk7/8 9b8w== X-Gm-Message-State: AOAM532lFUfpJnQ5YglonvPrRls9hrocrSMvSIK+xWbbt5nR4rdqM70i PI8JxzZQYGMSNOhlS+YabVZ5MVI7Y30oAg== X-Received: by 2002:a1c:2257:: with SMTP id i84mr36890908wmi.158.1593795263785; Fri, 03 Jul 2020 09:54:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/34] target/arm: Fix temp double-free in sve ldr/str Date: Fri, 3 Jul 2020 17:53:46 +0100 Message-Id: <20200703165405.17672-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The temp that gets assigned to clean_addr has been allocated with new_tmp_a64, which means that it will be freed at the end of the instruction. Freeing it earlier leads to assertion failure. The loop creates a complication, in which we allocate a new local temp, which does need freeing, and the final code path is shared between the loop and non-loop. Fix this complication by adding new_tmp_a64_local so that the new local temp is freed at the end, and can be treated exactly like the non-loop path. Fixes: bba87d0a0f4 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.h | 1 + target/arm/translate-a64.c | 6 ++++++ target/arm/translate-sve.c | 8 ++------ 3 files changed, 9 insertions(+), 6 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 49e4865918d..647f0c74f62 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -30,6 +30,7 @@ void unallocated_encoding(DisasContext *s); } while (0) TCGv_i64 new_tmp_a64(DisasContext *s); +TCGv_i64 new_tmp_a64_local(DisasContext *s); TCGv_i64 new_tmp_a64_zero(DisasContext *s); TCGv_i64 cpu_reg(DisasContext *s, int reg); TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 73d753f11fb..8c0764957c8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -461,6 +461,12 @@ TCGv_i64 new_tmp_a64(DisasContext *s) return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); } +TCGv_i64 new_tmp_a64_local(DisasContext *s) +{ + assert(s->tmp_a64_count < TMP_A64_MAX); + return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64(); +} + TCGv_i64 new_tmp_a64_zero(DisasContext *s) { TCGv_i64 t = new_tmp_a64(s); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f318ca265f2..08f0fd15b28 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4372,9 +4372,8 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) /* Copy the clean address into a local temp, live across the loop. */ t0 = clean_addr; - clean_addr = tcg_temp_local_new_i64(); + clean_addr = new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); - tcg_temp_free_i64(t0); gen_set_label(loop); @@ -4422,7 +4421,6 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_st_i64(t0, cpu_env, vofs + len_align); tcg_temp_free_i64(t0); } - tcg_temp_free_i64(clean_addr); } /* Similarly for stores. */ @@ -4463,9 +4461,8 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) /* Copy the clean address into a local temp, live across the loop. */ t0 = clean_addr; - clean_addr = tcg_temp_local_new_i64(); + clean_addr = new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); - tcg_temp_free_i64(t0); gen_set_label(loop); @@ -4509,7 +4506,6 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) } tcg_temp_free_i64(t0); } - tcg_temp_free_i64(clean_addr); } static bool trans_LDR_zri(DisasContext *s, arg_rri *a) From patchwork Fri Jul 3 16:53:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231245 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2568483ilg; Fri, 3 Jul 2020 10:06:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7PbctZjitMssgVYT0Me5E/qa8xxSMhObnswN5itQ6vixeWKDzdKQB96/UyN/MiOLvduim X-Received: by 2002:a25:9305:: with SMTP id f5mr11380419ybo.331.1593795979111; Fri, 03 Jul 2020 10:06:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795979; cv=none; d=google.com; s=arc-20160816; b=PScNy30d1+dLvzcnmhNmvjf3TG+E8x0cPuMu7d8g727UpQJmDaN0Qo1VgWL2UVy6fb VW4Wdez4PYLG8FNqdfZfqqFFt4HUp8Wu3u6cWqiNRutokdxbxdEdONb3Yd0pSc5RQl0w dax0dE5OGZ3hCKZJ7riBFuX3FgzCTv67or1kByLGwMFstZtf1I/s/A9YvgyL5u/2Ekms NgV0ODNa4LHingWqHBuKa3Z5l5QV6IaTQlnHvjf+iyi7EI7Kp9B+C7fQuzQ1x3dlCqQ3 j0RvRKLOPb7QGGDdWKK9OfauacjJMb2Uc6Pkh7Jxa10tsQtexIfYZMKPJsTu3a6DNz7C 08XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=K1voChlz8vWgeFf1uPl+d638S/hhQnZSLnL38yK92NY=; b=ocTJjWk9wsIK9pSqEF47LqYQ/FbIslfvz55xZC0ePtH0gRvIVdHqNukxlnbDJQMVRr M73f+v6KlMdcOJOxeIXyVDrLY0iPV9XKG4fwKY1cHPfNNTmOJ/s0CL0AmSUq2XnhsF0f BGVKsPC1U2PfoVVMfCsuBcK59R1lQKaEBt+EWQr4fRGaTW9bBlZDf+Fkp8b2ei37BVh9 dRApzE9ICBrNTTo+QMzIWa6gv6Su6ezvxykQlCoxNgEdIYYZTBnkeBUA3O1eTgMeKLW0 M+wgYnwlFOuHVXlf7/yebSQNtcTz04OGhrElINeFoer0o/GDqcS5wtTZ3DPKwCSq2rR0 hj0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JFqFd5yh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b79si12353188yba.44.2020.07.03.10.06.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:06:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JFqFd5yh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP8k-0007Hl-EN for patch@linaro.org; Fri, 03 Jul 2020 13:06:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxI-000510-Ae for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:28 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36000) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxG-0005gu-JR for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:27 -0400 Received: by mail-wm1-x343.google.com with SMTP id 17so34698628wmo.1 for ; Fri, 03 Jul 2020 09:54:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K1voChlz8vWgeFf1uPl+d638S/hhQnZSLnL38yK92NY=; b=JFqFd5yhxwIvKdtUhTpkpcwGeRvxuV96DqWI4jadZkqixABHBhb9fKZ82q7Lx7WX49 5nOG27gnbUWGC2XauG9gXsB+zyL2Y1Qtbvkwbf8NENudkNjpI5tyL8V5ZUvAZ1FPAvAI gVoMjwEEr2pHewKAhm/2feDhFNdQYGgITiJmbrAB/5eqYpp/kVbquJ8PsccISRlLUAHO BT9LDzC0X46Ly1NQZTBqOjpWvNvFFXI15uHMN3Vw5z0esLVieYQlA6BFF5VRJJaaDTUb cGLZLpPoPm0lWrm++xjpgBXkaSrK3BKHPsKTDzd71u/fCN5lwOYJgw8Xu1DjZBtPnrx7 2bsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K1voChlz8vWgeFf1uPl+d638S/hhQnZSLnL38yK92NY=; b=kXK7cz/b4rUEB3krrugX8aM7J1gUkypZVFYmcH1TNOu1uulY4u6efvM7op1AHsR75V QyqFzBYJ+W0AR9fv/nXGiNqTaFUeqfcraNob3rNtvQywS8TAD1OXZ3W6IClLBx++UWnl 9usG3T59EZL99GEks3AoRKqewGT1YZc2PGF9i0ebx5Ss19ppGgncv+CtPZRsIP7JjNCQ RVAjMVifdSyN1AF1wu91vrXsh0qxZnYhcUyC/sETR0omstBSLBAZZWLycPhAaTsbczUb YYE3bwJFEgjmMF9YHZVqJwE/LCFkCPqkzxdJJyiAWRBReqrn1US6cYdQ896o1QJrKC4F qm3A== X-Gm-Message-State: AOAM532kJsaDQw04u86uxXKiwuNHU99waKuzrauWb/SFheBTkadC2eN8 OABNVSl35lvctRBkifQZ7Filp5y/owC4Tw== X-Received: by 2002:a05:600c:2f17:: with SMTP id r23mr35719247wmn.167.1593795264910; Fri, 03 Jul 2020 09:54:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/34] hw/display/bcm2835_fb.c: Initialize all fields of struct Date: Fri, 3 Jul 2020 17:53:47 +0100 Message-Id: <20200703165405.17672-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we pass a pointer to a local struct to another function without initializing all its fields. This is a real bug: bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig struct into s->config, so any fields we don't initialize will corrupt the state of the device. Copy the two fields which we don't want to update (pixo and alpha) from the existing config so we don't accidentally change them. Fixes: cfb7ba983857e40e88 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200628195436.27582-1-peter.maydell@linaro.org --- hw/display/bcm2835_fb.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.20.1 diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c index c6263808a27..7c0e5eef2d5 100644 --- a/hw/display/bcm2835_fb.c +++ b/hw/display/bcm2835_fb.c @@ -282,6 +282,10 @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value) newconf.base = s->vcram_base | (value & 0xc0000000); newconf.base += BCM2835_FB_OFFSET; + /* Copy fields which we don't want to change from the existing config */ + newconf.pixo = s->config.pixo; + newconf.alpha = s->config.alpha; + bcm2835_fb_validate_config(&newconf); pitch = bcm2835_fb_get_pitch(&newconf); From patchwork Fri Jul 3 16:53:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231249 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2570144ilg; Fri, 3 Jul 2020 10:08:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgTTS0nA38Ih18oob1udLyoT/NqcnwkZl7uactWxBEUme9rSt3vw8yfRDPxHXaI9fD47h1 X-Received: by 2002:a25:c00b:: with SMTP id c11mr44579077ybf.430.1593796100068; Fri, 03 Jul 2020 10:08:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796100; cv=none; d=google.com; s=arc-20160816; b=AQMhlmnPGq5giJj0jKNXINMS7TMAMEbDOxB6XS3TXXMliT86e9SGr3R3qUg7uk8NLX aZwgs/W4FDOom2JGkcr2qbCo87jcTy9re9MO7kd9narAfNTD2YksqhmnC0rH2C0vzoJe KYdXIiZ76mWbUHYbbdTo/OeNeiD1Fc2yH1W5mzS+2vn/SQkzD0+pBYdu9wrw1k5yFc2k h8vqrSCSlRHfwFuMIkRqxis91Clgj8ZnD9wnEd+HDuDmczjEZUlGWUELhSQNpTMHr36t wF8ajzijQ/gAoWnSMKj+bzXVQ79LPllW6Zg3os3RmeAZv4Y2kA5jQ/lfP2TE3KZ0g7Pa MQtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kzUM2VqizH8esaQXOC5IzGhh1jcxpGV+zhaMyuOh1A4=; b=Nslrl/tFExlBTNcIKm2MYu5VhNIqLD3MoBKkXOk8sPaCnuYwseKqyNdkP+QIBiiNN1 wm7gj9j9/JFpc5V0ftwOy9jGmqtX7YjcXd/bPJoGG0uUlh36STiVCRsRHkboqb7Mu1Di 2Lotbwz3PIy/4YYv93Lo4ZkPXCdNK/ujKNHUEXipmmtEfDo9FsdT+KWd4zeLIECT7aXR sUOLjtFcWg2F62x5AMa2NPjAl43wNR5IbDMCHwQe9X/ZfR/PdWVjfFSuC7+ctAJhxIRe F/4O5CXcUEBmyyLV6AMefk9xGUz+g9jf1BlIe6/MZAyz4CQ5YFEdCd9sLRk9i6wU5eMk b+tA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gcbwqikr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h2si12926487ybj.207.2020.07.03.10.08.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:08:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gcbwqikr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPAh-0002Jk-DY for patch@linaro.org; Fri, 03 Jul 2020 13:08:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxK-00055r-E7 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:30 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:38709) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxI-0005hD-4l for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:30 -0400 Received: by mail-wm1-x330.google.com with SMTP id f18so34754892wml.3 for ; Fri, 03 Jul 2020 09:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kzUM2VqizH8esaQXOC5IzGhh1jcxpGV+zhaMyuOh1A4=; b=Gcbwqikrja3epDbqpV+9oyEjl1lpXcMwfKgNAsE8MF78I6vZMdTDP+jVSwpeySoFtQ xLp3jwezI4wyw0QxUqc5aQTBQkbvIQG95gvqzFQxBYjYldMX59Y36ZIIgJ2KKc4QbM/3 zomXN7VKD9aNBqa7FrJ7elf4a/Dv5plly61Rn/TjOGBLMar6sGADPklwNPLqTPsO1ocK r4F4sbtF7VHPWZ8DZ25cctcKMffrmqubcC96z7q0+Td295D3RWBSA6OLjsUEdtZwRWAc 8vTtOvWiAit88yhRJDeWVj0TZH7mXfnNA2jcz9mZIVApSs/NPFyx8l6kSBWb340b6E8g 64Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kzUM2VqizH8esaQXOC5IzGhh1jcxpGV+zhaMyuOh1A4=; b=WifJxp9vib/y6pn4V0qNaQbs/UhIOOsoFOoDR7o/9xJ8vpDI+kpbMwlSp+8ELdqYdM tAtOKNq4ywonUjRN1itlJ7lM5LOl7NvCtsobqyXeWX6BDBDyqz14ezKo+i6HJ8G6yRUL ynSaQhkutVqee6++on7qUz0T7TZOpgY3tc7gNlo91erhzkHaGGhizqJxYVLl4gtIVMuc JyAQjDdi12rIb96Kur4WR7tGNO7JAwORXWprcH1e4bRDCAF5RuFuFwaE/zaKAwR60CaU XzNsT8N24eZrH8EcbLijIQff8yc1aNP+1awKyC2/FdZVliJc9OHS1ElwbDIL7wHK8qC+ WrJw== X-Gm-Message-State: AOAM533q6qj6vtuw7bKzmkcCjE4L3fgzaReBSd8R/+69z/COx6xFvPq1 W9MJY6gwjid207tJS6rDXb2ClAv9pxXFGA== X-Received: by 2002:a1c:cc07:: with SMTP id h7mr37383820wmb.179.1593795266202; Fri, 03 Jul 2020 09:54:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/34] hw/arm/spitz: Detabify Date: Fri, 3 Jul 2020 17:53:48 +0100 Message-Id: <20200703165405.17672-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The spitz board has been around a long time, and still has a fair number of hard-coded tab characters in it. We're about to do some work on this source file, so start out by expanding out the tabs. This commit is a pure whitespace only change. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-2-peter.maydell@linaro.org --- hw/arm/spitz.c | 156 ++++++++++++++++++++++++------------------------- 1 file changed, 78 insertions(+), 78 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index fc18212e686..9eaedab79b5 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -34,25 +34,25 @@ #include "cpu.h" #undef REG_FMT -#define REG_FMT "0x%02lx" +#define REG_FMT "0x%02lx" /* Spitz Flash */ -#define FLASH_BASE 0x0c000000 -#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ -#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ -#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ -#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ -#define FLASH_ECCCLRR 0x10 /* Clear ECC */ -#define FLASH_FLASHIO 0x14 /* Flash I/O */ -#define FLASH_FLASHCTL 0x18 /* Flash Control */ +#define FLASH_BASE 0x0c000000 +#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ +#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ +#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ +#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ +#define FLASH_ECCCLRR 0x10 /* Clear ECC */ +#define FLASH_FLASHIO 0x14 /* Flash I/O */ +#define FLASH_FLASHCTL 0x18 /* Flash Control */ -#define FLASHCTL_CE0 (1 << 0) -#define FLASHCTL_CLE (1 << 1) -#define FLASHCTL_ALE (1 << 2) -#define FLASHCTL_WP (1 << 3) -#define FLASHCTL_CE1 (1 << 4) -#define FLASHCTL_RYBY (1 << 5) -#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) +#define FLASHCTL_CE0 (1 << 0) +#define FLASHCTL_CLE (1 << 1) +#define FLASHCTL_ALE (1 << 2) +#define FLASHCTL_WP (1 << 3) +#define FLASHCTL_CE1 (1 << 4) +#define FLASHCTL_RYBY (1 << 5) +#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) #define TYPE_SL_NAND "sl-nand" #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND) @@ -74,12 +74,12 @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size) int ryby; switch (addr) { -#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) +#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) case FLASH_ECCLPLB: return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); -#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) +#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) case FLASH_ECCLPUB: return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); @@ -191,8 +191,8 @@ static void sl_nand_realize(DeviceState *dev, Error **errp) /* Spitz Keyboard */ -#define SPITZ_KEY_STROBE_NUM 11 -#define SPITZ_KEY_SENSE_NUM 7 +#define SPITZ_KEY_STROBE_NUM 11 +#define SPITZ_KEY_SENSE_NUM 7 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { 12, 17, 91, 34, 36, 38, 39 @@ -214,11 +214,11 @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, }; -#define SPITZ_GPIO_AK_INT 13 /* Remote control */ -#define SPITZ_GPIO_SYNC 16 /* Sync button */ -#define SPITZ_GPIO_ON_KEY 95 /* Power button */ -#define SPITZ_GPIO_SWA 97 /* Lid */ -#define SPITZ_GPIO_SWB 96 /* Tablet mode */ +#define SPITZ_GPIO_AK_INT 13 /* Remote control */ +#define SPITZ_GPIO_SYNC 16 /* Sync button */ +#define SPITZ_GPIO_ON_KEY 95 /* Power button */ +#define SPITZ_GPIO_SWA 97 /* Lid */ +#define SPITZ_GPIO_SWB 96 /* Tablet mode */ /* The special buttons are mapped to unused keys */ static const int spitz_gpiomap[5] = { @@ -300,7 +300,7 @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) #define SPITZ_MOD_CTRL (1 << 8) #define SPITZ_MOD_FN (1 << 9) -#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c +#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c static void spitz_keyboard_handler(void *opaque, int keycode) { @@ -308,25 +308,25 @@ static void spitz_keyboard_handler(void *opaque, int keycode) uint16_t code; int mapcode; switch (keycode) { - case 0x2a: /* Left Shift */ + case 0x2a: /* Left Shift */ s->modifiers |= 1; break; case 0xaa: s->modifiers &= ~1; break; - case 0x36: /* Right Shift */ + case 0x36: /* Right Shift */ s->modifiers |= 2; break; case 0xb6: s->modifiers &= ~2; break; - case 0x1d: /* Control */ + case 0x1d: /* Control */ s->modifiers |= 4; break; case 0x9d: s->modifiers &= ~4; break; - case 0x38: /* Alt */ + case 0x38: /* Alt */ s->modifiers |= 8; break; case 0xb8: @@ -536,14 +536,14 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp) /* LCD backlight controller */ -#define LCDTG_RESCTL 0x00 -#define LCDTG_PHACTRL 0x01 -#define LCDTG_DUTYCTRL 0x02 -#define LCDTG_POWERREG0 0x03 -#define LCDTG_POWERREG1 0x04 -#define LCDTG_GPOR3 0x05 -#define LCDTG_PICTRL 0x06 -#define LCDTG_POLCTRL 0x07 +#define LCDTG_RESCTL 0x00 +#define LCDTG_PHACTRL 0x01 +#define LCDTG_DUTYCTRL 0x02 +#define LCDTG_POWERREG0 0x03 +#define LCDTG_POWERREG1 0x04 +#define LCDTG_GPOR3 0x05 +#define LCDTG_PICTRL 0x06 +#define LCDTG_POLCTRL 0x07 typedef struct { SSISlave ssidev; @@ -623,12 +623,12 @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp) /* SSP devices */ -#define CORGI_SSP_PORT 2 +#define CORGI_SSP_PORT 2 -#define SPITZ_GPIO_LCDCON_CS 53 -#define SPITZ_GPIO_ADS7846_CS 14 -#define SPITZ_GPIO_MAX1111_CS 20 -#define SPITZ_GPIO_TP_INT 11 +#define SPITZ_GPIO_LCDCON_CS 53 +#define SPITZ_GPIO_ADS7846_CS 14 +#define SPITZ_GPIO_MAX1111_CS 20 +#define SPITZ_GPIO_TP_INT 11 static DeviceState *max1111; @@ -659,13 +659,13 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) s->enable[line] = !level; } -#define MAX1111_BATT_VOLT 1 -#define MAX1111_BATT_TEMP 2 -#define MAX1111_ACIN_VOLT 3 +#define MAX1111_BATT_VOLT 1 +#define MAX1111_BATT_TEMP 2 +#define MAX1111_ACIN_VOLT 3 -#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ -#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ -#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ +#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ +#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ +#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ static void spitz_adc_temp_on(void *opaque, int line, int level) { @@ -735,11 +735,11 @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) /* Wm8750 and Max7310 on I2C */ -#define AKITA_MAX_ADDR 0x18 -#define SPITZ_WM_ADDRL 0x1b -#define SPITZ_WM_ADDRH 0x1a +#define AKITA_MAX_ADDR 0x18 +#define SPITZ_WM_ADDRL 0x1b +#define SPITZ_WM_ADDRH 0x1a -#define SPITZ_GPIO_WM 5 +#define SPITZ_GPIO_WM 5 static void spitz_wm8750_addr(void *opaque, int line, int level) { @@ -806,20 +806,20 @@ static void spitz_out_switch(void *opaque, int line, int level) } } -#define SPITZ_SCP_LED_GREEN 1 -#define SPITZ_SCP_JK_B 2 -#define SPITZ_SCP_CHRG_ON 3 -#define SPITZ_SCP_MUTE_L 4 -#define SPITZ_SCP_MUTE_R 5 -#define SPITZ_SCP_CF_POWER 6 -#define SPITZ_SCP_LED_ORANGE 7 -#define SPITZ_SCP_JK_A 8 -#define SPITZ_SCP_ADC_TEMP_ON 9 -#define SPITZ_SCP2_IR_ON 1 -#define SPITZ_SCP2_AKIN_PULLUP 2 -#define SPITZ_SCP2_BACKLIGHT_CONT 7 -#define SPITZ_SCP2_BACKLIGHT_ON 8 -#define SPITZ_SCP2_MIC_BIAS 9 +#define SPITZ_SCP_LED_GREEN 1 +#define SPITZ_SCP_JK_B 2 +#define SPITZ_SCP_CHRG_ON 3 +#define SPITZ_SCP_MUTE_L 4 +#define SPITZ_SCP_MUTE_R 5 +#define SPITZ_SCP_CF_POWER 6 +#define SPITZ_SCP_LED_ORANGE 7 +#define SPITZ_SCP_JK_A 8 +#define SPITZ_SCP_ADC_TEMP_ON 9 +#define SPITZ_SCP2_IR_ON 1 +#define SPITZ_SCP2_AKIN_PULLUP 2 +#define SPITZ_SCP2_BACKLIGHT_CONT 7 +#define SPITZ_SCP2_BACKLIGHT_ON 8 +#define SPITZ_SCP2_MIC_BIAS 9 static void spitz_scoop_gpio_setup(PXA2xxState *cpu, DeviceState *scp0, DeviceState *scp1) @@ -839,15 +839,15 @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu, qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); } -#define SPITZ_GPIO_HSYNC 22 -#define SPITZ_GPIO_SD_DETECT 9 -#define SPITZ_GPIO_SD_WP 81 -#define SPITZ_GPIO_ON_RESET 89 -#define SPITZ_GPIO_BAT_COVER 90 -#define SPITZ_GPIO_CF1_IRQ 105 -#define SPITZ_GPIO_CF1_CD 94 -#define SPITZ_GPIO_CF2_IRQ 106 -#define SPITZ_GPIO_CF2_CD 93 +#define SPITZ_GPIO_HSYNC 22 +#define SPITZ_GPIO_SD_DETECT 9 +#define SPITZ_GPIO_SD_WP 81 +#define SPITZ_GPIO_ON_RESET 89 +#define SPITZ_GPIO_BAT_COVER 90 +#define SPITZ_GPIO_CF1_IRQ 105 +#define SPITZ_GPIO_CF1_CD 94 +#define SPITZ_GPIO_CF2_IRQ 106 +#define SPITZ_GPIO_CF2_CD 93 static int spitz_hsync; @@ -907,8 +907,8 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) /* Board init. */ enum spitz_model_e { spitz, akita, borzoi, terrier }; -#define SPITZ_RAM 0x04000000 -#define SPITZ_ROM 0x00800000 +#define SPITZ_RAM 0x04000000 +#define SPITZ_ROM 0x00800000 static struct arm_boot_info spitz_binfo = { .loader_start = PXA2XX_SDRAM_BASE, From patchwork Fri Jul 3 16:53:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231252 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2572106ilg; Fri, 3 Jul 2020 10:10:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz9MJswfzDSRPmEUI9+nR+90ehtT2AGzdBIK9UqoWkoAjw3V4HUYF6JdNitPKOsbd61awOK X-Received: by 2002:a25:7b82:: with SMTP id w124mr64257465ybc.349.1593796244051; Fri, 03 Jul 2020 10:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796244; cv=none; d=google.com; s=arc-20160816; b=kMCwhzOB/Ha+cyUNS8BlGD1APxRMmRSEMfDSvxBXmYhMpDUrTgrh7sh2v2TXilG5zw vzFxxuOvH32yx/Hs1HbI5Vb3S3yw0iWz5hxzfuYLDf58ePI/NwuvgL3Mj/lRatrlZGPZ vAHrQHlCUd2ji+rmnIPKFOJPolpqIOnl1ctrpmxqgqh3vgmm5m2/+noSMSneeIaBaRWC A9y61dPS650fLiv0LDaSOKVum1jA1kyznBEdNiJFaB9kgQ/HhXMeNHLUhhp4SvE9892S AhFiAct62ZwVLopUSYbntbD0ObldVCWdhz6x7VWAmTyOCuHgOmjOtMh9XWZQ4UDePL2K 8N7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FSBAmlrtWVF6FORp650+KLsFcscgV77fdb6cJMrBfcg=; b=GckzX3N92HJbCQdkqfAuW9qacMuvAbH2+KYFek9i4g69Onra0ZmMUL/bEcFKw7m2Lb 4oj5BKMto1oG1Nkg3n+cP8WTmiyiRBlzE2hOptnPlV1E8IELPeEpJB0uoSgGxpR3SyJc G4bCxsLA/qzS/Tuku/qBn51zI3gdv4SHC2VrarqTZuoGeFd2F6HNdMLt9N3vyo5HSV/V nd3nXeaPpRYKGPtEQ5Ew361Fz9szes+EwsTMxjlkTYS/DUWZE6O+QV//jhHOP0IRjydj yIO/Ra8wCThwQxwGYjQx5tXydsTlquzU8lGJg9XU+MJv8wVfnnb7B9qEPVWoYU8m1GPd h5Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CoI5TY6K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i127si14646129ybb.475.2020.07.03.10.10.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:10:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CoI5TY6K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPD1-0006LA-DA for patch@linaro.org; Fri, 03 Jul 2020 13:10:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxL-00057U-3k for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:31 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:38471) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxJ-0005hY-7p for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:30 -0400 Received: by mail-wr1-x42d.google.com with SMTP id z13so33426252wrw.5 for ; Fri, 03 Jul 2020 09:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FSBAmlrtWVF6FORp650+KLsFcscgV77fdb6cJMrBfcg=; b=CoI5TY6KRiaofGrQJIKMv/dVYY8/Q5D2fWS2JMpVuVeYe4Nx+o0dauefwNlbNP+bQj G0CNf9nN1w9G/T+PNQbkaYDuODmOVupOjhKs3BkJ0IYMAtQURhOYnU4nxvsT3yq1gZ8A L7KWrx4w7kXlYdh0qeaUtzTl6ldlQDBAOKjRvhThxVJ/s7lNLsf+R157Bxeowuy6Uq23 zVB74AJ0E7V3C8E4+R3/LhwEU7fmsNUdO4+SucNXsU5rD1Aq6RflqCe0/WAS2wBdQzgf cO/+i3WEm+R7W0XjN8b3xShNulZSiG2nNVrpRtcXSQmv//9waXM+RJk+S8pu+FwD64Px iMig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FSBAmlrtWVF6FORp650+KLsFcscgV77fdb6cJMrBfcg=; b=gmSGUOZIGTcfgI/+V0iozf8RTEvE8z5qaQK2Vn4uiwdp+tVTwoaLaAsYyBBUYQM1z4 kPkPEQS7l7yAFKX0DiuXCNDK6vf1YU395VjlTn/m9TBMllU6i8XA6YQX6uzJ+ISuU24Q ZeW5FO3i30jC7wlbD4g9TQWt8GWMqQI3BfP82vintzSQvGejBzf0mdMOn5qeppxGO5xa bEOwAzxQ5Z7kPbH1MxKL389D9bIaLw2mtrq+Y65u6N8b5OejgdoOA5Abb4OxPGcRkwkh sGRGwkJpqxpAolzUur9GQsvwY+902JeSA06/TYrtRdg13swAPxF+WMuALbJO+makVckB FlzA== X-Gm-Message-State: AOAM530kSEKzGXCZoegFl6S7MelyXQiVbtEXH6rB+bToWKBRmQH/SOMk l/m/1my7PXHMnTanRv302uXt1A9Ssr/bzQ== X-Received: by 2002:adf:9051:: with SMTP id h75mr40378471wrh.152.1593795267438; Fri, 03 Jul 2020 09:54:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/34] hw/arm/spitz: Create SpitzMachineClass abstract base class Date: Fri, 3 Jul 2020 17:53:49 +0100 Message-Id: <20200703165405.17672-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For the four Spitz-family machines (akita, borzoi, spitz, terrier) create a proper abstract class SpitzMachineClass which encapsulates the common behaviour, rather than having them all derive directly from TYPE_MACHINE: * instead of each machine class setting mc->init to a wrapper function which calls spitz_common_init() with parameters, put that data in the SpitzMachineClass and make spitz_common_init the SpitzMachineClass machine-init function * move the settings of mc->block_default_type and mc->ignore_memory_transaction_failures into the SpitzMachineClass class init rather than repeating them in each machine's class init (The motivation is that we're going to want to keep some state in the SpitzMachineState so we can connect GPIOs between devices created in one sub-function of the machine init to devices created in a different sub-function.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200628142429.17111-3-peter.maydell@linaro.org --- hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 55 insertions(+), 36 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 9eaedab79b5..c70e912a33d 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -33,6 +33,26 @@ #include "exec/address-spaces.h" #include "cpu.h" +enum spitz_model_e { spitz, akita, borzoi, terrier }; + +typedef struct { + MachineClass parent; + enum spitz_model_e model; + int arm_id; +} SpitzMachineClass; + +typedef struct { + MachineState parent; +} SpitzMachineState; + +#define TYPE_SPITZ_MACHINE "spitz-common" +#define SPITZ_MACHINE(obj) \ + OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE) +#define SPITZ_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE) +#define SPITZ_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE) + #undef REG_FMT #define REG_FMT "0x%02lx" @@ -905,8 +925,6 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) } /* Board init. */ -enum spitz_model_e { spitz, akita, borzoi, terrier }; - #define SPITZ_RAM 0x04000000 #define SPITZ_ROM 0x00800000 @@ -915,9 +933,10 @@ static struct arm_boot_info spitz_binfo = { .ram_size = 0x04000000, }; -static void spitz_common_init(MachineState *machine, - enum spitz_model_e model, int arm_id) +static void spitz_common_init(MachineState *machine) { + SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine); + enum spitz_model_e model = smc->model; PXA2xxState *mpu; DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); @@ -958,100 +977,100 @@ static void spitz_common_init(MachineState *machine, /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ spitz_microdrive_attach(mpu, 0); - spitz_binfo.board_id = arm_id; + spitz_binfo.board_id = smc->arm_id; arm_load_kernel(mpu->cpu, machine, &spitz_binfo); sl_bootparam_write(SL_PXA_PARAM_BASE); } -static void spitz_init(MachineState *machine) +static void spitz_common_class_init(ObjectClass *oc, void *data) { - spitz_common_init(machine, spitz, 0x2c9); + MachineClass *mc = MACHINE_CLASS(oc); + + mc->block_default_type = IF_IDE; + mc->ignore_memory_transaction_failures = true; + mc->init = spitz_common_init; } -static void borzoi_init(MachineState *machine) -{ - spitz_common_init(machine, borzoi, 0x33f); -} - -static void akita_init(MachineState *machine) -{ - spitz_common_init(machine, akita, 0x2e8); -} - -static void terrier_init(MachineState *machine) -{ - spitz_common_init(machine, terrier, 0x33f); -} +static const TypeInfo spitz_common_info = { + .name = TYPE_SPITZ_MACHINE, + .parent = TYPE_MACHINE, + .abstract = true, + .instance_size = sizeof(SpitzMachineState), + .class_size = sizeof(SpitzMachineClass), + .class_init = spitz_common_class_init, +}; static void akitapda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; - mc->init = akita_init; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); + smc->model = akita; + smc->arm_id = 0x2e8; } static const TypeInfo akitapda_type = { .name = MACHINE_TYPE_NAME("akita"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = akitapda_class_init, }; static void spitzpda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; - mc->init = spitz_init; - mc->block_default_type = IF_IDE; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); + smc->model = spitz; + smc->arm_id = 0x2c9; } static const TypeInfo spitzpda_type = { .name = MACHINE_TYPE_NAME("spitz"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = spitzpda_class_init, }; static void borzoipda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; - mc->init = borzoi_init; - mc->block_default_type = IF_IDE; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); + smc->model = borzoi; + smc->arm_id = 0x33f; } static const TypeInfo borzoipda_type = { .name = MACHINE_TYPE_NAME("borzoi"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = borzoipda_class_init, }; static void terrierpda_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; - mc->init = terrier_init; - mc->block_default_type = IF_IDE; - mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); + smc->model = terrier; + smc->arm_id = 0x33f; } static const TypeInfo terrierpda_type = { .name = MACHINE_TYPE_NAME("terrier"), - .parent = TYPE_MACHINE, + .parent = TYPE_SPITZ_MACHINE, .class_init = terrierpda_class_init, }; static void spitz_machine_init(void) { + type_register_static(&spitz_common_info); type_register_static(&akitapda_type); type_register_static(&spitzpda_type); type_register_static(&borzoipda_type); From patchwork Fri Jul 3 16:53:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231294 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2574122ilg; Fri, 3 Jul 2020 10:13:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwrHAXrCjfLSdpVONkvYpF/xQXKXUfAtP85C6NoWtFXRgusMsokCmag4is8M66mhjeaTZ1j X-Received: by 2002:a25:2f47:: with SMTP id v68mr53496231ybv.142.1593796411712; Fri, 03 Jul 2020 10:13:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796411; cv=none; d=google.com; s=arc-20160816; b=MexSNbyLPS7M5IJxfgU1DT/OMYS0jTlx1xKu1l0bZnv2bDrFQ6Brf6sxlJ/IT7TVH3 l+LXy+4QPoXQSmpgZwKVRYYw4GeWCHiZb54w6nhvz6VFrptuoUbdA1fpU6qLgOP+WKzX Yve5Rtt+S5pMONesD7c1lmiN4J2EoHQ7hWe4o9FQbKRwYhiu9BVNACK0/MGbTANGmEZd 1r1MfErNL1pdwhNo7OO5aEQ1DeK/+aqkoaK0W5LiiC1iuU1i/pa4Ki9V+U21FSEwAhND ChQZzioFQvnk7s55eQiwdxKG/HDy04RVVJoiXCURSY1KvMETHN+suF/yV29mcMpBIGT1 o4qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PQU0VMDoZFuJFaraom9TI5EU5C92z+9V7Vol+wly+Aw=; b=jGnXRoCIJgd5pr0rs3heAy7BsL0B2sYixjz4oIK9uGiybTRbx3fd4BHSn3ZwO1Rbfm avPI9bGx8Rpcp4/I7CjoBkbOu8MVOXzyKNAiKULRlwv+Wza9rVUz9D91ZU7NHXOCF3iS Q/aYG4HvelSRjoiIGNgJlTA9HXMRlo2mmFuIqwv3LNnf4u8EnBOiHvLqScCmuaa+qZoh u4Rhegntvm407f8wwojZfHkX6TAI3PWAd10gTf0OlfA+2WCE3NcRa4OZxuz7h6uwUhLN 7dg3eQ8ssVAeKfE1vurTnmhJrnv8coeTiS78027sYa9cCoZNs7wDQkgvLqFEdAAG5HYf Y4Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=me84YcsN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l9si741097ybq.77.2020.07.03.10.13.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:13:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=me84YcsN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPFj-0001TB-06 for patch@linaro.org; Fri, 03 Jul 2020 13:13:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxM-0005AM-FA for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:32 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:33347) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxK-0005hk-HB for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:32 -0400 Received: by mail-wr1-x42d.google.com with SMTP id f18so25360363wrs.0 for ; Fri, 03 Jul 2020 09:54:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PQU0VMDoZFuJFaraom9TI5EU5C92z+9V7Vol+wly+Aw=; b=me84YcsNO+e/d2ilC8Fuhz7444zRvDy0bwTdafc/KntclJdT/dduHZWHK7vy37jBlz 6UNSGQ/HrzPfjsb997foUgu2ofXVFWvUeITGogcp+8FMK/Ry9abFTn9LseL933GzV1Tg 83qD71RLmDr0AGB2GptAj36po0X7YItTsfFCjg+mdHXoxhk2wu8bhWE82hMW3sHrfpxm jICKtAld+2yHNZfy6gMxh43tq4cMJ5B09qpQ4zr4Ypc4CWUdBeOSHxWl+kKEEgs4Qt5E dQOl3twO7yBtYPa9wHe7dV014JRvRBl9LiVXB7qK+pr3Tulaceq1GlcUniapVKl5XSK3 Wylg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PQU0VMDoZFuJFaraom9TI5EU5C92z+9V7Vol+wly+Aw=; b=Wof+HxnIMuNfE/+X/zFpzNzU0iz4aUe4AWXbo2F5XrUY1DlY0aWQlOEw0ar/Rh7C96 tGDsvnFspeuFIKfBDX3/cHaD/rymaRtF02Osz2xKIuxboMzO3khbfQGsLj309/ANr7gt 13exNtMdKEkZvoR0WceIeTzKosNwEmlvwCDYNJnIa3bVNh9IYlEyfQYak3EISc2eb1YH 8726C6UD3hzpIN7qegL0uXmflU7ERCylbBIc2yJ3YBH+xTS6BK1JjCdEskThfITYqGv4 xY74m630mDy50L+8hfYjqLUo246foc04ql/B6c/kSXE1FnTzk0lH+CRtwb3gx5Iq09SD PsbQ== X-Gm-Message-State: AOAM533QnVNhGHa7MkkUoRay4Q+tY+6Khz40bxkLuxKzx8JPUbgQG3Lv yewvQ7zhph5LhMkknQ5LYUKftYpt7hjiNQ== X-Received: by 2002:adf:fa8b:: with SMTP id h11mr37684497wrr.391.1593795268819; Fri, 03 Jul 2020 09:54:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/34] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState Date: Fri, 3 Jul 2020 17:53:50 +0100 Message-Id: <20200703165405.17672-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Keep pointers to the MPU and the SSI devices in SpitzMachineState. We're going to want to make GPIO connections between some of the SSI devices and the SCPs, so we want to keep hold of a pointer to those; putting the MPU into the struct allows us to pass just one thing to spitz_ssp_attach() rather than two. We have to retain the setting of the global "max1111" variable for the moment as it is used in spitz_adc_temp_on(); later in this series of commits we will be able to remove it. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-4-peter.maydell@linaro.org --- hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index c70e912a33d..f48e966c047 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -43,6 +43,11 @@ typedef struct { typedef struct { MachineState parent; + PXA2xxState *mpu; + DeviceState *mux; + DeviceState *lcdtg; + DeviceState *ads7846; + DeviceState *max1111; } SpitzMachineState; #define TYPE_SPITZ_MACHINE "spitz-common" @@ -709,34 +714,33 @@ static void corgi_ssp_realize(SSISlave *d, Error **errp) s->bus[2] = ssi_create_bus(dev, "ssi2"); } -static void spitz_ssp_attach(PXA2xxState *cpu) +static void spitz_ssp_attach(SpitzMachineState *sms) { - DeviceState *mux; - DeviceState *dev; void *bus; - mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); + sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); - bus = qdev_get_child_bus(mux, "ssi0"); - ssi_create_slave(bus, "spitz-lcdtg"); + bus = qdev_get_child_bus(sms->mux, "ssi0"); + sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg"); - bus = qdev_get_child_bus(mux, "ssi1"); - dev = ssi_create_slave(bus, "ads7846"); - qdev_connect_gpio_out(dev, 0, - qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT)); + bus = qdev_get_child_bus(sms->mux, "ssi1"); + sms->ads7846 = ssi_create_slave(bus, "ads7846"); + qdev_connect_gpio_out(sms->ads7846, 0, + qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); - bus = qdev_get_child_bus(mux, "ssi2"); - max1111 = ssi_create_slave(bus, "max1111"); - max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); - max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); - max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); + bus = qdev_get_child_bus(sms->mux, "ssi2"); + sms->max1111 = ssi_create_slave(bus, "max1111"); + max1111 = sms->max1111; + max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); + max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0); + max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS, - qdev_get_gpio_in(mux, 0)); - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS, - qdev_get_gpio_in(mux, 1)); - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS, - qdev_get_gpio_in(mux, 2)); + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS, + qdev_get_gpio_in(sms->mux, 0)); + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS, + qdev_get_gpio_in(sms->mux, 1)); + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS, + qdev_get_gpio_in(sms->mux, 2)); } /* CF Microdrive */ @@ -936,6 +940,7 @@ static struct arm_boot_info spitz_binfo = { static void spitz_common_init(MachineState *machine) { SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine); + SpitzMachineState *sms = SPITZ_MACHINE(machine); enum spitz_model_e model = smc->model; PXA2xxState *mpu; DeviceState *scp0, *scp1 = NULL; @@ -945,6 +950,7 @@ static void spitz_common_init(MachineState *machine) /* Setup CPU & memory */ mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, machine->cpu_type); + sms->mpu = mpu; sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); @@ -954,7 +960,7 @@ static void spitz_common_init(MachineState *machine) /* Setup peripherals */ spitz_keyboard_register(mpu); - spitz_ssp_attach(mpu); + spitz_ssp_attach(sms); scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); if (model != akita) { From patchwork Fri Jul 3 16:53:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231296 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2575158ilg; Fri, 3 Jul 2020 10:14:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwD9rAl0i1RIZO0E39tp+fy/3r5rdwo6zGzyHJYsO56ggd1NKd6d5Q6z1S+5kJKMmZesshX X-Received: by 2002:a25:544:: with SMTP id 65mr60087860ybf.309.1593796494676; Fri, 03 Jul 2020 10:14:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796494; cv=none; d=google.com; s=arc-20160816; b=VdcmSlOejYdY/Du7xeD3Cd9ud/+tcoJKp9IzQlPWg9NO0YdUtkIwqKq/igp/NTPO3I mlJFeKqJEusBPHH+/EG8NoCRgOlpLkChVz6ia+aDaXucacS4qI1LNYP+LpLrdY1DFsvY 2UeRwqCPF12hUZ0b3qRudOMJnUb0gIi8Z4jRRXU2Ya6LlexZWzHVD+dKtjKimPYM85gV z/mdXrJLX2711zHOKhlEZCIxF1HivhveVi0YZPKtuTX6mlqf/i+X0Hnr2xXmFqx80cpk /wCMeK4U7GRwCPwTLoszUhjTy3jJVaXX7YA2wHtmMZicosEK2XDurw4r6tUMEifzgc6u CdSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iwlYqQU7+O2GzS7GEPMQGSoYyptCVeRYnaJi/QEQwvA=; b=eT6hxDhp+n+chJwvafCXvF1CPEeAe5CiG+d0ZwwXeecfGN3wti6PZeAvUdnmvarsDQ OJHuq6Ov75UcmGmLb9OdlpjKdFvW9NAFe96nf48lJWBLIJr3T7jUCmcvfFpIdQPN8PpG 0mNWJOQCFXdRfb+imRg93Gzafm750nkP2BO0UmVvWAcMHGy1iOwPkyyhVLkwQM3Ivdfs n12wakdUZY8WbfWnecXc9h/McL+D7ZGgUjSTvUyNKniG/b6Nsk+upZgtWQR8HdSi+qhy zMRjphE+vibNs3lowlUIRqGe0W5drMyc6OcnRqp/3R/UhWB41fD4hkpRFEkBS2wXt8r2 D2LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UyheaOu2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u12si12169994ybc.311.2020.07.03.10.14.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:14:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UyheaOu2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPH4-0005MN-3l for patch@linaro.org; Fri, 03 Jul 2020 13:14:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxN-0005C4-K3 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:33 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:52976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxL-0005hs-P2 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:33 -0400 Received: by mail-wm1-x342.google.com with SMTP id q15so32632012wmj.2 for ; Fri, 03 Jul 2020 09:54:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iwlYqQU7+O2GzS7GEPMQGSoYyptCVeRYnaJi/QEQwvA=; b=UyheaOu2VW5fWM1ujPiYm3BL9/aNbs9/aGy5CsSdzkxnKPRe7VAcm01jY9/L7fV9B5 5+8cAqp5ntoakgpGz50MNPz8d4zpTGgR2SsfiDIQ1pibE+pFzhJtIOQqJ7adkfY3KTX1 RgQNnXojK7Q5qIAQH5pHw+Rk2vE5WXImfE90hLwlRw47mJMFtkMNamTTUUm9jvO0Dovn h3KgdoDqJrxWYOWDT7426vtlXYLujTFQMeRlutVTbMuh30bSbVd+lDDowh2RYD2SLylK OIf5OZRLHJKj0M2aKdai6CeDyrPfAdQo6HPhFZjgHcbqjdsWVrfp7rLLBkNdAEOv49Um ZLqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iwlYqQU7+O2GzS7GEPMQGSoYyptCVeRYnaJi/QEQwvA=; b=XN/W2E7KfnS+izNo7w/NFtdAvlSOd4NdI3mFrgnVilo743jMycinqlUn/fskTamiuu FrFBn6ANVSAhveEh63Cural94/ydswblQIhaUlUqx38kbJyTqQf7EempBi9RhmjNOT29 t+bV+hSjguD5KE3GBHfSwOnWhqEZSF1SdQwvaRwgjnrDgHnmn4n6ELITJs7kk11UveLH RcA/wh4v0dPKYC/1rl2Rairm4p2EwHJE+HYMCpj7+yyvHnyC3RgKzde0rdx1jUX6rlXI +dgAW9O/p9njd7MBjGZi4WHh2kiB6MRVoQU9bfAm2w9cKgSdbiI07RQ+YyXfZFT5fZ4A XQFQ== X-Gm-Message-State: AOAM531CYGeaB3n+X9muKXURX2sQg6J8davEfNAPexUPCeh0YQ4jRQ4X JkYDS2oOVBJ1kNjwnWJAxLLcmUa+TYw2RQ== X-Received: by 2002:a7b:c38f:: with SMTP id s15mr6375072wmj.152.1593795270034; Fri, 03 Jul 2020 09:54:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/34] hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState Date: Fri, 3 Jul 2020 17:53:51 +0100 Message-Id: <20200703165405.17672-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Keep pointers to scp0, scp1 in SpitzMachineState, and just pass that to spitz_scoop_gpio_setup(). (We'll want to use some of the other fields in SpitzMachineState in that function in the next commit.) Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-5-peter.maydell@linaro.org --- hw/arm/spitz.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index f48e966c047..69bc2b3fa10 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -48,6 +48,8 @@ typedef struct { DeviceState *lcdtg; DeviceState *ads7846; DeviceState *max1111; + DeviceState *scp0; + DeviceState *scp1; } SpitzMachineState; #define TYPE_SPITZ_MACHINE "spitz-common" @@ -845,22 +847,23 @@ static void spitz_out_switch(void *opaque, int line, int level) #define SPITZ_SCP2_BACKLIGHT_ON 8 #define SPITZ_SCP2_MIC_BIAS 9 -static void spitz_scoop_gpio_setup(PXA2xxState *cpu, - DeviceState *scp0, DeviceState *scp1) +static void spitz_scoop_gpio_setup(SpitzMachineState *sms) { - qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); + qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8); - qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); - qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]); - qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); - qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); - if (scp1) { - qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); - qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); + if (sms->scp1) { + qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, + outsignals[4]); + qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, + outsignals[5]); } - qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); } #define SPITZ_GPIO_HSYNC 22 @@ -943,7 +946,6 @@ static void spitz_common_init(MachineState *machine) SpitzMachineState *sms = SPITZ_MACHINE(machine); enum spitz_model_e model = smc->model; PXA2xxState *mpu; - DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *rom = g_new(MemoryRegion, 1); @@ -962,12 +964,14 @@ static void spitz_common_init(MachineState *machine) spitz_ssp_attach(sms); - scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); + sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); if (model != akita) { - scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); + sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); + } else { + sms->scp1 = NULL; } - spitz_scoop_gpio_setup(mpu, scp0, scp1); + spitz_scoop_gpio_setup(sms); spitz_gpio_setup(mpu, (model == akita) ? 1 : 2); From patchwork Fri Jul 3 16:53:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231238 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2564533ilg; Fri, 3 Jul 2020 10:01:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBuDrp8yn+gE57lbbCcYRTLkNdRCF6pDXTq21uBDyKBN/ok9Ytgrey25SzAgg3R5ztpc5j X-Received: by 2002:a25:ad56:: with SMTP id l22mr59128602ybe.383.1593795716136; Fri, 03 Jul 2020 10:01:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795716; cv=none; d=google.com; s=arc-20160816; b=hPVF9JMERVPvg7+AYf5s78Vibli4W0XNgf8eQ6UGwGZE3bX3cO3svEVBXf0y6bQ/Qx BOVog5YHWDaBXDU68gSM6Mj2Ae35zZ9ahdm55xiauWXGWikL8cGHEqL0YBZJGBM7AERj 1SuthBertW+0bUG37SB/i9CwpTr6T3+Z1u3wis0IdXiop4Y2M0SFHCpI5cuUFs5T7tHE XGKhWHRpG7q2smF+QluYt/QBaV8h/vB0aGwTo852inLpiz/j9gcTXyahuojExW89GyMQ 2U7Jo5ABhDB/ZtddPY8sxX6jZ/GB2ONu0A9/EFytHtOx1pYU9k1XvkLQGKNuo7PgEMNN +snw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Hph4sRVrrHIXw5YxnyUupaHI04MuhyQF4bKu2vDwcK0=; b=dan+rR73qjwVPAdS3sYWC1hdAToLk+QquWfBK5UWnmwp4cI6eK0YtIr4aWypBE9H3j Gvox41XFJDkzbIHKE93WzMosp23+/2al3yVSQOszYbUlnaVH0MPe14+2TbWI30j3JoLg j3dAPuJcErrlj56p5xubOgsGQmij81YCiC5Fo5Iy8KV1DhOOoM8L1VeBdvpL32K+/VEq PmFEiVvRHc4sMmw0ah5ENIldUxUlmhECyB2W5Y1BJfDJItij9SUmJqOioq+3bTYyCg7B ByMWT+XzJpX4Zi/W/V2J/kys/8QDXDEHOxLXWHUmnVLz/F+l6TDpajSMWaykNjfzI7Bf Qw6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oL99wT3W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f128si11772385ybf.34.2020.07.03.10.01.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:01:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oL99wT3W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP4V-0000dU-Jz for patch@linaro.org; Fri, 03 Jul 2020 13:01:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxO-0005FD-SO for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:34 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45168) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxN-0005i6-0V for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:34 -0400 Received: by mail-wr1-x442.google.com with SMTP id s10so33383728wrw.12 for ; Fri, 03 Jul 2020 09:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Hph4sRVrrHIXw5YxnyUupaHI04MuhyQF4bKu2vDwcK0=; b=oL99wT3WaeQJXGPpANoeqAxdlnpLZCgpqgQll6LBDd+mBvqm15hVr+ulPsSd5Psy63 U4JaazB/sN6S+Rrk72UWBiCz7iTJdrWGOuKPhK7Bv240y8+haQr1RE+DskApFsIOguVj YHMGDYqzXkOy+LnNFmIdwF4VRHgvKMO2a7OoVO8QJ2rDPACAitToqtmukuMSuuNgoiYR PMNtEal0cD3EyEzDg3DAHi57GPjXMHyGzli0Y+7ib56u53m4pgCYcbLKi2jl3OtQ7IrN 6Feh5uARG1gh2q25rNLp1xZjgT9dIpWeNAuuVm8qjmJWh8KS+lSXlxpzzO1Y2WdEGxfm nfWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hph4sRVrrHIXw5YxnyUupaHI04MuhyQF4bKu2vDwcK0=; b=OO7U4EKwsLlmOFu57rMxkMNaXpvT8pKFjBB9taYNqP0v1n9lA+Mz8rD0yb+Sslk+2U lzczPfFXBc8A+MFM8VPJKZ7TarZeUTMyA2KzMbUjL9DrJuHyfmS0/S1/VuWupd7iZOJI jzxrTTMbyjC9FxBRyW8yzEogrsED03VyF/O1hOvamKWjEtVC6blXgsT/7b+pPwcXMH9K DbMj5tSRsdJUO2iAjNyYpooKEBIhtc4QpDKw26b/UUscJNOZ8L+WhsUhIRxAqEnZAR4z dC6usn9hqIag/5jEK1HShfyFSsFvv1KfCRil4vsei6V3qkr741oIUlYwHY4XVG59Tlys 4KNg== X-Gm-Message-State: AOAM533Qse2fncZM9G+YuzsLuTQH2HiO9GV+myocT+XHhtBNrHdODAhb nEQct2yqDaoweHfKfx7oj62AEp3AdTg0ZA== X-Received: by 2002:a5d:6803:: with SMTP id w3mr37168766wru.200.1593795271227; Fri, 03 Jul 2020 09:54:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/34] hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals Date: Fri, 3 Jul 2020 17:53:52 +0100 Message-Id: <20200703165405.17672-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the Spitz board uses a nasty hack for the GPIO lines that pass "bit5" and "power" information to the LCD controller: the lcdtg realize function sets a global variable to point to the instance it just realized, and then the functions spitz_bl_power() and spitz_bl_bit5() use that to find the device they are changing the internal state of. There is a comment reading: FIXME: Implement GPIO properly and remove this hack. which was added in 2009. Implement GPIO properly and remove this hack. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-6-peter.maydell@linaro.org --- hw/arm/spitz.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 69bc2b3fa10..11e413723f4 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -586,12 +586,9 @@ static void spitz_bl_update(SpitzLCDTG *s) zaurus_printf("LCD Backlight now off\n"); } -/* FIXME: Implement GPIO properly and remove this hack. */ -static SpitzLCDTG *spitz_lcdtg; - static inline void spitz_bl_bit5(void *opaque, int line, int level) { - SpitzLCDTG *s = spitz_lcdtg; + SpitzLCDTG *s = opaque; int prev = s->bl_intensity; if (level) @@ -605,7 +602,7 @@ static inline void spitz_bl_bit5(void *opaque, int line, int level) static inline void spitz_bl_power(void *opaque, int line, int level) { - SpitzLCDTG *s = spitz_lcdtg; + SpitzLCDTG *s = opaque; s->bl_power = !!level; spitz_bl_update(s); } @@ -639,13 +636,16 @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) return 0; } -static void spitz_lcdtg_realize(SSISlave *dev, Error **errp) +static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) { - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); + SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi); + DeviceState *dev = DEVICE(s); - spitz_lcdtg = s; s->bl_power = 0; s->bl_intensity = 0x20; + + qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1); + qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1); } /* SSP devices */ @@ -820,15 +820,11 @@ static void spitz_out_switch(void *opaque, int line, int level) case 3: zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); break; - case 4: - spitz_bl_bit5(opaque, line, level); - break; - case 5: - spitz_bl_power(opaque, line, level); - break; case 6: spitz_adc_temp_on(opaque, line, level); break; + default: + g_assert_not_reached(); } } @@ -858,9 +854,9 @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms) if (sms->scp1) { qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, - outsignals[4]); + qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0)); qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, - outsignals[5]); + qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0)); } qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); From patchwork Fri Jul 3 16:53:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231244 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2568471ilg; Fri, 3 Jul 2020 10:06:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMTbWCFqYltYjFuMFNl/eJd/ZzK8DeXFgW+0kSotpoW4+UyzFK/wXXRndd+kl8WdPxkCyx X-Received: by 2002:a5b:809:: with SMTP id x9mr53903988ybp.503.1593795978345; Fri, 03 Jul 2020 10:06:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795978; cv=none; d=google.com; s=arc-20160816; b=UGul8SHF8clC1CrKNK8E71ubTQmU3dPgvqx31wfnMIO5JXKkTUYQXl01/u9An8iHvZ CswQHJWmkgGj+dINrNWDzLkHxT5R+WBIqW5xU1nGKq1nWlSsJIjMLpoxmX4znyRpRTVk zphI2QCF2WiWV7waG1dlHHUT2dLdiUlwAVuskfIJvfaCwEKED6ufhlkOLjoBQewS0LzP /8ZSXRNIl/zoZ6EUUY+FEiDeQUe4ooBF8rKgJi0Efz0aGTSfKaCFsSrJCYLvfUmweU9Y yDzGxd5W9jnlSAC7pbCrQLAB/AkAKAYuUPiWChXyv665tSadF061s0H+QiaP+OVzYrXq ksMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZVAij/KCpWXCOhgRXrDw7xB6C1uHCslS7BtBDspLBtw=; b=F/fbNYAjl0wpaaNtYkiylqvaFLEWa+wjmqCJgcimPmhGOH+isAQ9eDbPoNr6LHyLsa 9g0IZXIyGbn++8ingRXyKMeh6XxnUGLcia6SeHAimtscR4VkjI5hTX5ru319kKdEgVLj SvQWOTtLqsf16CvM/CHXiQqwRp+HZsOfNtNskITn/pgBuxBGNdvg4Mxf6gMA/kIDbXTO zSe/i//LXLiY6pfOLmNy/YSKNuHsgHbORGDevoDcPxuMoCKyU7HRs23vlae5KdN5ur/S u1Qe+MgMRsYQnI/b5r6Gw7s+OMjAT4w3pd0Nnt5d6Sd8UJYxktMRAio8Z8+v/Xg3RuFB /2Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xh8MW3xB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 23si11707904ybf.120.2020.07.03.10.06.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:06:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xh8MW3xB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP8j-0007Gg-Nx for patch@linaro.org; Fri, 03 Jul 2020 13:06:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxQ-0005I9-1w for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:36 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:35620) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxO-0005iJ-68 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:35 -0400 Received: by mail-wm1-x335.google.com with SMTP id l2so33241445wmf.0 for ; Fri, 03 Jul 2020 09:54:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZVAij/KCpWXCOhgRXrDw7xB6C1uHCslS7BtBDspLBtw=; b=Xh8MW3xB9bUBnI1gzX3cmnQ7sa+uRTGG5OpR43q86k4qx0dbCVhdSlVyGow/qTqQCb WGlwQ1IkRAvSzOKvMgEhesTo7LHulDlZ4zo09if4Olqx2j3lKAvFlBFthBb4XN1nYOQ/ fy4Dq/WU2sF9df5w3ooqN1bWRgv87sYezkSVSO/uHjIjRyNIpELHdum+uDD/tqDJTSyi trD2q8y/Z7IwTJxDq+57UWXOBNIJOqlgMhJECbkI21WUwmQIreed/3Edvnf61tGVx/0W 0nnIy/+4UjYn/5YUDvv4c43pmDeO6MbWx6G1UJaSwcFbCIJpXRClGLukcZHSr7B3Y6w5 bT7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZVAij/KCpWXCOhgRXrDw7xB6C1uHCslS7BtBDspLBtw=; b=SHftWq3S25HPNt22Hd/2uFzx+RYUcA2I4ZcQKjZG0MKkBFiQI1E5QTCn/8UZ9iKAvi 3qVNBlRMZ5kSImYUUf/LL4KCti597Ayq97GcQ5K0AGFXE5teZcPL4L4G+T5fmNPxZ2MB Hc22d6QZyoMLsHYVzjmYnhsC+Y6xK9ijVKncIK1+Yx9zoMWbdT3p2efnaj6R/UBEMW1I ZP7u99AqU181wKFPLRtf8X5+ggcoypkUtZ5ew0ttpnBwrkFvnn8r/czLtzx+p/cnl7EV uJDMD4bTYm9NvUdBNIH7ekxChpygLU1OnnuVAOmbBAlAPVkSNsu9P0RK/+7bUxRoy5iG G++g== X-Gm-Message-State: AOAM530KAKPTjewCDYGHMo1yUZE2gsWP9Q41yyIF2Pjgpjiny+IZqkB9 uiE3cy9yTTo1seVjwLbisyvPKnUA2RR3ng== X-Received: by 2002:a1c:3dc3:: with SMTP id k186mr39360530wma.66.1593795272401; Fri, 03 Jul 2020 09:54:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/34] hw/misc/max111x: provide QOM properties for setting initial values Date: Fri, 3 Jul 2020 17:53:53 +0100 Message-Id: <20200703165405.17672-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add some QOM properties to the max111x ADC device to allow the initial values to be configured. Currently this is done by board code calling max111x_set_input() after it creates the device, which doesn't work on system reset. This requires us to implement a reset method for this device, so while we're doing that make sure we reset the other parts of the device state. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-7-peter.maydell@linaro.org --- hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 10 deletions(-) -- 2.20.1 diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index 2b87bdee5b7..d0e5534e4f5 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -15,11 +15,15 @@ #include "hw/ssi/ssi.h" #include "migration/vmstate.h" #include "qemu/module.h" +#include "hw/qdev-properties.h" typedef struct { SSISlave parent_obj; qemu_irq interrupt; + /* Values of inputs at system reset (settable by QOM property) */ + uint8_t reset_input[8]; + uint8_t tb1, rb2, rb3; int cycle; @@ -135,16 +139,6 @@ static int max111x_init(SSISlave *d, int inputs) qdev_init_gpio_out(dev, &s->interrupt, 1); s->inputs = inputs; - /* TODO: add a user interface for setting these */ - s->input[0] = 0xf0; - s->input[1] = 0xe0; - s->input[2] = 0xd0; - s->input[3] = 0xc0; - s->input[4] = 0xb0; - s->input[5] = 0xa0; - s->input[6] = 0x90; - s->input[7] = 0x80; - s->com = 0; vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY, &vmstate_max111x, s); @@ -168,11 +162,50 @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value) s->input[line] = value; } +static void max111x_reset(DeviceState *dev) +{ + MAX111xState *s = MAX_111X(dev); + int i; + + for (i = 0; i < s->inputs; i++) { + s->input[i] = s->reset_input[i]; + } + s->com = 0; + s->tb1 = 0; + s->rb2 = 0; + s->rb3 = 0; + s->cycle = 0; +} + +static Property max1110_properties[] = { + /* Reset values for ADC inputs */ + DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), + DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), + DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), + DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), + DEFINE_PROP_END_OF_LIST(), +}; + +static Property max1111_properties[] = { + /* Reset values for ADC inputs */ + DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), + DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), + DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), + DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), + DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0), + DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0), + DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90), + DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80), + DEFINE_PROP_END_OF_LIST(), +}; + static void max111x_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->transfer = max111x_transfer; + dc->reset = max111x_reset; } static const TypeInfo max111x_info = { @@ -186,8 +219,10 @@ static const TypeInfo max111x_info = { static void max1110_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->realize = max1110_realize; + device_class_set_props(dc, max1110_properties); } static const TypeInfo max1110_info = { @@ -199,8 +234,10 @@ static const TypeInfo max1110_info = { static void max1111_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); k->realize = max1111_realize; + device_class_set_props(dc, max1111_properties); } static const TypeInfo max1111_info = { From patchwork Fri Jul 3 16:53:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231239 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2565245ilg; Fri, 3 Jul 2020 10:02:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyHmQ/pj6kKNxtH/fOaLtYv0l9+Q8hsjojAondFnxXT6/1pL4mT1vhsxCObfUs1MxVpFEOW X-Received: by 2002:a25:c5cf:: with SMTP id v198mr59032728ybe.6.1593795759771; Fri, 03 Jul 2020 10:02:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795759; cv=none; d=google.com; s=arc-20160816; b=yt6CvarmSwvl2nxpoWn2nhEadlOeadd/lmaaq+p9GTU7MPKKMUtHqaNDWEFdYVzDTb FDDW8Z+2G6LQIFqonmv7FUnhkMPCWORk8Wfb0/RCn9jaznbqDOK8QoAErqurszRsfhDX ug6cqmCnpe/aw7ZZbeuweRSz3uvsNJYu8V6W7AlYHbpHYHwQHfBqMBoWtFLEC8Wf8pI6 6iwA3ZsB5zUQwjwF47YiMdUZirkJoorLxWN96P/hOfM0aSnXiEe7q57HzwJrKHggx067 ewlUZ2hXH48ftwbaDoNmH/T5yu6bx+gfy2DiKf0ovtrg3bwB07o8PEkHiHW3eEQQPahH snOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CWWHX7OpcHVkiC1DN/wEDJR4y3nHHglCvW2K0gYh1/s=; b=SzzjR5AyzvgcdIChR4qd/ohZDfRRFQYqTdRBenK7FE25XsKfOg99y2jHl9z7G17KmB vDs9Y8YG3tkeguK8AQ2qzdF8eiRzKYnk7lsMnsWxpfF8ZOkuFXrg1nOOVBdGYql9d1io grFaMCIjUMr40au9AI53tnYC67TvBY/f1I5kgy4Eg2VLxZbDUftGHElYnnTyhd0r2xvD UEwVM+tQxz/YMS5p5JDShyclwc7tWkMpHCFiKBE+aFRKnQwDEEjH/GKuMOLZ7TfhCS8u U0OBOFo3iVnfuYvMDVOsS1PUos4ZtrnAIpGrnvqBQWfcPS1TE2rHr4A3JX5p4hCJvgnD EJNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jGvfkj7s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d3si12502054yba.205.2020.07.03.10.02.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:02:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jGvfkj7s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP5C-0000YG-Qt for patch@linaro.org; Fri, 03 Jul 2020 13:02:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxQ-0005Kg-PA for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:36 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41077) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxP-0005iT-47 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:36 -0400 Received: by mail-wr1-x42a.google.com with SMTP id z15so22144974wrl.8 for ; Fri, 03 Jul 2020 09:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CWWHX7OpcHVkiC1DN/wEDJR4y3nHHglCvW2K0gYh1/s=; b=jGvfkj7sQJBLzl5pbaYpKSCanbmROjtq3Mfu+3vZ8Ca71mmo5JYGI0iGeovL+Tu/8u YjqsJ1HzNx/g+bqe7ZZDWy94TUkYy1/BXgHsGlQnHsS8YiC9yXWi/rkUVKGHRqm0PN8t RRWEQ5lirou+l/6ziyRugj6hq0mUdG7nIt+/6S+D80chVCiFY2bEsUnExhDT81XgYMjU FWCOLim/wJrkp+8+A0magqiFCrPQImOsFonnNqk6gz+2BEL61HAnXDW8kNL6uTgSibM4 YIL3VwOFA6CuTuacADZQkRl1uBPHRvG9BvI0Y/3tdelI0MGxYAQuexeN93CjtQS9kVSw 8hdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CWWHX7OpcHVkiC1DN/wEDJR4y3nHHglCvW2K0gYh1/s=; b=jIAYJupQTs+pq7CP7czN4XIvhzXwJXW4vuZRNxV2dXGWXqXUY85CmZsc3Uj4oG1GOA ennM9l9VFJ4R+0n6MX0cm7OceFNo9yDCAnjJ58Dh/TrAV2N44GHCm+xwZ+bDTEVxrQYu 7pydYB0XM3EXhYKJTyVovs6o3LdfGYhWlyt3sedJ0Na5vI6RcwdGnMqUuyBdd5dMm34/ Q5Z8vsvz8Xgh2pv8O0AoZ7ZQjjCQz+tTQC+OQbLGR3Kair4y3rakODhaN+7nA7xl6BFN 1/u9fvlvKTViEZrGXQ/LTDeCLSTmFfrpSWg4rPMQlgqm0Wb+H+tkV6KGznyv50pKZDE7 TKTw== X-Gm-Message-State: AOAM53221/w/eZ3yhx/ELnY7jl6Iec/OfHONIlq34oM36L4fWExg/nzy EZTa5rdrdkPS7imfR4q7b7igf0Q7Ty/bGQ== X-Received: by 2002:adf:e6c8:: with SMTP id y8mr40035224wrm.40.1593795273486; Fri, 03 Jul 2020 09:54:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/34] hw/misc/max111x: Don't use vmstate_register() Date: Fri, 3 Jul 2020 17:53:54 +0100 Message-Id: <20200703165405.17672-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The max111x is a proper qdev device; we can use dc->vmsd rather than directly calling vmstate_register(). It's possible that this is a migration compat break, but the only boards that use this device are the spitz-family ('akita', 'borzoi', 'spitz', 'terrier'). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-8-peter.maydell@linaro.org --- hw/misc/max111x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index d0e5534e4f5..abddfa3c660 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -140,8 +140,6 @@ static int max111x_init(SSISlave *d, int inputs) s->inputs = inputs; - vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY, - &vmstate_max111x, s); return 0; } @@ -206,6 +204,7 @@ static void max111x_class_init(ObjectClass *klass, void *data) k->transfer = max111x_transfer; dc->reset = max111x_reset; + dc->vmsd = &vmstate_max111x; } static const TypeInfo max111x_info = { From patchwork Fri Jul 3 16:53:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231242 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2567334ilg; Fri, 3 Jul 2020 10:04:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyd8x6LbcfPEbomG5PjAbTUYDpmJaNV1yRC6PfJn8TaTZDY0uRb5IfyEeZhyIQBwgFCbUiv X-Received: by 2002:ab0:6e3:: with SMTP id g90mr26904476uag.98.1593795896037; Fri, 03 Jul 2020 10:04:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795896; cv=none; d=google.com; s=arc-20160816; b=EB/Vw39MEG0dwEWpnSBRdXwVmoWNIAmSXkNWKS2Ran4q70a1/JInMnwFTVG+9yOyH0 f4kBqiQkZAtOFZqUfbwvGchaPR/VzMGOkOo46gTOSQoV0BCLdveT1SvPcNK6bm3BvQE1 +oHr1h5XkCb6D4sQTHUA+QjvzfwSp4lf2ByFt4xtkkqq2w7Mbd/46w9y4WzomSkYl6CR pzw1aYBm5klyC/5/LFwmZDbmCtVVQoqhwWzF2GKgwRv0cGp8EHmNr2lSrLnAEPn8rHL8 O0SopvwYiijyk17Xrggg1D+6nwcrdyZ94cWVafLLAA4CLj6UPemM+G38UZoS6LW1xg8/ Wkbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BV5GFtOw7R1H4BotV7qt+eZkjeU8tiG6fWsBH/nC4NE=; b=Bunyb7FS3XLmj88PDqWhCkY/EtNBkZ7g0IQvXP6JwynsmC0I6yKUSyxgyuC8740hF5 QyvPt72st6D26sCBhGB9zHQQI50bjOqNSp4FXn039ABV7tV18KkkX4bFMdzQwAaxVQu2 ++MG8r/O6ssMOkGNHEug1pm+SEpfM22dgn3i82cfGAlHtud25ZcBfmQTqIbsf7RfqDtW Y6U8nSbQPbp7fdKOvECpANi3Fd0kUY30yvJEnA1Nfjn7QnMroEzx2tFU8B+KeNUopGi8 0ANH/qXCgIW+blk934D2HtNgRC+B/vGmbcavpIhPibNjwMLgURs1e0DUtvb87HUZrhLI 9oYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EWWololK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y11si1566409vsl.27.2020.07.03.10.04.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:04:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EWWololK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP7P-0004UC-D1 for patch@linaro.org; Fri, 03 Jul 2020 13:04:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxS-0005OK-7A for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:38 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:34978) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxQ-0005jD-A0 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:37 -0400 Received: by mail-wr1-x434.google.com with SMTP id z2so11163586wrp.2 for ; Fri, 03 Jul 2020 09:54:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BV5GFtOw7R1H4BotV7qt+eZkjeU8tiG6fWsBH/nC4NE=; b=EWWololKHeGgEes6IpwthhB0QUqEi+VEEERDOqW5NuniZEoVamTavcURzRXwo/8C8q wntmtgEkXZ/vwY42fEluTzXY06+/4tq/3G3adc/ouZPqtnNF4fpiLEqQAY3ehmBhOcK8 /qSHjhyVy2vSt+kxR9h1/Wh7vL8TFNRaHpGC0e7diU2L1D9MN1P66V6uNC1SbBqkkfcg OGHlJXDibCgpMhpnjM5hG2Bdm6S7cnXniz0t/GjukEjnc/0MT/hMVlxp/vFw25cHCNIQ hwNG3ZEj/6dTL7b/AJJ+9WPrBY6MK9JgtE+ysNY5t/WpfPjT4B/qD5nBHAppns+UF6Db BjRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BV5GFtOw7R1H4BotV7qt+eZkjeU8tiG6fWsBH/nC4NE=; b=ZQSyP7aPWVsdjGo0xpjKlKc+mEw2wssfDZU2yR94ULi68DP0B8CtVwJ0Hvaw4/QXGU 3bh9cW+LV9DED3Xz1llOUf4jZR1hpTtWaamL4y9tqutdlB+llB7XTtXWa9oGxS2al3rk uterkInQZYi9jEFK1Ois9qrALbOEMAJHMV/pN7JwjPBOgHF9kLoGlub5oEkRiVe3PVqv VNnFJla3+BOnnYj3rlTuW9jQfdUP78El3pxvlc+PnpyIYa+aCdvyLWrIAWHExfwty1Np WEabxSrnTtIZFlxvhJ7+7ZA/i3lYqjYM4AHHEoFsI9gAO165g6HoxZy23REbwghrx1Lx zFmg== X-Gm-Message-State: AOAM531JGo1FYAmHcbvJKTukSvvp1KLhidyv86GR84TMQAZUWLyJvt1K BWvOO/rSNbaYBVJ+GYqkbuoyTX0/RJRRZA== X-Received: by 2002:adf:8444:: with SMTP id 62mr35981389wrf.278.1593795274578; Fri, 03 Jul 2020 09:54:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/34] ssi: Add ssi_realize_and_unref() Date: Fri, 3 Jul 2020 17:53:55 +0100 Message-Id: <20200703165405.17672-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add an ssi_realize_and_unref(), for the benefit of callers who want to be able to create an SSI device, set QOM properties on it, and then do the realize-and-unref afterwards. The API works on the same principle as the recently added qdev_realize_and_undef(), sysbus_realize_and_undef(), etc. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-9-peter.maydell@linaro.org --- include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++ hw/ssi/ssi.c | 7 ++++++- 2 files changed, 32 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 93f2b8b0beb..4be5325e654 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -79,6 +79,32 @@ extern const VMStateDescription vmstate_ssi_slave; } DeviceState *ssi_create_slave(SSIBus *bus, const char *name); +/** + * ssi_realize_and_unref: realize and unref an SSI slave device + * @dev: SSI slave device to realize + * @bus: SSI bus to put it on + * @errp: error pointer + * + * Call 'realize' on @dev, put it on the specified @bus, and drop the + * reference to it. Errors are reported via @errp and by returning + * false. + * + * This function is useful if you have created @dev via qdev_new() + * (which takes a reference to the device it returns to you), so that + * you can set properties on it before realizing it. If you don't need + * to set properties then ssi_create_slave() is probably better (as it + * does the create, init and realize in one step). + * + * If you are embedding the SSI slave into another QOM device and + * initialized it via some variant on object_initialize_child() then + * do not use this function, because that family of functions arrange + * for the only reference to the child device to be held by the parent + * via the child<> property, and so the reference-count-drop done here + * would be incorrect. (Instead you would want ssi_realize(), which + * doesn't currently exist but would be trivial to create if we had + * any code that wanted it.) + */ +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp); /* Master interface. */ SSIBus *ssi_create_bus(DeviceState *parent, const char *name); diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index 67b48c31cd6..a35d7ebb266 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -90,11 +90,16 @@ static const TypeInfo ssi_slave_info = { .abstract = true, }; +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp) +{ + return qdev_realize_and_unref(dev, &bus->parent_obj, errp); +} + DeviceState *ssi_create_slave(SSIBus *bus, const char *name) { DeviceState *dev = qdev_new(name); - qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal); + ssi_realize_and_unref(dev, bus, &error_fatal); return dev; } From patchwork Fri Jul 3 16:53:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231243 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2567962ilg; Fri, 3 Jul 2020 10:05:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxn1N/6j7kjvRmpgtfgG7jR7J0RIpSz87Nkb7Q1t0srs348VzbSVblZEIIdX0pScdABZY2c X-Received: by 2002:a25:3155:: with SMTP id x82mr4664422ybx.492.1593795940302; Fri, 03 Jul 2020 10:05:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593795940; cv=none; d=google.com; s=arc-20160816; b=zDgpun8Jea8ttaP9pnQ8PQjhqDxGnCxEOVxqKFJS+IJUQ6ntiC+ziSX9J1DyuLZBsZ TJCXIOW42si13FCNzeYV37XWJacefmXLK3CV5MuwBPhRkM5YyOqZS2QlbCInc6dFDfTE 1ZVTipMgNrY1UYvIRCLdO2lAa7qvnlLr4NEEBpX9tzfgJuZMCkvtCXnkYBlYfAEewwMy GcItzxT6vj5Ub9gCkWbnaBh7WoZ2r+SYF+lFF8I7PHlSZIrpXGQxSZqitRfuEShJ5NWK +ZM+1pyy3hSCYkyqeV9WlnUqBNLEnqd2w0BE4pZzGwtxHZ7SA/P54C1VXWCEcIdkYQSG 7/cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=N/Piq7VUujhGlA1t1Zo+1vhhxB5erHw4tA6+anvZITQ=; b=AIu5of/MJjsuYWVh3FPtSmlpZ7Enfy5KvVBSjfBGGXSJhHfI9lVkhnoz1TaZKYRTjZ IFymAqaVLSA+5RDzXeqc8HaMk0T9lKU6AYSCs59ExKMG97c5+ke0dqYsJfDVVKE8ChQz ZYe6+5UER+twEDd2aVmlEhq/hhIbiRXgZiUxwFFZPWyd7r7RDtp8NDoxidXq7jJ3OAuj S6HTYmkhN+CrtSgzXUYO2B7Q/Aa8SpqytE/XRMOZctTHp2ejDCGclMF3Cq8KGCUq2i8W e4va98zDgDJrEvnXz0BDrTuFGoDrAer6LWlS1nNS0cHoSsLfzTjLbJCPg4UxPkNLqsHE aL/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cB1QV/RY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l9si724320ybq.77.2020.07.03.10.05.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:05:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cB1QV/RY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP87-0004Yl-PJ for patch@linaro.org; Fri, 03 Jul 2020 13:05:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxS-0005Q3-RI for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:38 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxR-0005ja-5x for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:38 -0400 Received: by mail-wr1-x436.google.com with SMTP id k6so33437882wrn.3 for ; Fri, 03 Jul 2020 09:54:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=N/Piq7VUujhGlA1t1Zo+1vhhxB5erHw4tA6+anvZITQ=; b=cB1QV/RYnMHCz3vyYQO44PtoTVfvt8N9Be1jvedQ6B7BRg8iEOchpandVaUQI0Pa2v x6jWguYmqGxoaUSRQ33Fho1PQbsKGoMtKLnDXXkEvMEiFa+TSCKOwcrwhYfIWkVxcQO6 loh8El8GCKPkpGr3UjxAVPBrsc/6qQsyPbAx3RTFy8QDQqlasuR3aAOink5fg13Jt7L6 Vr0GHCpeYR5p/diHLDqtej3kpceWYBEz7DqdQOS1Y0ND7UlhxNEeexbul/H1wgQEjnUr 0XiP+8sVtTd58bGI4/PAlTjJW5tgJHH6TJlZRodx1Nht9A5qygoyo4Czbv/t2LnnqLP9 MdUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N/Piq7VUujhGlA1t1Zo+1vhhxB5erHw4tA6+anvZITQ=; b=fE5FJ7hbxO9GWhRx7oLaWRBAJ8BHCS1tI2RUYat51mYQlSCyXGY7uqueuDzn3L0SJU VyNI5C/velhqGHCb/F8g0jyuWOtgBWNqKH0OjtBWMyy2gaH7TbsKFnWLsaRUZR16QXjW 8QV4UMtaB3M9c6wCq7jqLZelCSmTMlC/5cCW8Bsj6G+qZ2craXCE7M6dcg9339Z/63od p0/cZTOqDDgjkLwGps4WsEIiZ2mU/Zg2yEi4QYj0hi/9p5XHLTmDDFx04iC+oXJCkxRl Jgib10/9vzskfIVsjKonnBNFMv8aSDcuE1IBxqsHXKZ3Nb2RladX3BB8Hl3+0oVvMYC7 385A== X-Gm-Message-State: AOAM5317MXuafGPP/vTLn5xiumS5Iv/3RFqx77/NbmE12hYKEoFWaCyZ E6+4waB2FCmnLe6FlwVMdqgKBcbEE/OyNw== X-Received: by 2002:adf:f3cd:: with SMTP id g13mr35950993wrp.45.1593795275627; Fri, 03 Jul 2020 09:54:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/34] hw/arm/spitz: Use max111x properties to set initial values Date: Fri, 3 Jul 2020 17:53:56 +0100 Message-Id: <20200703165405.17672-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the new max111x qdev properties to set the initial input values rather than calling max111x_set_input(); this means that on system reset the inputs will correctly return to their initial values. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200628142429.17111-10-peter.maydell@linaro.org --- hw/arm/spitz.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 11e413723f4..93a25edcb5b 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -731,11 +731,14 @@ static void spitz_ssp_attach(SpitzMachineState *sms) qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); bus = qdev_get_child_bus(sms->mux, "ssi2"); - sms->max1111 = ssi_create_slave(bus, "max1111"); + sms->max1111 = qdev_new("max1111"); max1111 = sms->max1111; - max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); - max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0); - max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); + qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, + SPITZ_BATTERY_VOLT); + qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0); + qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */, + SPITZ_CHARGEON_ACIN); + ssi_realize_and_unref(sms->max1111, bus, &error_fatal); qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS, qdev_get_gpio_in(sms->mux, 0)); From patchwork Fri Jul 3 16:53:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231248 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2570105ilg; Fri, 3 Jul 2020 10:08:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxt1y/+epDKbOa/7CGKIGWhUBskS8jC9CU+TNvrsFQ9OP+9jM16Der4a22ZVyppjLw5ZdhX X-Received: by 2002:a25:4905:: with SMTP id w5mr58615331yba.159.1593796096962; Fri, 03 Jul 2020 10:08:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796096; cv=none; d=google.com; s=arc-20160816; b=gXyh6i5oqHYELPIXDlrApkS+Naee+SqoCelRfuGBm4rDfBbNYuzyCq01yN7YMAVBRF 5wyAtu7m5HydDuCJz1ZjAxekGpB9/IXFXk/9RrWuHGZR87rWeRxGarHdnRRQDhOGzStx dH8vqT3zQBOVmSxJtHFEJUKEZ/vgj4ZGRLemx827FzEWmDLkfMaW78HwzA3pszczrmF5 gz/G/J5sLCLvRzCSvGnDe1AMJMAhFreT5+B2cg/1c/nhjF0rq97cfImatgvGyfSEuK+x /epNwTwUmWgpOKlz2KgG9hwwvuyryuGscTTS7FUwx3icz0BklZEyJGupodL+xJYmfYfl bALA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oD1qiWavKhquHomKBKPR8Lyah9vGykUE9wA4yaevKfY=; b=Z6T6nuiIYTnOV6Wn+TzyM+T/l3yCUtTF4mlIw0J2sWz5GRYfwqeCJQy/ozg7BdlEwa wIU5s6gBa3PXS58HAXPmgOwkkHPrr1YKA4QF/Vi7uy93VchjT4ML2f8UaHbFI2mwtJlH VqEz9aKM5lNEI6FhI9U7bvR8mD/PR+S3Aw2tR7vysWXcFgUHsMRESjh7lT8TkKZtk/1P u1sCJ7Qnv69u7iLJXvuVTiJKfHPJhcoBPzYNBBy4TMhnyZeArPz/mS04ZYAqdAfwe0pc yxUkkOJ9YxzxQaTVpN/oN7Df7iHMuC1q66N+602qXNcFwnUEpfmXNECF99gFoNa86YQP QcBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XpS9NNSO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f80si11410867yba.451.2020.07.03.10.08.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:08:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XpS9NNSO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPAe-0002EQ-9z for patch@linaro.org; Fri, 03 Jul 2020 13:08:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxU-0005Tj-Am for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:40 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34968) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxS-0005l1-Cn for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:39 -0400 Received: by mail-wr1-x429.google.com with SMTP id z2so11163730wrp.2 for ; Fri, 03 Jul 2020 09:54:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oD1qiWavKhquHomKBKPR8Lyah9vGykUE9wA4yaevKfY=; b=XpS9NNSOvH2yaLLeLVVJvNBc49U8pNbeQRKHCDj3hogS9UzJgvxnW5VjalzmRFAphD jRQdW1jz5oHV5xvqqnMl24qox9YSSWlRXeD5N+xpMgdQUr6jxsN/b4YpCEI3g0fCcPX0 i7T70zAHn4Bl0MUT2B/1zWyLp5/3tKR5tI4KZA8AVYv4GQ8CSn1pLwnr2lYaRwgmrscn +LDwFLuNOQgLZ7FbR4ss0tzlyqJeyVT1gPHFKWZsD8lHmGBt7Shu9fYtyBvht3y+VENb rSCpW9RoJ6+HVV94NOYshY9B5dWxkxCyAhdHfbvUTg4mMWJRARDOD0tt4kSl2RnHSh2y 85PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oD1qiWavKhquHomKBKPR8Lyah9vGykUE9wA4yaevKfY=; b=rRsBph/ljjI98F5eTAFdNB5NL9jFaD149B/34TMm4lvYpmlWt7805vZTW56yDPysL5 +teC/Xv2TXfbi7qTQjCbxc2wK+f9jokj9GP7MnUUMfkvkuu+nO+Xv8ddiS6Ush5Z6cL6 lCOhnFqU8k/GsTEJc4fCBYENCQpeQ4x3m8Mr/+NHg9gD0wCAQTLjLiYqE+woM6xBl9ZL h6fnDqIY6maT/fr4qijFZb9km1n4wlFPfZBa8IliWmkICOAiSEs671/URBWBrmiejXOW AVAbPwIMYUNu/K2KQjQO7SlqUBpIJL4KoBQbZocyB2NQaKco5VUYq3BgVaoAoVBUoqnw TBAg== X-Gm-Message-State: AOAM533DaJslpPZB3TemFDw7OnpLB+jng7D9w9E7g70pdiGS3SmpLqcL MXhPM0uvYkqYMJ10aBn0JNNbkSRWesYxbg== X-Received: by 2002:a5d:69cf:: with SMTP id s15mr26617729wrw.10.1593795276757; Fri, 03 Jul 2020 09:54:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/34] hw/misc/max111x: Use GPIO lines rather than max111x_set_input() Date: Fri, 3 Jul 2020 17:53:57 +0100 Message-Id: <20200703165405.17672-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The max111x ADC device model allows other code to set the level on the 8 ADC inputs using the max111x_set_input() function. Replace this with generic qdev GPIO inputs, which also allow inputs to be set to arbitrary values. Using GPIO lines will make it easier for board code to wire things up, so that if device A wants to set the ADC input it doesn't need to have a direct pointer to the max111x but can just set that value on its output GPIO, which is then wired up by the board to the appropriate max111x input. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-11-peter.maydell@linaro.org --- include/hw/ssi/ssi.h | 3 --- hw/arm/spitz.c | 9 +++++---- hw/misc/max111x.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 4be5325e654..5fd411f2e4e 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -111,7 +111,4 @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name); uint32_t ssi_transfer(SSIBus *bus, uint32_t val); -/* max111x.c */ -void max111x_set_input(DeviceState *dev, int line, uint8_t value); - #endif diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 93a25edcb5b..fa592aad6d6 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -696,13 +696,14 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) static void spitz_adc_temp_on(void *opaque, int line, int level) { + int batt_temp; + if (!max1111) return; - if (level) - max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); - else - max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); + batt_temp = level ? SPITZ_BATTERY_TEMP : 0; + + qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp); } static void corgi_ssp_realize(SSISlave *d, Error **errp) diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index abddfa3c660..3a5cb838445 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -131,12 +131,21 @@ static const VMStateDescription vmstate_max111x = { } }; +static void max111x_input_set(void *opaque, int line, int value) +{ + MAX111xState *s = MAX_111X(opaque); + + assert(line >= 0 && line < s->inputs); + s->input[line] = value; +} + static int max111x_init(SSISlave *d, int inputs) { DeviceState *dev = DEVICE(d); MAX111xState *s = MAX_111X(dev); qdev_init_gpio_out(dev, &s->interrupt, 1); + qdev_init_gpio_in(dev, max111x_input_set, inputs); s->inputs = inputs; @@ -153,13 +162,6 @@ static void max1111_realize(SSISlave *dev, Error **errp) max111x_init(dev, 4); } -void max111x_set_input(DeviceState *dev, int line, uint8_t value) -{ - MAX111xState *s = MAX_111X(dev); - assert(line >= 0 && line < s->inputs); - s->input[line] = value; -} - static void max111x_reset(DeviceState *dev) { MAX111xState *s = MAX_111X(dev); From patchwork Fri Jul 3 16:53:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231297 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2576422ilg; Fri, 3 Jul 2020 10:16:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzYB2gJwzDi40M4n3pbzQN6cePa1+aXc2w4n+G0OvQwiG+48Sg7XlotIWAeiEK5KkESOohb X-Received: by 2002:a25:be81:: with SMTP id i1mr60382671ybk.243.1593796597136; Fri, 03 Jul 2020 10:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796597; cv=none; d=google.com; s=arc-20160816; b=gQHsiGsxwtOq87iJb/wgJpB3NBQWTYvSKuIm7dl3+d+0C00K/yijwO0RnihvGdP4mG KqW3xKo4T+bf7Cdb34FM5v7T+OPvrNTikXPGDX0jZ34hq9I0EdMoc2c3HKstOEBs9bJX W6BW0cWQtYJKHiWqaNZ4U5iCPdsaDUtWRDqY8fiLnQ9IsfOqgCA8RqRBZyyoSiEoOSug G58nduytZXDm5I5EWRap5NPcsHunKgBh11kNL19pFbS6xAtqfjc8DbeXKVzu9FIAoBRs nMY43yJVzrI+JvTuvP2Obb88zmkuZ6D9/gz3CwUmX97PLp6qzhqTox72q23HOJqhea/Z BEAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UtlmxB+fyNUWPbT2HQyqJRiOYmojja7C2iCam/D7HtA=; b=LN9Am9gOotAUElF/inNNRks7Tz7qQfXiX690QOphVCzw+/oB6Qa/NIZf5oUk25YDRs z6FDH72U1nbE06MweBT5PHnpAyJd09ZfZ7TGyVuFOnkWccQALFK0RHM3ITfzfZTYpDum EjyLUEySfl8ol6hMTYWQ+S0hDGQFo38jIRod+pM1+jfRH4el8coDUU8ld+eWM+dM0Agc JK9VEWXgFXNYi42OBoS2nLmHNw5bPXCm4rL5sBPHwe4deXz1WWlmRqDHv5AzQ53MSQwW xp6qouSLJHHsdezHmMHnORBVedco3yMN8boTO1AEQSzZKDEfVeObq/xGm2OQfGL+9AWq hf2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HJSxryxx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i204si11537267ybc.254.2020.07.03.10.16.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:16:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HJSxryxx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPIi-0007o3-Kt for patch@linaro.org; Fri, 03 Jul 2020 13:16:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxV-0005X0-Jm for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:41 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:36646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxT-0005mD-Ko for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:41 -0400 Received: by mail-wr1-x42a.google.com with SMTP id k6so33437975wrn.3 for ; Fri, 03 Jul 2020 09:54:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UtlmxB+fyNUWPbT2HQyqJRiOYmojja7C2iCam/D7HtA=; b=HJSxryxxho2hjPzV9+3cfichOP0MDserb92dcfHp69Y7P7xnA5Cuw/pl+rgDPw+qcc l7xnx8NsW3Im+rXxul3IhjHan/X2irSHx4cxHHzjlOpuoG1xsqAJWWoplh0uwiVxrNPT O1cERSGfFQllTENvM3nye1Jp/YwKJKQEJicKVzJ1B+Rp3NWfXZ9pBE0/JNirOT8oQyYx jrJt0ZhmYxizw8yqt8tYgtvs5y1akq/1+uqvqsjoKDY1Ffn722m7v0gLC7r5e+HQPKe1 IxWlawjCRv09P31w9ADYVKIBJuAM6Kp5NICmUg3TvhJBXAG7RYCWRwrRpKhvPjFlodcK GXQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UtlmxB+fyNUWPbT2HQyqJRiOYmojja7C2iCam/D7HtA=; b=obixuCdcqBkqQ6ebqmoWLl4Tlux5aIo3LhRy7uIGLeF4kyakDBjl3XlbfuwnWmPZtK wbAzwhBBwOO0q+5WR8hjTzIbXgjAgOUwNV683+um1u5gU5kRcXhQOJ3EDHw77/eRPbKh wOsiK7iirAQb0nWXYxraBTKoDoew4/IVCehhFIZ6dq2fuPMp7k+voA5vIRB151hsYJo0 i40SxHehfvtvOlo/pfg3nu6/82tsnZ6ML0K+DQBLYySu5UV1EuYdB6Shi7V8qlav00Db tRV3x4TPLekanDk35sKAaSoMnZ04V+aC+Y8KvVrq+huEiejdLBh2HfD+2TSD4BJiicZT Ssyw== X-Gm-Message-State: AOAM530f8V17CNPw5Zv828KqZv48PMYLWZAuLtThnaNCAs6FI00HGsjm WZEBH3FZgyU7xzweX4C+m8E71m2QPndLJg== X-Received: by 2002:a5d:4b0f:: with SMTP id v15mr2686353wrq.216.1593795277823; Fri, 03 Jul 2020 09:54:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/34] hw/misc/max111x: Create header file for documentation, TYPE_ macros Date: Fri, 3 Jul 2020 17:53:58 +0100 Message-Id: <20200703165405.17672-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a header file for the hw/misc/max111x device, in the usual modern style for QOM devices: * definition of the TYPE_ constants and macros * definition of the device's state struct so that it can be embedded in other structs if desired * documentation of the interface This allows us to use TYPE_MAX_1111 in the spitz.c code rather than the string "max1111". Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200628142429.17111-12-peter.maydell@linaro.org --- include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++ hw/arm/spitz.c | 3 ++- hw/misc/max111x.c | 24 +---------------- MAINTAINERS | 1 + 4 files changed, 60 insertions(+), 24 deletions(-) create mode 100644 include/hw/misc/max111x.h -- 2.20.1 diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h new file mode 100644 index 00000000000..af7f1017eff --- /dev/null +++ b/include/hw/misc/max111x.h @@ -0,0 +1,56 @@ +/* + * Maxim MAX1110/1111 ADC chip emulation. + * + * Copyright (c) 2006 Openedhand Ltd. + * Written by Andrzej Zaborowski + * + * This code is licensed under the GNU GPLv2. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef HW_MISC_MAX111X_H +#define HW_MISC_MAX111X_H + +#include "hw/ssi/ssi.h" + +/* + * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU + * is an SSI slave device. It has either 4 (max1110) or 8 (max1111) + * 8-bit ADC channels. + * + * QEMU interface: + * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value + * of each ADC input, as an unsigned 8-bit value + * + GPIO output 0: interrupt line + * + Properties "input0" to "input3" (max1110) or "input0" to "input7" + * (max1111): initial reset values for ADC inputs. + * + * Known bugs: + * + the interrupt line is not correctly implemented, and will never + * be lowered once it has been asserted. + */ +typedef struct { + SSISlave parent_obj; + + qemu_irq interrupt; + /* Values of inputs at system reset (settable by QOM property) */ + uint8_t reset_input[8]; + + uint8_t tb1, rb2, rb3; + int cycle; + + uint8_t input[8]; + int inputs, com; +} MAX111xState; + +#define TYPE_MAX_111X "max111x" + +#define MAX_111X(obj) \ + OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) + +#define TYPE_MAX_1110 "max1110" +#define TYPE_MAX_1111 "max1111" + +#endif diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index fa592aad6d6..1400a56729d 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -29,6 +29,7 @@ #include "audio/audio.h" #include "hw/boards.h" #include "hw/sysbus.h" +#include "hw/misc/max111x.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" #include "cpu.h" @@ -732,7 +733,7 @@ static void spitz_ssp_attach(SpitzMachineState *sms) qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); bus = qdev_get_child_bus(sms->mux, "ssi2"); - sms->max1111 = qdev_new("max1111"); + sms->max1111 = qdev_new(TYPE_MAX_1111); max1111 = sms->max1111; qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, SPITZ_BATTERY_VOLT); diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index 3a5cb838445..7e6723f3435 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -11,34 +11,12 @@ */ #include "qemu/osdep.h" +#include "hw/misc/max111x.h" #include "hw/irq.h" -#include "hw/ssi/ssi.h" #include "migration/vmstate.h" #include "qemu/module.h" #include "hw/qdev-properties.h" -typedef struct { - SSISlave parent_obj; - - qemu_irq interrupt; - /* Values of inputs at system reset (settable by QOM property) */ - uint8_t reset_input[8]; - - uint8_t tb1, rb2, rb3; - int cycle; - - uint8_t input[8]; - int inputs, com; -} MAX111xState; - -#define TYPE_MAX_111X "max111x" - -#define MAX_111X(obj) \ - OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) - -#define TYPE_MAX_1110 "max1110" -#define TYPE_MAX_1111 "max1111" - /* Control-byte bitfields */ #define CB_PD0 (1 << 0) #define CB_PD1 (1 << 1) diff --git a/MAINTAINERS b/MAINTAINERS index dec252f38b1..c31c878c635 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -787,6 +787,7 @@ F: hw/gpio/max7310.c F: hw/gpio/zaurus.c F: hw/misc/mst_fpga.c F: hw/misc/max111x.c +F: include/hw/misc/max111x.h F: include/hw/arm/pxa.h F: include/hw/arm/sharpsl.h F: include/hw/display/tc6393xb.h From patchwork Fri Jul 3 16:53:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231246 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2569020ilg; Fri, 3 Jul 2020 10:06:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRYa/uWw4kdmu0MOgFni5R/7XcuQZR7iStmJN6PoCakMc63ynhusbCbhUbD/nrpFWD2Nhn X-Received: by 2002:a25:bc81:: with SMTP id e1mr57331779ybk.375.1593796019234; Fri, 03 Jul 2020 10:06:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796019; cv=none; d=google.com; s=arc-20160816; b=uFMJYSuu+ubnqyOAUYkCKlXmlPzYvCHZEmxCzRcv1koJh0sRAz5phDoSeSnvzJJqup RgoFaNuYI1DfE6GrmwOJ+xNhTovGeME0jqDHvJCQyEs5ny3rJrMEw1hNutXh0dzXLTqI 3i6LntGOUVP3yhEHBqJ+RxIBFY2rhrmahqztMVJxVv19+QY79EiU7bbq0DQK06jDhBAp BQ2fsIBiFx47/t9a4ROa3PpZzDsVZ1Px/rvQU1Tn9F8lT/wVfrGUylQh0Pl/qNqQTyH/ AbWa3gsThbXf2zx0a0cSUxpntoZWaAshptG0qYQIEVYyypF3aRlEQx5f1omPFl7j/kBg uFqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4gjeoLHX0Ef+gOr8X5gcli+FPO0iTyDXIyWGEogpcRg=; b=CZZfMvuXzNzc72f3/ti5xiaW34PoBF09IxHL2/kkxEX3gZBCnGDFESpRPBIEn7lIwH iPqNzY/cW/8tIAN5cQE0hVTjoxYnTmAEtjeerPZrQrys8LiftXos4gnDbx8aECIpT2hr oSzuodid3IClb1CyZGT5X3Qsy/GIWkKSuqmjLrCbfSJE47KkRKfOvn1TZWgdLLdGCVdY /Jw2twH74ptws8qp6bDUeazVmLtQbY0vQeaEV3d7ber8ctyaZqNY1z8CNWYP6nfqeQDW 1Yw4X33CIyeO5aTL0x+LMaokMH+oeI5aR/aFd6gtZcsWBFmj4hxTHa2EzmEDCHkqwj5/ MrcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="SCoz5y/M"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d18si12407559ybc.349.2020.07.03.10.06.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:06:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="SCoz5y/M"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP9O-0008Ug-9R for patch@linaro.org; Fri, 03 Jul 2020 13:06:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50386) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxX-0005bH-Aq for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:43 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43475) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxV-0005ng-5E for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:43 -0400 Received: by mail-wr1-x435.google.com with SMTP id j4so30987805wrp.10 for ; Fri, 03 Jul 2020 09:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4gjeoLHX0Ef+gOr8X5gcli+FPO0iTyDXIyWGEogpcRg=; b=SCoz5y/MLBmRIz6ER8a3tknYzLLTXtuliaNa4s9Z5bCnNTahoW4FGXaRGCqQ8sfhtn IIbJPXeO4PU0HvD1BOCioaD+7DrxRZSYKtGwENbOb6IUlO4ilF5ETshqnGHupnhRrlCT 3t/MeQcY1iQf5WTIEyetYS9kWYoVZ8+ceM/rPJ933zSsODfwCMi2dyf42keLevxdJ5yt SbCw5XF+esVDs1MIFhIbDQATfEWZa1b4SEPy0lpT7QBV4JpumvvXTi5q4cgop5kPk7tQ iwJEG2tG07nA7gG8Lsus/bKecR/vWbd1BoZI/tVtS2hJUK+jfqjcAuphJZnj4Ttrt8Hu 7VhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4gjeoLHX0Ef+gOr8X5gcli+FPO0iTyDXIyWGEogpcRg=; b=E/HkEAnrHtqZmQ7OxsIUa2miSqgQtfQxt8cglM4JoRxBzkWGvPBRMLRegNXTorWs5i SUZG0Up2WS5ZJMtMLcKUeROaWIAS2FiXPCuo7H1Jr8mynY09wXdrcYDbqbbGWgqDF5YZ qrkprLwpvZeCtv8gKWtpNknl9nkCRd4Xn/s8AXgbvtDOzdtAIYlJofHXAmpvGCMxAspr 2N7z7BzwA/1ZrtArgDmNxppqeWsqWuMh0toxcoCUJSFLmCGAzWBNzGG9zS0pumCiXq6U 9jMdOrtLHSSzzXaEyeqXLVxrITjArvEs7XIWKnvlOKz/BsTznYpw5+O1EL4IAuvZQzTB 1Jew== X-Gm-Message-State: AOAM533HWL9pFP0orCGhPQKsMIWj0RiL73V4GOTG87YGXZNL6NS/WNcv XWoJQ2mJ6zpR+AipfmBdq9UI74ct0xDQsQ== X-Received: by 2002:adf:f34e:: with SMTP id e14mr37393617wrp.299.1593795279194; Fri, 03 Jul 2020 09:54:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/34] hw/arm/spitz: Encapsulate misc GPIO handling in a device Date: Fri, 3 Jul 2020 17:53:59 +0100 Message-Id: <20200703165405.17672-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently we have a free-floating set of IRQs and a function spitz_out_switch() which handle some miscellaneous GPIO lines for the spitz board. Encapsulate this behaviour in a simple QOM device. At this point we can finally remove the 'max1111' global, because the ADC battery-temperature value is now handled by the misc-gpio device writing the value to its outbound "adc-temp" GPIO, which the board code wires up to the appropriate inbound GPIO line on the max1111. This commit also fixes Coverity issue CID 1421913 (which pointed out that the 'outsignals' in spitz_scoop_gpio_setup() were leaked), because it removes the use of the qemu_allocate_irqs() API from this code entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-13-peter.maydell@linaro.org --- hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 87 insertions(+), 42 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 1400a56729d..bab9968ccee 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -51,6 +51,7 @@ typedef struct { DeviceState *max1111; DeviceState *scp0; DeviceState *scp1; + DeviceState *misc_gpio; } SpitzMachineState; #define TYPE_SPITZ_MACHINE "spitz-common" @@ -658,8 +659,6 @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) #define SPITZ_GPIO_MAX1111_CS 20 #define SPITZ_GPIO_TP_INT 11 -static DeviceState *max1111; - /* "Demux" the signal based on current chipselect */ typedef struct { SSISlave ssidev; @@ -695,18 +694,6 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ -static void spitz_adc_temp_on(void *opaque, int line, int level) -{ - int batt_temp; - - if (!max1111) - return; - - batt_temp = level ? SPITZ_BATTERY_TEMP : 0; - - qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp); -} - static void corgi_ssp_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); @@ -734,7 +721,6 @@ static void spitz_ssp_attach(SpitzMachineState *sms) bus = qdev_get_child_bus(sms->mux, "ssi2"); sms->max1111 = qdev_new(TYPE_MAX_1111); - max1111 = sms->max1111; qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, SPITZ_BATTERY_VOLT); qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0); @@ -810,27 +796,66 @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu) /* Other peripherals */ -static void spitz_out_switch(void *opaque, int line, int level) +/* + * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards. + * + * QEMU interface: + * + named GPIO inputs "green-led", "orange-led", "charging", "discharging": + * these currently just print messages that the line has been signalled + * + named GPIO input "adc-temp-on": set to cause the battery-temperature + * value to be passed to the max111x ADC + * + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x + */ +#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio" +#define SPITZ_MISC_GPIO(obj) \ + OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO) + +typedef struct SpitzMiscGPIOState { + SysBusDevice parent_obj; + + qemu_irq adc_value; +} SpitzMiscGPIOState; + +static void spitz_misc_charging(void *opaque, int n, int level) { - switch (line) { - case 0: - zaurus_printf("Charging %s.\n", level ? "off" : "on"); - break; - case 1: - zaurus_printf("Discharging %s.\n", level ? "on" : "off"); - break; - case 2: - zaurus_printf("Green LED %s.\n", level ? "on" : "off"); - break; - case 3: - zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); - break; - case 6: - spitz_adc_temp_on(opaque, line, level); - break; - default: - g_assert_not_reached(); - } + zaurus_printf("Charging %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_discharging(void *opaque, int n, int level) +{ + zaurus_printf("Discharging %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_green_led(void *opaque, int n, int level) +{ + zaurus_printf("Green LED %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_orange_led(void *opaque, int n, int level) +{ + zaurus_printf("Orange LED %s.\n", level ? "off" : "on"); +} + +static void spitz_misc_adc_temp(void *opaque, int n, int level) +{ + SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque); + int batt_temp = level ? SPITZ_BATTERY_TEMP : 0; + + qemu_set_irq(s->adc_value, batt_temp); +} + +static void spitz_misc_gpio_init(Object *obj) +{ + SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj); + DeviceState *dev = DEVICE(obj); + + qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1); + qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1); + qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1); + qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1); + qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1); + + qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1); } #define SPITZ_SCP_LED_GREEN 1 @@ -850,12 +875,22 @@ static void spitz_out_switch(void *opaque, int line, int level) static void spitz_scoop_gpio_setup(SpitzMachineState *sms) { - qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8); + DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); + sms->misc_gpio = miscdev; + + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, + qdev_get_gpio_in_named(miscdev, "charging", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, + qdev_get_gpio_in_named(miscdev, "discharging", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, + qdev_get_gpio_in_named(miscdev, "green-led", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, + qdev_get_gpio_in_named(miscdev, "orange-led", 0)); + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, + qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0)); + qdev_connect_gpio_out_named(miscdev, "adc-temp", 0, + qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP)); if (sms->scp1) { qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, @@ -863,8 +898,6 @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms) qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0)); } - - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); } #define SPITZ_GPIO_HSYNC 22 @@ -1217,12 +1250,24 @@ static const TypeInfo spitz_lcdtg_info = { .class_init = spitz_lcdtg_class_init, }; +static const TypeInfo spitz_misc_gpio_info = { + .name = TYPE_SPITZ_MISC_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SpitzMiscGPIOState), + .instance_init = spitz_misc_gpio_init, + /* + * No class_init required: device has no internal state so does not + * need to set up reset or vmstate, and does not have a realize method. + */ +}; + static void spitz_register_types(void) { type_register_static(&corgi_ssp_info); type_register_static(&spitz_lcdtg_info); type_register_static(&spitz_keyboard_info); type_register_static(&sl_nand_info); + type_register_static(&spitz_misc_gpio_info); } type_init(spitz_register_types) From patchwork Fri Jul 3 16:54:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231251 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2572048ilg; Fri, 3 Jul 2020 10:10:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycF9XqFrM/MzkB4/Pz86ChpcQg5O6QRDqqtX/ROUj8m50zGEseBWkJbW7kUWj6Je0hg1kT X-Received: by 2002:a25:8e08:: with SMTP id p8mr6257857ybl.63.1593796240520; Fri, 03 Jul 2020 10:10:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796240; cv=none; d=google.com; s=arc-20160816; b=yVEDKdptE4SIzdgvLtgRI6+vqwgaFv6MFOWO1yaRB88IWuTyCLmuOE0eCoME752w/2 Hw1nLfkmD+lKmNRUrbJFuIWYcGiZcaw5X0L+qOXM5Pp8hUjBH+dNXrex0d4bibgTygqO N5zBJL/PSUtJPChyCaZBHXmY3Tv8+Tb+/4I7lF2Wy38u5J3wzXO0gR9ZTM7mNwCD4P7X nXd/9a2k9W3Q9WBms55BsqXwLwY1TY93OdLgKjTyrWsQ2NjV+KqHugqbn0/ziaLzkwrm Li7vYcAfB2pzFhGzIhdID/x/UhTwUJiSJ/aGzBSRjbWXALv5wlK2/alHFKFPqTIxkI3b aEwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ojDJUB2Dp/Uy9824bM0ku4i9qeSH5AqC6BZl5G2EuJg=; b=VMAxx0G7p+CV07GZkpmL7ugCcDRLnr9jblrwgGTSM3QSYyiCOaJ7oqWOVqCnja6okR mU8B30oQ6DwlksuK54DYOIjT+HT09Doq1V3GS3t0D0m8IuyL/PLcuDyEUybGJaKOCpdp fDiZNvr2IJIkD/a6CYrsNDaKC5fEuzVTZ6AndqvzhSrySgUA04+DsXcPLzOHGpxgrPt9 S5ing7XFzqlXPIUNsFv5QiIAiqLl7ZXnWLbrO5pr+sAZhiw+kSVmg45fLhHUTpmkqfbJ pqmUli8Bo7Ii0zSKJZLjaur9267exH7cxorljq070Z31zk9GjsLGLEz5gulMdQqf98zC CbmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pe1O1Pat; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o65si15746ybo.428.2020.07.03.10.10.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:10:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pe1O1Pat; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPCx-0006EX-ST for patch@linaro.org; Fri, 03 Jul 2020 13:10:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxY-0005dT-69 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:44 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:50494) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxW-0005oA-DF for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:43 -0400 Received: by mail-wm1-x343.google.com with SMTP id l17so32637829wmj.0 for ; Fri, 03 Jul 2020 09:54:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ojDJUB2Dp/Uy9824bM0ku4i9qeSH5AqC6BZl5G2EuJg=; b=Pe1O1PattLH7Gsauc4CIpc9YMymi1HxniEKAnfmTlLgOOAsR2uj9/3hOlGVpw9YNkt bLLVr4H9AEAbkGNer19+fFJxZHanVVlWZaQwAKyhbldAa/kikktt4xjx+MGTuh1CGqh0 Drku7oHN4fD4LQgXLzD77wvWTJYg76676ZjQLhixACqLq2biUrKDcHmtNwVX/XrmxfpO auJ8ikOWumfoW0vmqI9JeLzusKon+OHLOLLcvyAllV6KMgUHlS5Z2INmfJUeawEnkS46 9T7GMVXpDGXG1a9drLaEDZ7iZmpViuIwEbAbTEe9TPr+JrPqnuX5bt2BJmOmeYt5F78x wNBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ojDJUB2Dp/Uy9824bM0ku4i9qeSH5AqC6BZl5G2EuJg=; b=FvDAF55vaIRMMx2nbdhKCifc5GUnn9yZGBrck3gW3xJR6l4JEjHvuA4WlVrXzE1qxK k6ig6LjkBqYImxuc6LUMUH3qKGL97vkd0n4y9m4m0pGPfYI9U/5VsCsEgXrzT8FBnXeQ bGzX1XV9L4UvMwtDv62sEI0EsXKAEka6ZKNzxt+/7JgN8uSSATwLjnEnMcR7BnD8rFgE y4ktdmbclHRx7ounR5pQhV+fM/q3L4iZtosMqJ4AsXluwReaBlve7mt9kAKjTL6Mj5W6 NVVWpES1YSTuR8Y6WGAsYE7nqDCBlpChB3EKv/nxvqHAAX6+TopAKr+nfS1ELTHbp6zK KgJQ== X-Gm-Message-State: AOAM533uM4zGO6PNcIRzv7zZGBLN8JYSqNTY176/zRW8/XVjg6INLveR oXPp8j2us9JXQABMR1v+9FWRXSNtEKfkDg== X-Received: by 2002:a7b:cc92:: with SMTP id p18mr38826182wma.4.1593795280747; Fri, 03 Jul 2020 09:54:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/34] hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses Date: Fri, 3 Jul 2020 17:54:00 +0100 Message-Id: <20200703165405.17672-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of logging guest accesses to invalid register offsets in this device using zaurus_printf() (which just prints to stderr), use the usual qemu_log_mask(LOG_GUEST_ERROR,...). Since this was the only use of the zaurus_printf() macro outside spitz.c, we can move the definition of that macro from sharpsl.h to spitz.c. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-14-peter.maydell@linaro.org --- include/hw/arm/sharpsl.h | 3 --- hw/arm/spitz.c | 3 +++ hw/gpio/zaurus.c | 12 +++++++----- 3 files changed, 10 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h index 89e168fbff3..e986b28c527 100644 --- a/include/hw/arm/sharpsl.h +++ b/include/hw/arm/sharpsl.h @@ -9,9 +9,6 @@ #include "exec/hwaddr.h" -#define zaurus_printf(format, ...) \ - fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) - /* zaurus.c */ #define SL_PXA_PARAM_BASE 0xa0000a00 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index bab9968ccee..6eb46869157 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -62,6 +62,9 @@ typedef struct { #define SPITZ_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE) +#define zaurus_printf(format, ...) \ + fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) + #undef REG_FMT #define REG_FMT "0x%02lx" diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c index 9a12c683420..258e9264930 100644 --- a/hw/gpio/zaurus.c +++ b/hw/gpio/zaurus.c @@ -22,9 +22,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/module.h" - -#undef REG_FMT -#define REG_FMT "0x%02lx" +#include "qemu/log.h" /* SCOOP devices */ @@ -104,7 +102,9 @@ static uint64_t scoop_read(void *opaque, hwaddr addr, case SCOOP_GPRR: return s->gpio_level; default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } return 0; @@ -150,7 +150,9 @@ static void scoop_write(void *opaque, hwaddr addr, scoop_gpio_handler_update(s); break; default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } } From patchwork Fri Jul 3 16:54:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231293 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2573554ilg; Fri, 3 Jul 2020 10:12:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYtguAzt8pnvgStg25S4Jp7x0bfNmbEeDRmDdWxbrZVJ7T036l67qBcvVGRGWMo/OPNrTy X-Received: by 2002:a5b:886:: with SMTP id e6mr58894576ybq.318.1593796361816; Fri, 03 Jul 2020 10:12:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796361; cv=none; d=google.com; s=arc-20160816; b=OQJkJrtEJzoZskGsYNYcLLKjayc5PU0jhoRVEn0/s7OOhJveCGZCii8V+jWrwTU/YL /dYJNlYBiyfRn+EWXxHjHrHv21iva9mP1P1hsneGODaMFDjjSCvnjGY3Bm9PtMt0s7cb hhDOItZ7s8S5mvYFNkk0nSQ1HBuNSWKDsBDKl+5ae0sxq3Yr/8Cfjm8wMZ7i8xRbAbO9 Q2Brmjv/0DAD+sXLiXO1CSkiJ6Se5CO8TBq6+dUWmSgh8hnndoV4xBWCykM67XE2LdyC 4ybDhZxgZYoBQ3oBHlyVzxcYyUlo1SYnnIPp3aVFJjXv5Wrr4t/iot2czS/wAGDUHAi2 qcuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6xyMO6sPhGUDnxlfSoi6DiHjZATj8PW0iRsXQiCCoSA=; b=hEecmt2u+Z+uKgHkrySdufzmLaEwz6zitlxJRhios1KMd/dgRceJIdmeMRP/5qbYef WOcXNC0pQvuW8XuaT5CCmzRNsvPmWDn+zwiPqkTRjrMKSOOL1AlD8EOL5lWPX7pGZ7Z4 AUqeyd+EwatiTiZtiCs2MVACA7D6PFg4WQXnIb2+AbnRC+MKMzhNmJxiWOJIQx3w5Esc h+EBQ0XyqeGJAUWVFT1YEleqaasGtlmd4U6yJj8GjfvME5fuEAsN/Ye90ZTAHTkaWTEC r7I7fEk2MuvqptPjsbUcot26dOctYRCSzJt2YeiLtbqJfmYgFW09lMVMLx2qWDwNd7zP iufw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MQcTXF+L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f13si11876560ybp.87.2020.07.03.10.12.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:12:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MQcTXF+L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPEt-0001J1-W7 for patch@linaro.org; Fri, 03 Jul 2020 13:12:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxZ-0005fn-4Y for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:45 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:36002) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxX-0005oX-Ga for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:44 -0400 Received: by mail-wm1-x342.google.com with SMTP id 17so34699455wmo.1 for ; Fri, 03 Jul 2020 09:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6xyMO6sPhGUDnxlfSoi6DiHjZATj8PW0iRsXQiCCoSA=; b=MQcTXF+LbtqVm2mbdYE+UIEqgtEldL599kPMzeRlZdPPU+uRjIzhhVJj7SJuJPF/Tk rBJC7qO96ZAFioGz38YuKP4fQt90wcUxxhap4z05s/8ym+q+zQKeukgSdOTYil6cgOOq v0Ly46GxRotdtPRbhehAX7/OLRgaJjSh/iw69HsP5j4tw+fb+PHC4BNE1ZRXSN2WFroL vkVDjWLceD7lH1s9pRsic/lHvNB1kJruZF7+uxQ1/ZSdQWEkFTcy149wWNQl4XZNQZXM CINkv4OVfGx1Y3an6xqnLqbkQQHHewBL7S3oeLYHPSm48s5aInRp3WtLMZlWbVWmrQLl aShw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6xyMO6sPhGUDnxlfSoi6DiHjZATj8PW0iRsXQiCCoSA=; b=j55VbzjypJSxkGPCzS1UvQjX+pQtCrkjMLlILfnTV07Bek0MScV9FiYxfI6KIgzjMJ DKFBA2uZQpeSbwb29SgxL0gqdUQotDwYTpFsWGlsOfuhQA75XAI+3D4XpSKdt+jUUDlx zugeobpse2qZBJh+OvbBoUDVdvXiJCsmhZLrSY6qe/IOTWObMJIAhuUSeV4lOkG2n++9 K/CyonyEhswqkzzcuNJ4AOjuhnHdZOelNO9wpWImABlrDwQLiECcmlBE6CKWK9ypKq8D 7MWWyFiRTpgqHIyyra6LCozEXhTaJAZkMh1MzcD8MBratHMZhz5ZHRA91/B6kp/AP9At tSVA== X-Gm-Message-State: AOAM531KfpAvLUwl2hTX3TyeyVW4SslBwiA7p8Fa7fH+iEXvFo9A+zQk r8Kvwha/14ywfsd9Q52PG0srKQvjZgBPuQ== X-Received: by 2002:a05:600c:d5:: with SMTP id u21mr36601868wmm.156.1593795281903; Fri, 03 Jul 2020 09:54:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/34] hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses Date: Fri, 3 Jul 2020 17:54:01 +0100 Message-Id: <20200703165405.17672-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of logging guest accesses to invalid register offsets in the Spitz flash device with zaurus_printf() (which just prints to stderr), use the usual qemu_log_mask(LOG_GUEST_ERROR,...). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-15-peter.maydell@linaro.org --- hw/arm/spitz.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 6eb46869157..49eae3fce4e 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -23,6 +23,7 @@ #include "hw/ssi/ssi.h" #include "hw/block/flash.h" #include "qemu/timer.h" +#include "qemu/log.h" #include "hw/arm/sharpsl.h" #include "ui/console.h" #include "hw/audio/wm8750.h" @@ -65,9 +66,6 @@ typedef struct { #define zaurus_printf(format, ...) \ fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) -#undef REG_FMT -#define REG_FMT "0x%02lx" - /* Spitz Flash */ #define FLASH_BASE 0x0c000000 #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ @@ -137,7 +135,9 @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size) return ecc_digest(&s->ecc, nand_getio(s->nand)); default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } return 0; } @@ -168,7 +168,9 @@ static void sl_write(void *opaque, hwaddr addr, break; default: - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); + qemu_log_mask(LOG_GUEST_ERROR, + "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n", + addr); } } From patchwork Fri Jul 3 16:54:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231250 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2570690ilg; Fri, 3 Jul 2020 10:09:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwLfOSm+GvHV2RizEjzMBaX5FNyL4foYYsBbeOMntHJHZRq6bL4oHRxPs3v6UM3J/kf3z9A X-Received: by 2002:a25:bb0b:: with SMTP id z11mr41956320ybg.235.1593796141401; Fri, 03 Jul 2020 10:09:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796141; cv=none; d=google.com; s=arc-20160816; b=wyqltBZxeYawhC88xvrx7NqU/FUj7lcui0/vjmYiRApt6y+n2BdzbE8AgeOgrYQA7P 0M9bCJsU8gq+kxUKXsolN9V7vTFPMoVTW0qMtoVqFrdhviADlAwQ1jOzh5zt6EZpyIdr eaPv50hDPKmpqFBOvzE27AagCgbwfVdeUTfeNyzp5e4ZwKwSLmnqwXJKFhLI7wLpXR87 RqADsI8wTRtky5mv95f5a5jDD5yYvJLbcGvCq2R0ApJ6Kg1bNvkpKmod9hyhukD5p/u2 JwxDqS5a7nmwRyUpHyr0U2qLaW6+IvNCuVjrb9t7xxSuj0wgNsx/M0IDOlkh58SWPxfd 6TEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VKvp3GygN6NnSayidALafcM4t4tV8T/cgZll1mJohvM=; b=z7H94eXl4cmR+IuQy0hgsLbg2WiKrSDiYeSDmaq3UhWCU6iJRyO2oJm2ep0a3iQENk 8HQQg/3NTQpdKi6uD3zCOblqCrKbhHP1dL6QRyboSaRYYYh0exXQ0DJleC1mhWQZIHEy mOjOT46f0HgqlPu+vOq411lEkjwohIpvHFOV0zllsDuqW91IdNJVEQ1M0xiGzBdkxRfG N5iPd9KE8KWSrZRejZ7bMbA99//HvarLr2ktoT8ZjteY4rsDJNRQ+1CEAJbnQXa4F69w Af1uUd5WGW4qrSk67TW+aDZ7UfhcNATujYxo34iSpF3DGMb3nzjBnqjSr19V5e9gW36J aeKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NTyIN0ns; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c204si224505ybb.467.2020.07.03.10.09.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:09:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NTyIN0ns; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPBM-0003Yg-P0 for patch@linaro.org; Fri, 03 Jul 2020 13:09:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxe-0005sj-BG for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:50 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:45169) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxY-0005oj-GB for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:49 -0400 Received: by mail-wr1-x441.google.com with SMTP id s10so33384355wrw.12 for ; Fri, 03 Jul 2020 09:54:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VKvp3GygN6NnSayidALafcM4t4tV8T/cgZll1mJohvM=; b=NTyIN0ns1+eSMr4oOtscO/0nnHqmiA0KUWOeizBulFcWpsQt5nYQqVzqo9Uew0KkTR 5zdNGPKcvfod5SVYumuQ+mXtJTkIw7u6wqMw+yDbFhQq9aBpQsEpWeXb+2hj5aVJO2Di iikeml2zfcSflRtTZMs87NOSmDLwfzddKok0lFsLp3xKmdCM8NygtJvLbjXSeD6kHtc7 PP+1OvnER8vn0EX2eEmf6DhF2fr72mtrR2T8stgTT7w0yf+MnQrP5Oaip1YNuvL19ugE D3OR3PXrFeswP60q5wCLXAAj98FbyXqprDaWN5cW69/8enBCHEVLBmIAD7Nc33ojGKjm 16gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VKvp3GygN6NnSayidALafcM4t4tV8T/cgZll1mJohvM=; b=tyUrsYfLxDyWt8p4uTnA8PbzSKb2jMgJeg4m4cnDZDYeEsLxgjweX1Omvs+0faOqkp exPGIQevzdo9f3nRhaq2hE27/wirD1RzbPYGywaCXoq0owXLmQjFOTz1+F8lLVAsrsWc +CBgwFUrXe8iefF+jwVx4SuEmClsG5SDccDFYy3ZTU4lyoRBlLduTLtDEtCM2e+WjqY8 9qq6Cy70wGnjpFz9UJ7dOMeX5fCeUPe6lDt7W40vFSC+n3L1iM5xi1avsWTRW+adxY47 dpsAoE5qkEnFEtPy2lx2qUP1uyPXXIpiNdeaVdoVBGt2u3xe/8pbIA032oHuoRToHj2f eQMQ== X-Gm-Message-State: AOAM531/EQeRoiaVg4ud760/yXRNnTJRr3KAfZcBOyCVOFP27iLVJsAl v99Gvv6qDCH4c0eGRfmQ79ARjBXH6Zqc3A== X-Received: by 2002:a5d:68c7:: with SMTP id p7mr39704358wrw.16.1593795282877; Fri, 03 Jul 2020 09:54:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/34] hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses Date: Fri, 3 Jul 2020 17:54:02 +0100 Message-Id: <20200703165405.17672-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of using printf() for logging guest accesses to invalid register offsets in the pxa2xx PIC device, use the usual qemu_log_mask(LOG_GUEST_ERROR,...). This was the only user of the REG_FMT macro in pxa.h, so we can remove that. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-16-peter.maydell@linaro.org --- include/hw/arm/pxa.h | 1 - hw/arm/pxa2xx_pic.c | 9 +++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index f6dfb5c0cf0..8843e5f9107 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -184,7 +184,6 @@ struct PXA2xxI2SState { }; # define PA_FMT "0x%08lx" -# define REG_FMT "0x" TARGET_FMT_plx PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, const char *revision); diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 105c5e63f2f..ceee6aa48db 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -11,6 +11,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/arm/pxa.h" #include "hw/sysbus.h" @@ -166,7 +167,9 @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset, case ICHP: /* Highest Priority register */ return pxa2xx_pic_highest(s); default: - printf("%s: Bad register offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx + "\n", offset); return 0; } } @@ -199,7 +202,9 @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset, s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; break; default: - printf("%s: Bad register offset " REG_FMT "\n", __func__, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pxa2xx_pic_mem_write: bad register offset 0x%" + HWADDR_PRIx "\n", offset); return; } pxa2xx_pic_update(opaque); From patchwork Fri Jul 3 16:54:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231295 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2575078ilg; Fri, 3 Jul 2020 10:14:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyY2bEuP6V3Gf6jYGQMMPbiLjBeRt7uwK56em6sMWO/WZ/AKMnGhndOzEWRNSFQ7wOhDToX X-Received: by 2002:a05:6902:1002:: with SMTP id w2mr12992321ybt.321.1593796488887; Fri, 03 Jul 2020 10:14:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796488; cv=none; d=google.com; s=arc-20160816; b=Sxh+3pDtP7Rpel3gfOgoVC0RKlkfHi3J9LgLERzmQH3b5AxvHvECPx55qXMXVAebqA YAQsmNUC+9ZToQ4II3aIsRZ28KILjBE45pgfswmTCnOmUNhwP3nTVLhZRpgGEkZnxcQe n5IPKBkzniLUFcuhKGJbQFAVbuCP26ZsjSy6Djaz1ajJf3e8UkOI83ekF5Nk2BSvJqDb w6kHDiCGekjHXugwYbm0zXB2IdY6OJFv2fn5pE1blzszz/GC92CnOUHQH5By4XNp6vxi HYwbqW3XBinDdr6QKHVhAkDSXuKgRIssx+lIe5oFCNu2w5LbMPlxLh1pGHkPkcHBOIRc +oEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WcP1RS8FiMepwE14qHYBXQBJblwCXUsUHB2p+oUgg94=; b=gx4ZAhn/HNG8PeYgRzA2UErGdz90LqgnKEkZbMtuSuGmu3miWaKUokABrdUmolSypB 8HpgjArBqNgvj+NSg5XX16HaxfuXHL2XCo9GeI2ZHTAsxKjXfO32LEKRUrlvY9NnL7zo Ftt+WWX3VvQD6Wa8VFX/TuRAIm1GjM4H4JyW4hRWV3QJJQMzQu0+8zOqT6FjyZLiFLSo D1uLJxfTH7UtVRCzcrQ3v9VlLRLnxCHSMGR9hbVW2OhmPCvpTyZgoioHqdSr7fiQ5kyY TrDc5bYPK/48/bm2RSsMmPs2nRc4uDuPWdGTHZWGDJCA7e5EuXxT9rSE4IsyLF4Nit7m YdqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mLx+J7MR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r66si2196373ybf.291.2020.07.03.10.14.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:14:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mLx+J7MR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPGy-0005Av-A7 for patch@linaro.org; Fri, 03 Jul 2020 13:14:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxb-0005mc-Q2 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:47 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45170) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxZ-0005pG-Mj for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:47 -0400 Received: by mail-wr1-x442.google.com with SMTP id s10so33384422wrw.12 for ; Fri, 03 Jul 2020 09:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WcP1RS8FiMepwE14qHYBXQBJblwCXUsUHB2p+oUgg94=; b=mLx+J7MRoxJqk0y/+oZmAvjX8UEmqG+RNxnxmpl90p6GLXLpuXqGz8Y/e+ma5PwTpo xgkRHTa3oxMb2at6UhpdTed+wc7kotvIH4vN3PAH4110Mw2BTPk6itORabWN7QC18bAz BeJR9mP0GLICYpJETdZcuwK/UjAVFYwLqReFlBjf0U4Y9grnUk3UJ3hUIoLAQz0+FNJz I4XbwyrV1G6f64iLYmoXvoac+Ayxk+yI4ATVHqUkcNKXu1niWQi3D7eMhNkhn57+jfHm ciZGo0M0tFt88+dZNsYbVnMQFxWeGy/mFLjiNm3BZjcFaAvc8m9R8IxdguS1g7wQ8+J6 OUpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WcP1RS8FiMepwE14qHYBXQBJblwCXUsUHB2p+oUgg94=; b=OyCghysgPg9TYmauusVHji9ttxLzQ5H9AcFzMRewqFwRobhPTOWBsi7mKihWh7I6Au 0TH5nFGjk/kPOnoMRm9T/I63F89i9O7by+bRJzA+S3PEWlW0+8BeYjseisW14MSOwn5U I2pvteiVcmzTJYjSFNXXufoHeY4PQ7RR+LrPm3yhQb0Rv5PtaH5vsBP4kEgBXdpoPj30 M+8+dmJ4jkBkHZ0Zw/o9vGTv57S4iKMVaEVn9lJ3qIm6UxPyIsTZSU1AvN+GL8TroMiZ 7szfFcYXNvHXK/A+enXEvjD0Xun4NsxEILp5q7LUja+myfNmGrA3bIxYX7LBa+nOaKB5 gKig== X-Gm-Message-State: AOAM530DHYU4j1KoiUgGT9u8906qKXMBamP9MW3WLgF8Gj8sSQrCqg4q 12ToY71f4Qbrrj6HiIIbYzySeSVf6QTniA== X-Received: by 2002:a5d:4e81:: with SMTP id e1mr35718004wru.22.1593795284102; Fri, 03 Jul 2020 09:54:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/34] hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg Date: Fri, 3 Jul 2020 17:54:03 +0100 Message-Id: <20200703165405.17672-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the usual QOM TYPE and casting macros; provide and use them. In particular, we can safely use the QOM cast macros instead of FROM_SSI_SLAVE() because in both cases the 'ssidev' field of the instance state struct is the first field in it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-17-peter.maydell@linaro.org --- hw/arm/spitz.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 49eae3fce4e..f020aff9747 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -579,6 +579,9 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp) #define LCDTG_PICTRL 0x06 #define LCDTG_POLCTRL 0x07 +#define TYPE_SPITZ_LCDTG "spitz-lcdtg" +#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG) + typedef struct { SSISlave ssidev; uint32_t bl_intensity; @@ -616,7 +619,7 @@ static inline void spitz_bl_power(void *opaque, int line, int level) static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) { - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); + SpitzLCDTG *s = SPITZ_LCDTG(dev); int addr; addr = value >> 5; value &= 0x1f; @@ -645,7 +648,7 @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) { - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi); + SpitzLCDTG *s = SPITZ_LCDTG(ssi); DeviceState *dev = DEVICE(s); s->bl_power = 0; @@ -664,6 +667,9 @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) #define SPITZ_GPIO_MAX1111_CS 20 #define SPITZ_GPIO_TP_INT 11 +#define TYPE_CORGI_SSP "corgi-ssp" +#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP) + /* "Demux" the signal based on current chipselect */ typedef struct { SSISlave ssidev; @@ -673,7 +679,7 @@ typedef struct { static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value) { - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); + CorgiSSPState *s = CORGI_SSP(dev); int i; for (i = 0; i < 3; i++) { @@ -702,7 +708,7 @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) static void corgi_ssp_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d); + CorgiSSPState *s = CORGI_SSP(d); qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3); s->bus[0] = ssi_create_bus(dev, "ssi0"); @@ -714,10 +720,11 @@ static void spitz_ssp_attach(SpitzMachineState *sms) { void *bus; - sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); + sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], + TYPE_CORGI_SSP); bus = qdev_get_child_bus(sms->mux, "ssi0"); - sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg"); + sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG); bus = qdev_get_child_bus(sms->mux, "ssi1"); sms->ads7846 = ssi_create_slave(bus, "ads7846"); @@ -1220,7 +1227,7 @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data) } static const TypeInfo corgi_ssp_info = { - .name = "corgi-ssp", + .name = TYPE_CORGI_SSP, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(CorgiSSPState), .class_init = corgi_ssp_class_init, @@ -1249,7 +1256,7 @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data) } static const TypeInfo spitz_lcdtg_info = { - .name = "spitz-lcdtg", + .name = TYPE_SPITZ_LCDTG, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(SpitzLCDTG), .class_init = spitz_lcdtg_class_init, From patchwork Fri Jul 3 16:54:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231247 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2569026ilg; Fri, 3 Jul 2020 10:06:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyD1qyRWs7mkatgyFnKB3P6HtzBH+NvVY3Iyl/aBmFxQp8rIT/hOMrIXK71lEGTLxdOYT1a X-Received: by 2002:a25:80cd:: with SMTP id c13mr5050612ybm.253.1593796019581; Fri, 03 Jul 2020 10:06:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796019; cv=none; d=google.com; s=arc-20160816; b=E4sGI9WFaMRtE4xapfA6edmNJXzlw3OUDzCi6AWSbWrMkMuSIWcDTgvHXYixtToZPT peyMh58kJSmlF9bMw+wS5Ai1UzKH3H0PSCgjrJLXaiCV+5tJEtc6/7o6frRLPdifoh6S Pzt6SJPraC1WdfH5Swn3cIa1q1e3YJZ6kJfhraTTafzS0orqVvdXNlwkIgltuWqWUyGd v4EcVr4ZCLdH679jPaf4ltbZJ04mdcpHwzXllKsyNt7/Kcp6kNivWKX7PH6LP49Wcg+i rugIidlabn626vTroZTyNEB/H/wjYIFKFiVWnOyEG4XbqxFBCS+GwuCUJzpGZnIX3L1f p2wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZnUx+Lf8ZiVdRHH6uu3Dh0HB/bmYuGZE+e5cPCXeTxE=; b=a+MyBOBH5hunJkHqjM99OUYooFHRoTQcxWzO4olA9kf+TtUcmUhhSQt/koHYHMzG1D p9c92xffDE+KYVddG8iFFPLGC3ySVROu9hBgewGC1mxH4t1FZ5qSeMUCxbj0q78ktpSJ 4hrf1p7X+nJ4yI1dQcZEb1YIOdJP80PQDWJEDa1dG1/v3AIoa6eWHa0LLZMQQiBKFawc nps0dDiJOKf0pcpQHA3UTj80taSzZRqoH8v0jbJv3zcuJNzNSg4WX8Hm9z9df6V26MwU cPjJAa7jc2tNhILV7WuxRD/oJqeiXnrIAIHGv+i3TTixiGujaJiidEax1uuwGPbp6pCp wF3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ipLWrrcj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f13si11865460ybp.87.2020.07.03.10.06.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:06:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ipLWrrcj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrP9O-0008W2-TV for patch@linaro.org; Fri, 03 Jul 2020 13:06:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxd-0005pY-4Q for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:49 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:33464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxb-0005pg-4H for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:48 -0400 Received: by mail-wm1-x32e.google.com with SMTP id a6so22699340wmm.0 for ; Fri, 03 Jul 2020 09:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZnUx+Lf8ZiVdRHH6uu3Dh0HB/bmYuGZE+e5cPCXeTxE=; b=ipLWrrcjsS2vt1Y/nl/5cL3rULFm0TgLBGQGMqVtlI7q9dOssSDzTvZFKNx+Hi/zHZ L2f8YQT4TD2Rr1274Kh3QSlrmZWlPf8F+3UpIJMiuyl6zA/iFkPkDTKkrrciuxmmsAfH FfuXxhqPoLVA83R3GZauf5YAG78F3+R7Tx0WRXfvWVJSMYu/a9MeO2m5K1f9k2u+Q14C bp/hfGGeTrdC20KiVCU4n33Wz/FGKMj5g2xuKvFrGzduSW1Pkk9eFez+XNugcF7SkEdm P9JtIceZD7vMwCHuuuhw7NHnRBCkpzLBTmN3/xZz3nq/l8lJaf0UVUq5B2LUtZFceGM6 rl+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZnUx+Lf8ZiVdRHH6uu3Dh0HB/bmYuGZE+e5cPCXeTxE=; b=JMbFbEd30dbFtEK/3XcbPCm0xF+Up0dXcj+U+fiaIxRZZmGRrsi14Buak3sxkB0KMT 2KZ8G+cRHnFrcy+DPGw7Djnk76v6wurVP1GDpO/P8B80wYL296Pa2ZwNVL/iaMx+vdz5 2taTL8ErBUgLCGiuOqvhsHG9QltLxnDv/2JwHEEVeIVVDAgOHyf116QwsuadMpKis85T RIWymeUtBDtDdVa7gmladlQJ0eZZp1ZnVnB45FLcpxbDvWsdCVUJsv5ykXbSa+35WU34 jZ1sFPRWGwUG7Ckh6DtCjqcjdNztP67GeBGQMxVzu7a6p7f6LfFhhnEpK3SIgfrv0pTr 0bqA== X-Gm-Message-State: AOAM531HX9e+FF9Uw3zuQqWMiNUtNni3+3/fqfRG7X+Lc9tdsRaM9R+p 08zIVpkRZMqPBXvmn4rFh4wpkkG6GzYj0Q== X-Received: by 2002:a05:600c:204d:: with SMTP id p13mr37306929wmg.88.1593795285377; Fri, 03 Jul 2020 09:54:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/34] Replace uses of FROM_SSI_SLAVE() macro with QOM casts Date: Fri, 3 Jul 2020 17:54:04 +0100 Message-Id: <20200703165405.17672-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way to cast from an SSISlave* to the instance struct of a subtype of TYPE_SSI_SLAVE. Switch to using the QOM cast macros instead, which have the same effect (by writing the QOM macros if the types were previously missing them.) (The FROM_SSI_SLAVE() macro allows the SSISlave member of the subtype's struct to be anywhere as long as it is named "ssidev", whereas a QOM cast macro insists that it is the first thing in the subtype's struct. This is true for all the types we convert here.) This removes all the uses of FROM_SSI_SLAVE() so we can delete the definition. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20200628142429.17111-18-peter.maydell@linaro.org --- include/hw/ssi/ssi.h | 2 -- hw/arm/z2.c | 11 +++++++---- hw/display/ads7846.c | 9 ++++++--- hw/display/ssd0323.c | 10 +++++++--- hw/sd/ssi-sd.c | 4 ++-- 5 files changed, 22 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 5fd411f2e4e..eac168aa1db 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -66,8 +66,6 @@ struct SSISlave { bool cs; }; -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) - extern const VMStateDescription vmstate_ssi_slave; #define VMSTATE_SSI_SLAVE(_field, _state) { \ diff --git a/hw/arm/z2.c b/hw/arm/z2.c index a0f40959904..e1f22f58681 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -111,9 +111,12 @@ typedef struct { int pos; } ZipitLCD; +#define TYPE_ZIPIT_LCD "zipit-lcd" +#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD) + static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value) { - ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev); + ZipitLCD *z = ZIPIT_LCD(dev); uint16_t val; if (z->selected) { z->buf[z->pos] = value & 0xff; @@ -153,7 +156,7 @@ static void z2_lcd_cs(void *opaque, int line, int level) static void zipit_lcd_realize(SSISlave *dev, Error **errp) { - ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev); + ZipitLCD *z = ZIPIT_LCD(dev); z->selected = 0; z->enabled = 0; z->pos = 0; @@ -185,7 +188,7 @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data) } static const TypeInfo zipit_lcd_info = { - .name = "zipit-lcd", + .name = TYPE_ZIPIT_LCD, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(ZipitLCD), .class_init = zipit_lcd_class_init, @@ -325,7 +328,7 @@ static void z2_init(MachineState *machine) type_register_static(&zipit_lcd_info); type_register_static(&aer915_info); - z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd"); + z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD); bus = pxa2xx_i2c_bus(mpu->i2c[0]); i2c_create_slave(bus, TYPE_AER915, 0x55); wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b); diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c index 9228b40b1af..56bf82fe079 100644 --- a/hw/display/ads7846.c +++ b/hw/display/ads7846.c @@ -29,6 +29,9 @@ typedef struct { int output; } ADS7846State; +#define TYPE_ADS7846 "ads7846" +#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846) + /* Control-byte bitfields */ #define CB_PD0 (1 << 0) #define CB_PD1 (1 << 1) @@ -61,7 +64,7 @@ static void ads7846_int_update(ADS7846State *s) static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value) { - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev); + ADS7846State *s = ADS7846(dev); switch (s->cycle ++) { case 0: @@ -139,7 +142,7 @@ static const VMStateDescription vmstate_ads7846 = { static void ads7846_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d); + ADS7846State *s = ADS7846(d); qdev_init_gpio_out(dev, &s->interrupt, 1); @@ -166,7 +169,7 @@ static void ads7846_class_init(ObjectClass *klass, void *data) } static const TypeInfo ads7846_info = { - .name = "ads7846", + .name = TYPE_ADS7846, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(ADS7846State), .class_init = ads7846_class_init, diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index c3bdb18742c..32d27f008ae 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -66,9 +66,13 @@ typedef struct { uint8_t framebuffer[128 * 80 / 2]; } ssd0323_state; +#define TYPE_SSD0323 "ssd0323" +#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323) + + static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data) { - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev); + ssd0323_state *s = SSD0323(dev); switch (s->mode) { case SSD0323_DATA: @@ -346,7 +350,7 @@ static const GraphicHwOps ssd0323_ops = { static void ssd0323_realize(SSISlave *d, Error **errp) { DeviceState *dev = DEVICE(d); - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d); + ssd0323_state *s = SSD0323(d); s->col_end = 63; s->row_end = 79; @@ -368,7 +372,7 @@ static void ssd0323_class_init(ObjectClass *klass, void *data) } static const TypeInfo ssd0323_info = { - .name = "ssd0323", + .name = TYPE_SSD0323, .parent = TYPE_SSI_SLAVE, .instance_size = sizeof(ssd0323_state), .class_init = ssd0323_class_init, diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 25cec2ddeaa..25cdf4c966d 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -74,7 +74,7 @@ typedef struct { static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val) { - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev); + ssi_sd_state *s = SSI_SD(dev); /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */ if (s->mode == SSI_SD_DATA_READ && val == 0x4d) { @@ -241,7 +241,7 @@ static const VMStateDescription vmstate_ssi_sd = { static void ssi_sd_realize(SSISlave *d, Error **errp) { - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d); + ssi_sd_state *s = SSI_SD(d); DeviceState *carddev; DriveInfo *dinfo; Error *err = NULL; From patchwork Fri Jul 3 16:54:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 231298 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2576676ilg; Fri, 3 Jul 2020 10:16:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOAVIK7Ri7lRfbuQLW29yEHg1d0Miyyp0gGjlnaRYo+VNocyggaQ4yefxB1c4Nb/uh19ua X-Received: by 2002:a25:a122:: with SMTP id z31mr44336ybh.311.1593796618243; Fri, 03 Jul 2020 10:16:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593796618; cv=none; d=google.com; s=arc-20160816; b=m5CUfzIAxj74Z3gIpjw/lK/doK94m+1esJvKylkjIRTa97mPFp2b+gSYGU9GycQqdD PDYa+Mtdim0NnftplUK7oYnOsKdGKvNQxC8yXPldXHVRCIQrKHGd3XiWFMRnXfh/QXYw g/z0GH6JtlaB+/CihsD7h8Qyu5lRYAX6KzywiOuOCa/5pDbb6R7IBTZLTk745idXe1dk ZkjFXExJfbH+HWrkEHxKsKEA3r/3lpV8ZYalHcRYpUz4lebMqSBU4rpMaz6wv8/nYYBu hojddERRM3BMEpifwN1pjULs35fbyquflgXMXNlhvpREfuw2qu1GUEHScrnhk6jnUUN6 kxZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=luKuvfhrZOGh/JqYuKRFnEkYbiDld7fNdcxPvlNM2+o=; b=N7BrZyIyhz8vKjAu5v0fHWQp4cXiemecmTeEVrPUkyT0VBkA8XGjjYO8xdCnfq7Hhd lugEnokDYPhARpqUKrgL1kY2uoM/xlqJR+ucawyVILru6plCyepqIBUd6K6rdCkkMrSX Q7mvnCuT8yYeB4+gxuh6bOKxOp45OlGuTNbmGzIJio/JKcIw5SGXP7EijadLfMDIq5Po tH1iFl9xA2PbhKJs8WFjNpCzG73itb6unD7kwJ2alUIx8HM7J/QKiyUlpKap9+d8Yv/f Kx9LHsYGIytonzzB21P+VI8rwcuL/GV8SmvEBR+6ngFucE8maKz2jxnGXjoXZyecyIcr tc5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KfFU1PT8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w10si14754384ybt.261.2020.07.03.10.16.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Jul 2020 10:16:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KfFU1PT8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrPJ3-0007dJ-Lv for patch@linaro.org; Fri, 03 Jul 2020 13:16:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrOxd-0005qr-HR for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:49 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:41081) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jrOxb-0005px-T7 for qemu-devel@nongnu.org; Fri, 03 Jul 2020 12:54:49 -0400 Received: by mail-wr1-x42d.google.com with SMTP id z15so22145677wrl.8 for ; Fri, 03 Jul 2020 09:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=luKuvfhrZOGh/JqYuKRFnEkYbiDld7fNdcxPvlNM2+o=; b=KfFU1PT88rojyerKlPjDqbXpYIAMdqIf18WjQu5A9jR4K3DMgi+40a/yEijmRscYoZ xZEvl3UwoMqNwK6nkDWurZCDuXSXHgoAaj+H7pjunCuh1iapt7PwXrxTsoydHtyvHtpB 0Z+bBUY18+LowfTens+nlR7angCd9g8aGzw1lLQ0zikzGIwZ3Ps1v6C/DKuYEXGzjMIE k4pueW68Hxgfj1d4iRLhEroDhAMQHtljvE1azU5w6EdLHmX0ClQlBuIjKKggIpblAx8+ aEkGF/uQDHXPLJlFXGgfmpAW4W/9pNxeLHBp1YGxxOU57V9FWN+EPRfesNk4lau3vNKt Shxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=luKuvfhrZOGh/JqYuKRFnEkYbiDld7fNdcxPvlNM2+o=; b=t1T7p8rxESHYyIc3lfsy2e2FGgKJy3gLnRHVLc9UDoT9nLGHfGqis/oxnQRVNrK2Tr dg8l0GbKxfy7JxMpvu6dnFxC/FBWdxqNLvlb05DOpC9oXKcZh6B35SVMDZUjpxJolF9y aVuBGL1QirX2mDdaPIO58i54cPbwEEHC/BWlB/M8aNwyqltkBgzt2sjmmo6JX84LZdrw ocrRtzn3tcNjXBXv0qVuK8wvKOhTxLksBeFmM/3pPnvflWmAE6m8GMngQkGD4jJGcM8j UahVJhzGh/pfq27mj4pcwndqBDG0cHC/zBxNbqoyGLrEYFgQ9SxQP3uwOQBJkmYAXZ/V NSkg== X-Gm-Message-State: AOAM533tGZEMtv35DQ+D+1L2W7CQMguHeO27A2PX6CKzjnn4oiQmNOAx nbjyn/4Q+f8b7xWJ7cGO/7m7oEAveCtL1Q== X-Received: by 2002:adf:fa8b:: with SMTP id h11mr37685451wrr.391.1593795286336; Fri, 03 Jul 2020 09:54:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm5574224wrx.69.2020.07.03.09.54.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 09:54:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/34] Deprecate TileGX port Date: Fri, 3 Jul 2020 17:54:05 +0100 Message-Id: <20200703165405.17672-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200703165405.17672-1-peter.maydell@linaro.org> References: <20200703165405.17672-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Deprecate our TileGX target support: * we have no active maintainer for it * it has had essentially no contributions (other than tree-wide cleanups and similar) since it was first added * the Linux kernel dropped support in 2018, as has glibc Note the deprecation in the manual, but don't try to print a warning when QEMU runs -- printing unsuppressable messages is more obtrusive for linux-user mode than it would be for system-emulation mode, and it doesn't seem worth trying to invent a new suppressible-error system for linux-user just for this. Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-id: 20200619154831.26319-1-peter.maydell@linaro.org --- docs/system/deprecated.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.20.1 diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 843ae71fc61..47f84be8e09 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -404,6 +404,17 @@ The above, converted to the current supported format:: json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"} +linux-user mode CPUs +-------------------- + +``tilegx`` CPUs (since 5.1.0) +''''''''''''''''''''''''''''' + +The ``tilegx`` guest CPU support (which was only implemented in +linux-user mode) is deprecated and will be removed in a future version +of QEMU. Support for this CPU was removed from the upstream Linux +kernel in 2018, and has also been dropped from glibc. + Related binaries ----------------