From patchwork Wed Jul 8 09:30:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235049 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp264922ilg; Wed, 8 Jul 2020 02:30:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy0VH3hqXjQJN5V+uSxSu1oWYJTxH4vx1hmN8Bh0k4VxEYKV9+xdLs+L12/muO3jlgrs2YP X-Received: by 2002:a17:906:4c41:: with SMTP id d1mr51414835ejw.463.1594200648323; Wed, 08 Jul 2020 02:30:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200648; cv=none; d=google.com; s=arc-20160816; b=Ibsr8d6lnfI/Am67LSnzme79mOFRMiil8DawwDastsVY/PjUtKiS0SA8KO25z7S/dd DdiK3Ddi63VPNqkl3WEdAdfb6KoS55snmVHIklbMIXWerUbR0i9p5g3ZvbIkaJK6rrLo BGbOTH9lvfcqBWVTL1TxeNVITAsMUGEIz2n8fo8WNopf0J0pl1MnM1g77oiWn+Wn38Ne iHfWngWYLDiCkpJPJy8cSYW7d2pgmpxuw62s0fyz5Vv3X537bokB4zwhZZw5SWbgFZ8e fMnDGcjPe3M7GupQElXw5746rEcvJbFQzkZCQjva2xqsnXA4iKEAbeY4mrSvn031o3vN LlvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4dHzHIcoVceEkhB6z/897N9X5pO/7Q0JzeAzNl+vty8=; b=OZJl3IWF978dbfcxMwPwDjDulrGV81Gee2K8oQyloTgm9x1E2ZrAyYCLpft/075YgX CWjdxnDgrPSGumiI7EX3HneI3aw8JepCUaqyr9JKjSWPDDTUBhgUxYzZmWL4p/Axemon cxE71MwF99gJVXQQFg4xQF+KsZ42Ik/SVlQADzqEogCTB1iiaZetonAt0F74ib7OiZR1 ui2lphfcTxknKppa2kJfqLSEyxLgv9+FBFoKpAur8WIRlbrQ2C9jRZmY8EvGE4Bp9/rO JabaryAjkfnXu3IL6e9Zy/1Q1gj0KhEF9o4RyVvYxc03AJDlhqFQVhT68UVsExnIvF7R Qn9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=i5xk7aO3; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dh2si16863975edb.55.2020.07.08.02.30.48; Wed, 08 Jul 2020 02:30:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=i5xk7aO3; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728259AbgGHJai (ORCPT + 4 others); Wed, 8 Jul 2020 05:30:38 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58102 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726445AbgGHJai (ORCPT ); Wed, 8 Jul 2020 05:30:38 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689UR1S077787; Wed, 8 Jul 2020 04:30:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200627; bh=4dHzHIcoVceEkhB6z/897N9X5pO/7Q0JzeAzNl+vty8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=i5xk7aO3vmlMw/dkzg5yw9/xjnGNb9k1X1+xKyCnfi5nn9IBAusbxRJ47cQlcH8ye 9qAdiPzzVSGW20m9N2Z/qThR8lvnjGr3GvvFDhcJx8HE4ZHgGPAXBxdN4JjyNpbTm1 eq68X6A/Mv++zrey/6SikPU03uczsDKEfIIAJ6vk= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689URdN095307 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:27 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:26 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:26 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEI098512; Wed, 8 Jul 2020 04:30:23 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Date: Wed, 8 Jul 2020 15:00:05 +0530 Message-ID: <20200708093018.28474-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") while refactoring the Cadence PCIe driver to be used as library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup() and cdns_pcie_host_setup() but missed to remove the corresponding pm_runtime_put_sync() in the error path. Fix it here. Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++------- drivers/pci/controller/cadence/pcie-cadence-host.c | 6 +----- 2 files changed, 3 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 1c15c8352125..4a829ccff7d0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include "pcie-cadence.h" @@ -440,8 +439,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops); if (IS_ERR(epc)) { dev_err(dev, "failed to create epc device\n"); - ret = PTR_ERR(epc); - goto err_init; + return PTR_ERR(epc); } epc_set_drvdata(epc, ep); @@ -453,7 +451,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) resource_size(pcie->mem_res), PAGE_SIZE); if (ret < 0) { dev_err(dev, "failed to initialize the memory space\n"); - goto err_init; + return ret; } ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, @@ -472,8 +470,5 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) free_epc_mem: pci_epc_mem_exit(epc); - err_init: - pm_runtime_put_sync(dev); - return ret; } diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index f42a0acfce00..030e828bfd4c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -8,7 +8,6 @@ #include #include #include -#include #include "pcie-cadence.h" @@ -473,7 +472,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) ret = cdns_pcie_host_init(dev, &resources, rc); if (ret) - goto err_init; + return ret; list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; @@ -491,8 +490,5 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) err_host_probe: pci_free_resource_list(&resources); - err_init: - pm_runtime_put_sync(dev); - return ret; } From patchwork Wed Jul 8 09:30:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235050 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp264973ilg; Wed, 8 Jul 2020 02:30:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJy3bMbY84JZkagUBo3HYipH/7w48O8OyxY9RIbwVooINCDOc6l6Ud3HF+s2CdCcbA1pbd X-Received: by 2002:aa7:c885:: with SMTP id p5mr52466024eds.100.1594200651699; Wed, 08 Jul 2020 02:30:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200651; cv=none; d=google.com; s=arc-20160816; b=smaBGx6esQk9S2KWnhFkq64nhTmT6tjqOfOQoLGADTVdZ/HwcQ7pY3UfSqBznDvj3T XclwdzHW7v+FpBtUj88YB9PTFGr+bn4Ioe7NmeNtwV5fEJtWaU+p06gSAfkUReaFBiGY 5WrOSwgmYUOUJoZNboRiRHvhihLR66zoVdKVI5KBEnnDIHdRXtXVNT1tQ4Y0dEnK/O6l 0MeM0GemktxMML5sXkfOwurCmw6De6d/nkO4/cv+MyvcoObAsrsoMIkanPV9oUNYIMmc 6BCue1E7XgG6TieDOLbm1m3TF3eFnf0hvegytXvcC4v9NGGKMUSeNyyTUq4d2Zgx/jmS 8nMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=fkBtp+U4H+Rsz2F0H88TEXPb+zBTcNhWs4srHjBvzA4=; b=uQ8paJBfHMzPitUEvNMVnjk2xahmFpSuj+TPnVrWZTlH43JJttOBy1xUbzs3TBA2Rb yAOX9lhoFqKt5uhcqnghhepu7RF7ncx9n0irACHWNxoIozBfEeovauJ/qWBOMrousgI2 ShFV+5sMq12MfFXYEY9yx9G8tw6pDLnM+5/pOv8t1+pyxOCaaXDKD2arI6eug5sJlovY 7W7h7SNVi1FNTemfbmIXO16VOymb8YhNbIHM/6oHLx07KKTdDTcnzq2BazS6Aghz1FoC SIX6yHWVijOa2mVBUD+ljmSg7UxLmgoid+ujQcWx0ZeFcMt9qj55am0LJavAgAIRicZj rHoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YbmnIA87; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y15si17861722edm.260.2020.07.08.02.30.51; Wed, 08 Jul 2020 02:30:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YbmnIA87; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728306AbgGHJar (ORCPT + 4 others); Wed, 8 Jul 2020 05:30:47 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59266 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726445AbgGHJaq (ORCPT ); Wed, 8 Jul 2020 05:30:46 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689UZoJ102974; Wed, 8 Jul 2020 04:30:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200635; bh=fkBtp+U4H+Rsz2F0H88TEXPb+zBTcNhWs4srHjBvzA4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YbmnIA87qijELfDMqVIVbCOxjtDpG/fQequvcUHj0zHThJDnSfmoq6+KHm0CfSHV6 cEgDuezF9cJ/NH6feu3tZfgclP35eG9ixUb3vjMKt4izyS4G2L6pZ8sLzxIbCUTews DAnxGeLIjoHn0RRg8f28UaDXpS/zENQx16naTmOI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689UYYe043534 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:35 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:34 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:34 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEK098512; Wed, 8 Jul 2020 04:30:31 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses Date: Wed, 8 Jul 2020 15:00:07 +0530 Message-ID: <20200708093018.28474-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Certain platforms like TI's J721E using Cadence PCIe IP can perform only 32-bit accesses for reading or writing to Cadence registers. Convert all read and write accesses to 32-bit in Cadence PCIe driver in preparation for adding PCIe support in TI's J721E SoC. Also add spin lock to disable interrupts while modifying PCI_STATUS register while raising legacy interrupt since PCI_STATUS is accessible by both remote RC and EP and time between read and write should be minimized. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-ep.c | 4 + drivers/pci/controller/cadence/pcie-cadence.h | 76 ++++++++++++++----- 2 files changed, 62 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 4a829ccff7d0..c6eb2db94680 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -228,6 +228,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, bool is_asserted) { struct cdns_pcie *pcie = &ep->pcie; + unsigned long flags; u32 offset; u16 status; u8 msg_code; @@ -252,11 +253,13 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, msg_code = MSG_CODE_DEASSERT_INTA + intx; } + spin_lock_irqsave(&ep->lock, flags); status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) { status ^= PCI_STATUS_INTERRUPT; cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); } + spin_unlock_irqrestore(&ep->lock, flags); offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | @@ -464,6 +467,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; /* Reserve region 0 for IRQs */ set_bit(0, &ep->ob_region_map); + spin_lock_init(&ep->lock); return 0; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index bc49c22e48a9..a45c11158f49 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -304,6 +304,9 @@ struct cdns_pcie_rc { * @irq_pci_fn: the latest PCI function that has updated the mapping of * the MSI/legacy IRQ dedicated outbound region. * @irq_pending: bitmask of asserted legacy IRQs. + * @lock: spin lock to disable interrupts while modifying PCIe controller + * registers fields (RMW) accessible by both remote RC and EP to + * minimize time between read and write */ struct cdns_pcie_ep { struct cdns_pcie pcie; @@ -315,54 +318,94 @@ struct cdns_pcie_ep { u64 irq_pci_addr; u8 irq_pci_fn; u8 irq_pending; + /* protect writing to PCI_STATUS while raising legacy interrupts */ + spinlock_t lock; }; /* Register access */ -static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) +static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) { - writeb(value, pcie->reg_base + reg); + writel(value, pcie->reg_base + reg); } -static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) +static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) { - writew(value, pcie->reg_base + reg); + return readl(pcie->reg_base + reg); } -static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) +static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { - writel(value, pcie->reg_base + reg); + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 val = readl(aligned_addr); + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + WARN(1, "Address %p and size %d are not aligned\n", addr, size); + return 0; + } + + if (size > 2) + return val; + + return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); } -static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) +static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value) { - return readl(pcie->reg_base + reg); + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 mask; + u32 val; + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + WARN(1, "Address %p and size %d are not aligned\n", addr, size); + return; + } + + if (size > 2) { + writel(value, addr); + return; + } + + mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); + val = readl(aligned_addr) & mask; + val |= value << (offset * 8); + writel(val, aligned_addr); } /* Root Port register access */ static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x1, value); } static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x2, value); } /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + cdns_pcie_write_sz(addr, 0x1, value); } static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + cdns_pcie_write_sz(addr, 0x2, value); } static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, @@ -371,14 +414,11 @@ static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); } -static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) -{ - return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); -} - static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + return cdns_pcie_read_sz(addr, 0x2); } static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) From patchwork Wed Jul 8 09:30:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235053 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265098ilg; Wed, 8 Jul 2020 02:31:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxg8E1bHrhcLGnm0YQrsNIz/90Xz3KQygGBtGyxKtrHDnSuMKfLjL1S9Ornnkr6Esglv4M6 X-Received: by 2002:a17:906:9147:: with SMTP id y7mr47435242ejw.399.1594200662981; Wed, 08 Jul 2020 02:31:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200662; cv=none; d=google.com; s=arc-20160816; b=ZrSkeWeNEgX2fdn85J7BjXhEu2jfEYhA5QnP7P+HswiElX5wibU6rElBxDvsqCSw2d uXvwUDJMn8GLcEog05eMPmgP5dKTe05tbejwWfjihpihTVRVtJfolDd5KSArAi4ILU1e q0vXFa3eliLhk//sYqIZOeWie1hpyXcZ+wogUKjxdrGO/58tB3Qo2ozhW5oH0FXme6ol DFNQOfYPZ4Qn2tCCA30NeCU02r99P7yTyDkg4Wu4dIa1vI/7WX6mJiptcQqXa0HzQWhY 38RLOI2wgZaWoJylJgtQI68OlSfKTg9/YA8qn5qA97hAoWRqbEosmFqTpRb+3k6yDCL7 HUhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CWIKltqarvAYPvUpTOXv+9gnETqUvut1kE2gYgu5r3Y=; b=i/Jg5CoFOzkki87eSW5+pRvpWrG5L3GdKXp/K/BRrH8pPImIj6eZV5Z/IAZVPrDsEo oJkiv9Li4zk2TJIQYDFIadx2dPlwQfsOv8fKxLl3pSf43fLxGZMLknv5X+09W+HUCq84 Wx5UUzY/Mb7OGopAryPtbs5iEwaaDW6BemS6zWA7gp9hQha3y6UmPUYb7CB8ZMuMW9Ks PzaiRD4LNYUOKUVDQ0vdmJ5yMsqSiDHFIyhjKz7avTvlfnx8hyoSfOiBwOBpqzqz2WmL /LV46NOxlninghi0mjZ4FlHqhnhJv6aQtuU6U1+tE7Vvq5t/ilqxZJ6ECnBxVSTr/+Ho hcYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cSG8wSO4; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w9si17326727edr.171.2020.07.08.02.31.02; Wed, 08 Jul 2020 02:31:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cSG8wSO4; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728387AbgGHJaz (ORCPT + 4 others); Wed, 8 Jul 2020 05:30:55 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59296 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728368AbgGHJax (ORCPT ); Wed, 8 Jul 2020 05:30:53 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689UgQ0103018; Wed, 8 Jul 2020 04:30:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200642; bh=CWIKltqarvAYPvUpTOXv+9gnETqUvut1kE2gYgu5r3Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cSG8wSO4rJiPvVfZ3xSchQTR1lNa6KqywznDEz/rQabJ2vRKXaJ9uDOvW91vhhv57 Zft7pJf2TWzbRp2RLdzeHt8BUJC2kiASLwjzoefkl4Tk5BZuG7wYFOfRzdsjXI8UG+ 97tCjNk0UrzzSZ1mRMiiBZbmMr40VOzRKR6e7WkY= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689UgFL095666 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:42 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:42 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:42 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEM098512; Wed, 8 Jul 2020 04:30:38 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 05/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Date: Wed, 8 Jul 2020 15:00:09 +0530 Message-ID: <20200708093018.28474-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index de02fadc4809..a8303258874c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -505,7 +505,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + if (!bridge->ops) + bridge->ops = &cdns_pcie_host_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; From patchwork Wed Jul 8 09:30:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235052 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265088ilg; Wed, 8 Jul 2020 02:31:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzAJLDtJaYr/seQDHPWRY2zXe4/Df1S00qA0gQ00IeetjKR3KEcyMldbvgCHfT8ijn/1/R4 X-Received: by 2002:a17:906:fa15:: with SMTP id lo21mr53188398ejb.156.1594200662272; Wed, 08 Jul 2020 02:31:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200662; cv=none; d=google.com; s=arc-20160816; b=yudoc4+BGcdz3VnYQ8fOW/6V0WpMwSB4nQaKM0gqZbTrmFItN5dPy+VSVuWVUg+1Jt gQpL2nCIQUxmgFAyORteghdEa/fToWs4VpSxG5Xo2AHsVpciNmN69BPXFUakIgE8X9Ok PJba08y5mmRHZASU5hEXjPluqVKxeDTTiV/ca+OpMHZ1b7jF15sGIQ9+t6dF9nhLF16r omIdkvm3GGztGSZPey3Bmwum574w7wc6Yk8crBVmBWjY/nGxUdvb0pUtm+ZPjjCzkyoe LDr/88Ntoe4nj5wrh+rv4j0DK29Z7QId+KlP6XYb8Bnk6Mc5ALq6y/2DnAY9CTAqwKhY FJIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=wA/DJIaqqbKg+dmv5MdTfjimJ83LKxdmuu8q+r4WzXM=; b=shfKiAAwQ5AfHlBX0jzBDexRJbA2dSA1UXHmFCB6rpcR9Ji2w7OuXnp38LCCFMhC/f diKjxTSq1vCjOT08qVQu6kiJvjUNfTW1rmf/cCEGaq3DCFbnXVj/dNBRiuIj2wO1Na/G 4Oxac33RW6uRuFqLkRfMIOuABxa2FRxKrE9K3h6euhzJl38cJxbPYJCiKodwtZt0Djx2 8NKbKqlA311gM2PQUy2RebAezaJjJF/4aa7nn2iFS7a/FarWgndjf5Chtdo6tnRA6PWq i4TfHjQh98ZMA6jsegZQssM4YQ/0IF4Ytn7pcDpm1IBDYYsz0/qIE+5gthjwpJ4C49rH 17Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="jAu4/3B0"; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w9si17326727edr.171.2020.07.08.02.31.02; Wed, 08 Jul 2020 02:31:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="jAu4/3B0"; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728406AbgGHJa5 (ORCPT + 4 others); Wed, 8 Jul 2020 05:30:57 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:55924 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728396AbgGHJaz (ORCPT ); Wed, 8 Jul 2020 05:30:55 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689Uk4F068221; Wed, 8 Jul 2020 04:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200646; bh=wA/DJIaqqbKg+dmv5MdTfjimJ83LKxdmuu8q+r4WzXM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jAu4/3B0R471zRdVpir+e181McmhHAMrQ+yslY/46qF4TRy47Y7+waG2bBsFmDNx9 v4kBlvawZJqYTxslTEA+G/fk+VHr6EvUrdqm1QHnaJHQBGLWwMLWFf5FfGAr1f9eGh aTJNkveanl1hJ1Oh7w5rxEMnvkvTlpOZT6pXE35k= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689UkUo095732 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:46 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:45 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEN098512; Wed, 8 Jul 2020 04:30:42 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 06/14] dt-bindings: PCI: cadence: Remove "mem" from reg binding Date: Wed, 8 Jul 2020 15:00:10 +0530 Message-ID: <20200708093018.28474-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org "mem" is not a memory resource and it overlaps with PCIe config space and memory region. Removve "mem" from reg binding. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index 84a8f095d031..6d67067843bf 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -18,13 +18,12 @@ properties: const: cdns,cdns-pcie-host reg: - maxItems: 3 + maxItems: 2 reg-names: items: - const: reg - const: cfg - - const: mem msi-parent: true @@ -49,9 +48,8 @@ examples: device-id = <0x0200>; reg = <0x0 0xfb000000 0x0 0x01000000>, - <0x0 0x41000000 0x0 0x00001000>, - <0x0 0x40000000 0x0 0x04000000>; - reg-names = "reg", "cfg", "mem"; + <0x0 0x41000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; From patchwork Wed Jul 8 09:30:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235054 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265157ilg; Wed, 8 Jul 2020 02:31:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwO5/UMDDdBE0UFmTQSORep0602xEFq0qk4eEEYL2ODIHU3R5legcxTvMtSMElUuImx/UBl X-Received: by 2002:a17:906:9147:: with SMTP id y7mr47435498ejw.399.1594200667296; Wed, 08 Jul 2020 02:31:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200667; cv=none; d=google.com; s=arc-20160816; b=okiInykvmmclcFElUi9lcu2SkwnxWR1kWZDoIt8X6ZLYeeWi1L93mgXCMWVA+0RHma WQscuI5Wj1+AUMV2y3nlxd/JH7R+/kmbdLKJA7gH2I8zPESZ/0PORiTPZGaJYcyMr0nL FK/8j3d61Ix7fvULNSVvL95X0tWTDCNi/BJ10COwsC+19MiP3xFdv9SYqfOa2LYWBlp+ 0gjVBIwJSJzm/QDTA+UIBcjQ09QEfhMZ+v9UwZsYS11UE8E/hqhUALfaxHd4vzTq37n2 NJ1huezY85aLXugjKmO0HlBliOpGwyiz3lR/Oi/ZMnutPXLUcNi10BtmIcIewEZpCMdz 4VAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WHX8iD9cjD5EU6y2MfFy13+Qxxkt2LTJyVWsnKBeqJU=; b=G4+8Qql/kD6Y8ARHtMgO70TzDZnMEAZZoU+Jq9aIu+xbIkvWxVe1adutDXWCxOhBuS nVi0S1GNTwrs5CM6iEgjAmkIBiiWd2D1L5cteaoEobCnjTVjL5PDdfNBLqnSlvbqjECM r/zqRXgWrAsZYiYJhcw+X1PpU/BHgIO4Vxxs7iGKAzaliwJfa0wxF2U34qq8rGw4FFK1 vCeEQna5QFdt0WuG8sgG4MViQNJ/WWCX6ilA3/a4HuDZeB3fuaL5INCEDt46A8vFdOEz Ks1WYtBQGqi190oFGtlHVz8Y2YsmrnFlr6mEcO1I6CuseMKlv8THN+2QFTj6iacocbmU RvqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cA6rwsJP; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w9si17326727edr.171.2020.07.08.02.31.07; Wed, 08 Jul 2020 02:31:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cA6rwsJP; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728425AbgGHJbD (ORCPT + 4 others); Wed, 8 Jul 2020 05:31:03 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:55936 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726973AbgGHJbC (ORCPT ); Wed, 8 Jul 2020 05:31:02 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689Uoav068296; Wed, 8 Jul 2020 04:30:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200650; bh=WHX8iD9cjD5EU6y2MfFy13+Qxxkt2LTJyVWsnKBeqJU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cA6rwsJPRds/EmVbiF0cW2HU6HHzVHgkP1ylZABnYlQ4t/ljo9303lFBlUez0QKE+ FnvCpBbpO5Nuwf60ieBqJPbGm8PHp+mZQkcQ8mgoDP1acGGbBwTTQuznuykWjtvRj5 FkpdsIbRjvX5h/va+WCktRcOxjQcwCgXJ9fU26OU= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689Uop2102986 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:30:50 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:30:49 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:30:49 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEO098512; Wed, 8 Jul 2020 04:30:46 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Date: Wed, 8 Jul 2020 15:00:11 +0530 Message-ID: <20200708093018.28474-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the ATU and not just the offset. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/cadence/pcie-cadence-host.c | 15 ++++----------- .../pci/controller/cadence/pcie-cadence-plat.c | 13 +++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 8 ++++++-- drivers/pci/controller/cadence/pcie-cadence.h | 1 + 4 files changed, 24 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index a8303258874c..10127ea71b83 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -327,15 +327,14 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; - struct resource *mem_res = pcie->mem_res; struct resource *bus_range = rc->bus_range; struct resource *cfg_res = rc->cfg_res; struct device *dev = pcie->dev; struct device_node *np = dev->of_node; struct of_pci_range_parser parser; + u64 cpu_addr = cfg_res->start; struct of_pci_range range; u32 addr0, addr1, desc1; - u64 cpu_addr; int r, err; /* @@ -348,7 +347,9 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - cpu_addr = cfg_res->start - mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -477,14 +478,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) } rc->cfg_res = res; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); - if (!res) { - dev_err(dev, "missing \"mem\"\n"); - return -EINVAL; - } - - pcie->mem_res = res; - ret = cdns_pcie_start_link(pcie); if (ret) { dev_err(dev, "Failed to start link\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c index f5c6bf6dfcb8..6f5f07b3eed1 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -13,6 +13,8 @@ #include #include "pcie-cadence.h" +#define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF + /** * struct cdns_plat_pcie - private data for this PCIe platform driver * @pcie: Cadence PCIe controller @@ -30,6 +32,15 @@ struct cdns_plat_pcie_of_data { static const struct of_device_id cdns_plat_pcie_of_match[]; +static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) +{ + return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR; +} + +static const struct cdns_pcie_ops cdns_plat_ops = { + .cpu_addr_fixup = cdns_plat_cpu_addr_fixup, +}; + static int cdns_plat_pcie_probe(struct platform_device *pdev) { const struct cdns_plat_pcie_of_data *data; @@ -66,6 +77,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev) rc = pci_host_bridge_priv(bridge); rc->pcie.dev = dev; + rc->pcie.ops = &cdns_plat_ops; cdns_plat_pcie->pcie = &rc->pcie; cdns_plat_pcie->is_rc = is_rc; @@ -93,6 +105,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev) return -ENOMEM; ep->pcie.dev = dev; + ep->pcie.ops = &cdns_plat_ops; cdns_plat_pcie->pcie = &ep->pcie; cdns_plat_pcie->is_rc = is_rc; diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index cd795f6fc1e2..8a02981fd456 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -73,7 +73,9 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -100,7 +102,9 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, } /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->ops->cpu_addr_fixup) + cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 54e10caf2d4b..1d2bdc4e08e4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -254,6 +254,7 @@ struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); void (*stop_link)(struct cdns_pcie *pcie); bool (*link_up)(struct cdns_pcie *pcie); + u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; /** From patchwork Wed Jul 8 09:30:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235061 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265613ilg; Wed, 8 Jul 2020 02:31:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyU5r4hQEmgsWRZXYht3k2aBRg1qKPmD4zqTvO9f01SCbSOoVvBAv0CnbeSYhRkqtw7+t8 X-Received: by 2002:aa7:c98d:: with SMTP id c13mr56729497edt.188.1594200702814; Wed, 08 Jul 2020 02:31:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200702; cv=none; d=google.com; s=arc-20160816; b=cBi5VAtdKNDwpxRDrxFBanCRKfIQ8Cbzb/E0R+nwUU2GJD5kr1Ah7uL93ziludN3jj 4/sP8adJPYP/Z6IrDEkCAtT2Ibast76YmxDu/5BcwItyH2NX7PkdYiCZURZq9LVjPhtf //vYbeVvvNK2Z3YVWybpQGvHYELMVd6WnhPldkk6DmM2kuhHb0BA35a2oddOl7ptHQOM 6WTk85RZfTFGijiF40M5oXjPNpSeUmzGY5LnkU2G3yL/wz20GiS6Dk9ceAGivtfTaVbV ybaBOIEUoymMsm5jBBQ+Rx+W4IjNsgY2nwC+3Go9VwLlIUgasm/VZdPEyuMVEOoPZuPy 84bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=o7DMocX7rlMLQL03fwQQZCPBjquUDY+oSrh6N/Sv4XY=; b=rH59d15uhpFFoWPPMvY2Xs2vWYEefXFy+x8zqV9yPUX7xuG0fnE2BjMkJDdYJDJ9ok XywFGRN29NE4toSsBxc4h8jh66HtbclnqanRVEKkjB843VexTnLP7k6gWwJLxGjbAS+t ngr3mMPwfKmoYZUVFBH1ZOm1iUlG91XuLwZ/y8iOM2vrfqUyHRnwTJn8OaRhteEcgbMw UMcYSys63Veo3ahCwSbVx3AjJWmmX/Tq/h8S35H0ai74eNEvCxeGFIXqwWvpuSDYCSyT ybAmRYOUwHbeQHaBqzzgwZeUvgp5qsBB9ZZnu+nHBygoJlLUn4E4DpdaYNBIM5q/TvrC VuPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jdmWFLo3; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b17si16698056ejb.626.2020.07.08.02.31.42; Wed, 08 Jul 2020 02:31:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jdmWFLo3; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728509AbgGHJbT (ORCPT + 4 others); Wed, 8 Jul 2020 05:31:19 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59386 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728502AbgGHJbS (ORCPT ); Wed, 8 Jul 2020 05:31:18 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689V2LD103123; Wed, 8 Jul 2020 04:31:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200662; bh=o7DMocX7rlMLQL03fwQQZCPBjquUDY+oSrh6N/Sv4XY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jdmWFLo3qdWhee844IiFpfEVrLKl3+vZc1hLFb6fNqmAgFnEsFbQ2aOB9ETiwmxMe n4MLqZAqVCrgU8LdcOt2Worm7K7qc6PXafUShEy4/N23keTpnfjxONMu0sKFV7hTYe VtM/1IhW8UVu58qHco73jI45cRDKeVftYX+dd9vE= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689V26h022256; Wed, 8 Jul 2020 04:31:02 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:31:02 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:31:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJER098512; Wed, 8 Jul 2020 04:30:58 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Date: Wed, 8 Jul 2020 15:00:14 +0530 Message-ID: <20200708093018.28474-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add host mode dt-bindings for TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml new file mode 100644 index 000000000000..d7b60487c6c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI Host (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: "cdns-pcie-host.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-host + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: cfg + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + vendor-id: + const: 0x104c + + device-id: + const: 0xb00d + + msi-map: true + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - vendor-id + - device-id + - msi-map + - dma-coherent + - dma-ranges + - ranges + - reset-gpios + - phys + - phy-names + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_rc: pcie@2900000 { + compatible = "ti,j721e-pcie-host"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + vendor-id = <0x104c>; + device-id = <0xb00d>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + }; + }; From patchwork Wed Jul 8 09:30:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235057 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265322ilg; Wed, 8 Jul 2020 02:31:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyx8wM+/po9dhMnF35ofcl+Z2KEy+XptDKH/flAEa8fHI/krXHlk4ZIqMW56W3feG+tE3i9 X-Received: by 2002:aa7:dd10:: with SMTP id i16mr64436427edv.227.1594200680820; Wed, 08 Jul 2020 02:31:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200680; cv=none; d=google.com; s=arc-20160816; b=IQHJCfsbcXfI4qC368lnuzb6AV8vETtQaKq6V2XsQnEMyY9vFqj/soa231nQ6mBJNq eDpL45H126DDbwqKjpWCU9oAB0Desqo/nx+GPVzV8/fzixXI+/lRXROJpWCpesqsUkzE hUapwfIxRoLLHxkfqgyTXN2v3aXtfEH9XwL/jtTAHbCk4uSpc7xAUVe0ZjxepeE488k8 M7foP42+6APXYHM6ihKGVrJDF3ucuzVkPwud3a2HyUkS9ulNG8Fftmq7WJsL19AP018I qq++2sqrX+su3GtngnZBhZ4RsIOYT+Fw+eHkJUvLNygnWmvv4DNDGx6SebZtkIIq6gC0 kx9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=V5CpAZikPgA7e0e1YLq+ICNB6YOXd57BoX2naroTU7k=; b=1F7nKhux1YetczPEiTjgjp4QQAEiL1jTQ7reGxB5qVuYoYI1DUvRZkOCrl6AbgOgxu BWJ21GFF5L2R03guCMAcTJkibkbv8BPSd3yRvb9oEklYp29pXXFBWKeFWksHboxDv3Nn YleW5sd2IORzJPj3DIplC9TYqPYb8jmlfXpsOtdwdhq33UAuKvp+ZbDcIhLK4qzjQAmQ fKPwr6CbMRKs6/7JTzKNrEh9K6IkRrRVsBjchyh5NARveFzQzqwW0cjOqOKwNX+zPHMn ATR8Rxjt+SR4ncg4kfye3xzAFFRHfqd4pTU9uylgDbGme/R3aRQAHndQH3ZzUNfYpzBc DDNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Oe6hFCga; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id eb10si22133992edb.410.2020.07.08.02.31.20; Wed, 08 Jul 2020 02:31:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Oe6hFCga; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728520AbgGHJbT (ORCPT + 4 others); Wed, 8 Jul 2020 05:31:19 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59384 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728500AbgGHJbS (ORCPT ); Wed, 8 Jul 2020 05:31:18 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689V6A7103164; Wed, 8 Jul 2020 04:31:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200666; bh=V5CpAZikPgA7e0e1YLq+ICNB6YOXd57BoX2naroTU7k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Oe6hFCgaQtUPtS5FLRHQ+PQ4PWnkP/G+Exq2ZlwVz0xavYYyh4cIb4E89y0HT7fon VEeSfW/Lhc6OVSA5IrbwAUl9JjtRG0XffJtoa4xaeNvEXbkpHZ1uhC0o0+HwJlMYpL pvJ2YNDw3GBg1MZR1SD+k4bNFxNCQ0PHLDa0kSBU= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689V6VO022795; Wed, 8 Jul 2020 04:31:06 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:31:05 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:31:05 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJES098512; Wed, 8 Jul 2020 04:31:02 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 11/14] dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC Date: Wed, 8 Jul 2020 15:00:15 +0530 Message-ID: <20200708093018.28474-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PCIe EP mode dt-bindings for TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- .../bindings/pci/ti,j721e-pci-ep.yaml | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml new file mode 100644 index 000000000000..c09d25b2c1b2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI J721E PCI EP (PCIe Wrapper) + +maintainers: + - Kishon Vijay Abraham I + +allOf: + - $ref: "cdns-pcie-ep.yaml#" + +properties: + compatible: + enum: + - ti,j721e-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: intd_cfg + - const: user_cfg + - const: reg + - const: mem + + ti,syscon-pcie-ctrl: + description: Phandle to the SYSCON entry required for configuring PCIe mode + and link speed. + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + description: clock-specifier to represent input to the PCIe + + clock-names: + items: + - const: fck + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + +required: + - compatible + - reg + - reg-names + - ti,syscon-pcie-ctrl + - max-link-speed + - num-lanes + - power-domains + - clocks + - clock-names + - cdns,max-outbound-regions + - dma-coherent + - max-functions + - phys + - phy-names + +examples: + - | + #include + + pcie0_ep: pcie-ep@d000000 { + compatible = "ti,j721e-pcie-ep"; + reg = <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; + ti,syscon-pcie-ctrl = <&pcie0_ctrl>; + max-link-speed = <3>; + num-lanes = <2>; + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 239 1>; + clock-names = "fck"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <6>; + dma-coherent; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + }; From patchwork Wed Jul 8 09:30:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235060 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265559ilg; Wed, 8 Jul 2020 02:31:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8mcfGLH3C4Poz6kjvuNpRSLq54TE5MRoHKZqtRXA4PrKpVmDdddVnFOJG8pD20QR6bzLu X-Received: by 2002:aa7:da4c:: with SMTP id w12mr53091013eds.122.1594200699012; Wed, 08 Jul 2020 02:31:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200699; cv=none; d=google.com; s=arc-20160816; b=zPeQKM+vWo0g2K8gGmrIsgVZj24jPktUlsax5vvwtnkbXdvAAK4rD0iyFJBjmRIBcO EIpdpI+jzotW2JgZjlWFeguUBBVMJgFg26VQsaOgAh/50u29siPcVQTBuGROibF9bq/P BiXBWVQPHzk4jn/EXbU3PRRKZjyjVtixo2pE9A0Ko5v4HcnHFIBoY77UmAo35J+p7Df+ 4DG/29NuHyHuffmBOiezCzx6nqwECRQQ44jICrg9N4KzB0Ja/RkxBK0GYwqSVPdbCCYO kr6wwi7FHkNuvIYbIVpCwpdijpMssQruttzGNrcI1pcrPniWx9xwrb2Lq8el+pm/+UsR z/nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=xyX3aiXm+07Z01ejgMoUdbkhQAwdUpEtLjGrsDE0wxs=; b=sx5aIPSwUePlBrBGQ98qnpQJZCqhwokD3V4+MEsczRJggPRgLiXhEw6/T6eaoVUObH JAvuFqi1ocPMa/VQ/DU6LvPzPez9Rolr7GFMutb44JGXrF/zxT7cp5SuV3HBOFk/XpBX U9GPylcTCWrCoYRX+rCHfceVx8zwSzmtSrIAGaiKucwflkx9vvO9RNxzi4E/X+r8gcIK FdeQ0eOO6G9jICgPPKfqDRBm9E9JRlrrcU0lenDKdbm3tkMv/2bF/iz7MaAwzn8xLWNM +XaySl0iB827GhsYTmuvCTtCUMG/ZduAjBizpnJiBHBl6eoAQD0KkesVoIPBBFhdIEn1 rSLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LAj8PMb5; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b17si16698056ejb.626.2020.07.08.02.31.38; Wed, 08 Jul 2020 02:31:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LAj8PMb5; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728551AbgGHJbX (ORCPT + 4 others); Wed, 8 Jul 2020 05:31:23 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58236 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728516AbgGHJbW (ORCPT ); Wed, 8 Jul 2020 05:31:22 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689VAGZ078056; Wed, 8 Jul 2020 04:31:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200670; bh=xyX3aiXm+07Z01ejgMoUdbkhQAwdUpEtLjGrsDE0wxs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LAj8PMb5brAq2BinT2uR4WSFYZh0bNyeyS83HgtUGfWEiHxmQIODEFxuPb8h+E1eF tSeXz43bLVFfL0uq7FTV3UTWOr1cPobwqmkWC2vBIhkHpXJAR06/j7RhyXdp6wI4jp EkoFb/eMr8pC/7EPfG8N3Y/SMMBDquJVwo0DEa3A= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689V9cU022917; Wed, 8 Jul 2020 04:31:09 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:31:09 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:31:09 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJET098512; Wed, 8 Jul 2020 04:31:06 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 12/14] PCI: j721e: Add TI J721E PCIe driver Date: Wed, 8 Jul 2020 15:00:16 +0530 Message-ID: <20200708093018.28474-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/Kconfig | 23 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 493 ++++++++++++++++++ .../controller/cadence/pcie-cadence-host.c | 4 +- drivers/pci/controller/cadence/pcie-cadence.h | 8 + 5 files changed, 527 insertions(+), 2 deletions(-) create mode 100644 drivers/pci/controller/cadence/pci-j721e.c -- 2.17.1 diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index b76b3cf55ce5..5d30564190e1 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,4 +42,27 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCI_J721E + bool + +config PCI_J721E_HOST + bool "TI J721E PCIe platform host controller" + depends on OF + select PCIE_CADENCE_HOST + select PCI_J721E + help + Say Y here if you want to support the TI J721E PCIe platform + controller in host mode. TI J721E PCIe controller uses Cadence PCIe + core. + +config PCI_J721E_EP + bool "TI J721E PCIe platform endpoint controller" + depends on OF + depends on PCI_ENDPOINT + select PCIE_CADENCE_EP + select PCI_J721E + help + Say Y here if you want to support the TI J721E PCIe platform + controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe + core. endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 232a3f20876a..9bac5fb2f13d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o +obj-$(CONFIG_PCI_J721E) += pci-j721e.o diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c new file mode 100644 index 000000000000..23ad8fa699c4 --- /dev/null +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * pci-j721e - PCIe controller driver for TI's J721E SoCs + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../pci.h" +#include "pcie-cadence.h" + +#define ENABLE_REG_SYS_2 0x108 +#define STATUS_REG_SYS_2 0x508 +#define STATUS_CLR_REG_SYS_2 0x708 +#define LINK_DOWN BIT(1) + +#define J721E_PCIE_USER_CMD_STATUS 0x4 +#define LINK_TRAINING_ENABLE BIT(0) + +#define J721E_PCIE_USER_LINKSTATUS 0x14 +#define LINK_STATUS GENMASK(1, 0) + +enum link_status { + NO_RECEIVERS_DETECTED, + LINK_TRAINING_IN_PROGRESS, + LINK_UP_DL_IN_PROGRESS, + LINK_UP_DL_COMPLETED, +}; + +#define J721E_MODE_RC BIT(7) +#define LANE_COUNT_MASK BIT(8) +#define LANE_COUNT(n) ((n) << 8) + +#define GENERATION_SEL_MASK GENMASK(1, 0) + +#define MAX_LANES 2 + +struct j721e_pcie { + struct device *dev; + u32 mode; + u32 num_lanes; + struct cdns_pcie *cdns_pcie; + void __iomem *user_cfg_base; + void __iomem *intd_cfg_base; +}; + +enum j721e_pcie_mode { + PCI_MODE_RC, + PCI_MODE_EP, +}; + +struct j721e_pcie_data { + enum j721e_pcie_mode mode; +}; + +static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->user_cfg_base + offset); +} + +static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->user_cfg_base + offset); +} + +static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->intd_cfg_base + offset); +} + +static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->intd_cfg_base + offset); +} + +static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) +{ + struct j721e_pcie *pcie = priv; + struct device *dev = pcie->dev; + u32 reg; + + reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); + if (!(reg & LINK_DOWN)) + return IRQ_NONE; + + dev_err(dev, "LINK DOWN!\n"); + + j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN); + return IRQ_HANDLED; +} + +static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) +{ + u32 reg; + + reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); + reg |= LINK_DOWN; + j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); +} + +static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); + reg |= LINK_TRAINING_ENABLE; + j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); + + return 0; +} + +static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); + reg &= ~LINK_TRAINING_ENABLE; + j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); +} + +static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) +{ + struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); + reg &= LINK_STATUS; + if (reg == LINK_UP_DL_COMPLETED) + return true; + + return false; +} + +static const struct cdns_pcie_ops j721e_pcie_ops = { + .start_link = j721e_pcie_start_link, + .stop_link = j721e_pcie_stop_link, + .link_up = j721e_pcie_link_up, +}; + +static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 mask = J721E_MODE_RC; + u32 mode = pcie->mode; + u32 val = 0; + int ret = 0; + + if (mode == PCI_MODE_RC) + val = J721E_MODE_RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) + dev_err(dev, "failed to set pcie mode\n"); + + return ret; +} + +static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + struct device_node *np = dev->of_node; + int link_speed; + u32 val = 0; + int ret; + + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 2) + link_speed = 2; + + val = link_speed - 1; + ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); + if (ret) + dev_err(dev, "failed to set link speed\n"); + + return ret; +} + +static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 lanes = pcie->num_lanes; + u32 val = 0; + int ret; + + val = LANE_COUNT(lanes - 1); + ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); + if (ret) + dev_err(dev, "failed to set link count\n"); + + return ret; +} + +static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); + if (IS_ERR(syscon)) { + dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); + return PTR_ERR(syscon); + } + + ret = j721e_pcie_set_mode(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set pci mode\n"); + return ret; + } + + ret = j721e_pcie_set_link_speed(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set link speed\n"); + return ret; + } + + ret = j721e_pcie_set_lane_count(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set num-lanes\n"); + return ret; + } + + return 0; +} + +static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static struct pci_ops cdns_ti_pcie_host_ops = { + .map_bus = cdns_pci_map_bus, + .read = cdns_ti_pcie_config_read, + .write = cdns_ti_pcie_config_write, +}; + +static const struct j721e_pcie_data j721e_pcie_rc_data = { + .mode = PCI_MODE_RC, +}; + +static const struct j721e_pcie_data j721e_pcie_ep_data = { + .mode = PCI_MODE_EP, +}; + +static const struct of_device_id of_j721e_pcie_match[] = { + { + .compatible = "ti,j721e-pcie-host", + .data = &j721e_pcie_rc_data, + }, + { + .compatible = "ti,j721e-pcie-ep", + .data = &j721e_pcie_ep_data, + }, + {}, +}; + +static int j721e_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct pci_host_bridge *bridge; + struct j721e_pcie_data *data; + struct cdns_pcie *cdns_pcie; + struct j721e_pcie *pcie; + struct cdns_pcie_rc *rc; + struct cdns_pcie_ep *ep; + struct gpio_desc *gpiod; + void __iomem *base; + u32 num_lanes; + u32 mode; + int ret; + int irq; + + data = (struct j721e_pcie_data *)of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + mode = (u32)data->mode; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->dev = dev; + pcie->mode = mode; + + base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->intd_cfg_base = base; + + base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->user_cfg_base = base; + + ret = of_property_read_u32(node, "num-lanes", &num_lanes); + if (ret || num_lanes > MAX_LANES) + num_lanes = 1; + pcie->num_lanes = num_lanes; + + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) + return -EINVAL; + + irq = platform_get_irq_byname(pdev, "link_state"); + if (irq < 0) + return irq; + + dev_set_drvdata(dev, pcie); + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = j721e_pcie_ctrl_init(pcie); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, + "j721e-pcie-link-down-irq", pcie); + if (ret < 0) { + dev_err(dev, "failed to request link state IRQ %d\n", irq); + goto err_get_sync; + } + + j721e_pcie_config_link_irq(pcie); + + switch (mode) { + case PCI_MODE_RC: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) { + ret = -ENOMEM; + goto err_get_sync; + } + + bridge->ops = &cdns_ti_pcie_host_ops; + rc = pci_host_bridge_priv(bridge); + + cdns_pcie = &rc->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &j721e_pcie_ops; + pcie->cdns_pcie = cdns_pcie; + + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + goto err_get_sync; + } + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy\n"); + goto err_get_sync; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + + ret = cdns_pcie_host_setup(rc); + if (ret < 0) + goto err_pcie_setup; + + break; + case PCI_MODE_EP: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) { + ret = -ENOMEM; + goto err_get_sync; + } + + cdns_pcie = &ep->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &j721e_pcie_ops; + pcie->cdns_pcie = cdns_pcie; + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy\n"); + goto err_get_sync; + } + + ret = cdns_pcie_ep_setup(ep); + if (ret < 0) + goto err_pcie_setup; + + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } + + return 0; + +err_pcie_setup: + cdns_pcie_disable_phy(cdns_pcie); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return ret; +} + +static int j721e_pcie_remove(struct platform_device *pdev) +{ + struct j721e_pcie *pcie = platform_get_drvdata(pdev); + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; + struct device *dev = &pdev->dev; + + cdns_pcie_disable_phy(cdns_pcie); + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return 0; +} + +static struct platform_driver j721e_pcie_driver = { + .probe = j721e_pcie_probe, + .remove = j721e_pcie_remove, + .driver = { + .name = "j721e-pcie", + .of_match_table = of_j721e_pcie_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(j721e_pcie_driver); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 8935f7a37e5a..ba157278fb0f 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -23,8 +23,8 @@ static u8 bar_aperture_mask[] = { [RP_BAR1] = 0xF, }; -static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where) +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) { struct pci_host_bridge *bridge = pci_find_host_bridge(bus); struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 8057f4a338bd..07c3cb63a6fe 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -475,11 +475,19 @@ static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) #ifdef CONFIG_PCIE_CADENCE_HOST int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); +void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { return 0; } + +static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + return NULL; +} #endif #ifdef CONFIG_PCIE_CADENCE_EP From patchwork Wed Jul 8 09:30:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 235058 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp265400ilg; Wed, 8 Jul 2020 02:31:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy9DPPVufSUxWFdyAIQnRhQDsN4YdtLUAgvRs8dVY0PMALhlzY8a08h0MKV8V5yTrxXrZ+j X-Received: by 2002:a17:906:5203:: with SMTP id g3mr49562523ejm.58.1594200687398; Wed, 08 Jul 2020 02:31:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594200687; cv=none; d=google.com; s=arc-20160816; b=aug0A7lIfmAQVGDyB3ug9uG1AOeXLAmxnjmSMxtKz+QLKzxWL3//4uIi9yAobBvLra P3HHZOwnmJSqdeVg+GnTWwYPAbVAw/r3Dj/SoXY8f7+c1lsIIP5SuxJAsvvIGAb3fO8l XlvXvp7gbuvbLBO2lSrvQr+2F+qcYfLmIM3/Ek4SFQ0OdfXd8AxBI06o8h6ZLPCClU1X pkIkNzkdA4UXrbvXZEAPY/9xiTv8hAf/Lh4Yq1+jvMOBSCaV0K7rVRDKUcljBy/tF2al Z7YowboyK7BP3STbbeTOAMgLZIArTooCw3Iabm5hOVmvD/9mgRCrlO+xE26EBTJcEN1V K7qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=7OcnyXAqbvLTfoWs7cVYpAjSlZ1UufTOUaO13t5B4CY=; b=CKVxqX3HOTScR/C1mrfKASQgWYGhDXxNCp+acescFQaPgKQ9uNWV906mecbY68vRGO v0dI1fGuAAg7GXrgtGZIm8hhNhwmQxKEu2XjOi/AWiDlTwOjaScpOa0SB9DPkJsMJEr9 6Zz6oWGsSRZ/BwYvgFT9MV5Dx0aWe0VqN3ut88QqrEPQLjKhh4WRgFegLCIROI2t48cR f53g1eKJNzwSNZ3RHw37Ec14eoiI8tjpcga8bUggkfV/mHDD9YIk/HaCoHcEMzhO6DLA WMOjDcSL0Y3ecKSlRZsjoBUF1lZPdQeQfYzHDaXYLAs4J43nXeuUL0YITjn8EiS6IPjA fj+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aTR2N0PO; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q20si8677018edw.521.2020.07.08.02.31.27; Wed, 08 Jul 2020 02:31:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aTR2N0PO; spf=pass (google.com: domain of linux-omap-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728516AbgGHJb0 (ORCPT + 4 others); Wed, 8 Jul 2020 05:31:26 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39054 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728550AbgGHJbY (ORCPT ); Wed, 8 Jul 2020 05:31:24 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0689VDUu109637; Wed, 8 Jul 2020 04:31:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594200673; bh=7OcnyXAqbvLTfoWs7cVYpAjSlZ1UufTOUaO13t5B4CY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aTR2N0POKEBdioajxGaza1m3y89NwEVdHaGq2mh3d3/c8axJ/1QdHfG0eXnmnZfA+ x7KSnEeNC/Q2Q0ZSDI7paX7WaS5RYcofRWtdURUmAq2IyrbkKz82ATVVkNMvfJaokW 2N1qorqJ6ueo5KuOKXsXMFlEquxWtrvtPrAWN+WU= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0689VDWL096644 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 8 Jul 2020 04:31:13 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 8 Jul 2020 04:31:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 8 Jul 2020 04:31:13 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0689UJEU098512; Wed, 8 Jul 2020 04:31:10 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Kishon Vijay Abraham I , Lorenzo Pieralisi , Arnd Bergmann CC: Greg Kroah-Hartman , , , , , Subject: [PATCH v6 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Date: Wed, 8 Jul 2020 15:00:17 +0530 Message-ID: <20200708093018.28474-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708093018.28474-1-kishon@ti.com> References: <20200708093018.28474-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add J721E in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in J721E. Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 41c40971979e..e060796f9caa 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -68,6 +68,7 @@ #define PCI_ENDPOINT_TEST_FLAGS 0x2c #define FLAG_USE_DMA BIT(0) +#define PCI_DEVICE_ID_TI_J721E 0xb00d #define PCI_DEVICE_ID_TI_AM654 0xb00c #define is_am654_pci_dev(pdev) \ @@ -932,6 +933,11 @@ static const struct pci_endpoint_test_data am654_data = { .irq_type = IRQ_TYPE_MSI, }; +static const struct pci_endpoint_test_data j721e_data = { + .alignment = 256, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x), .driver_data = (kernel_ulong_t)&default_data, @@ -946,6 +952,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { }, { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0), }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), + .driver_data = (kernel_ulong_t)&j721e_data, + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);