From patchwork Tue Feb 18 16:13:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 236514 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Tue, 18 Feb 2020 08:13:23 -0800 Subject: [PATCH v1 1/2] fu540: prci: add request and free clock handlers In-Reply-To: <1582042404-27356-1-git-send-email-sagar.kadam@sifive.com> References: <1582042404-27356-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1582042404-27356-2-git-send-email-sagar.kadam@sifive.com> Add handlers to check if a valid clock id is used to request clock by any driver using clk_request/clk_free API calls. Signed-off-by: Sagar Shrikant Kadam Tested-by: Vincent Chen --- drivers/clk/sifive/fu540-prci.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 8847178..ecf29a0 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -580,6 +580,28 @@ static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate) return rate; } +static int sifive_fu540_prci_clk_request(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + if (clk->id >= ARRAY_SIZE(__prci_init_clocks)) + return -EINVAL; + + return 0; +} + +static int sifive_fu540_prci_clk_free(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + if (clk->id >= ARRAY_SIZE(__prci_init_clocks)) + return -EINVAL; + + return 0; +} + static int sifive_fu540_prci_probe(struct udevice *dev) { int i, err; @@ -611,6 +633,8 @@ static int sifive_fu540_prci_probe(struct udevice *dev) static struct clk_ops sifive_fu540_prci_ops = { .set_rate = sifive_fu540_prci_set_rate, .get_rate = sifive_fu540_prci_get_rate, + .request = sifive_fu540_prci_clk_request, + .rfree = sifive_fu540_prci_clk_free, }; static const struct udevice_id sifive_fu540_prci_ids[] = { From patchwork Tue Feb 18 16:13:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 236513 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Tue, 18 Feb 2020 08:13:24 -0800 Subject: [PATCH v1 2/2] cpu: clk: riscv: populate proper CPU core clk frequency In-Reply-To: <1582042404-27356-1-git-send-email-sagar.kadam@sifive.com> References: <1582042404-27356-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1582042404-27356-3-git-send-email-sagar.kadam@sifive.com> Fetch core clock frequency from prci if clock-frequency for CPU nodes is missing in device tree, so that the cmd "#cpu detail" will show the correct CPU frequency. U-Boot command "#cpu detail" is showing wrong frequency values. This patch fixes this issue by getting the core clock set in prci driver if clock-frequency is not added to CPU nodes in device tree. It is tested on HiFive Unleashed A00 board. Signed-off-by: Sagar Shrikant Kadam Tested-by: Vincent Chen --- drivers/cpu/riscv_cpu.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 28ad0aa..eb5491f 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -25,11 +27,46 @@ static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) return 0; } +static ulong riscv_get_clkrate(int clk_index) +{ + int ret; + struct udevice *dev; + struct clk clk; + ulong rate; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(sifive_fu540_prci), + &dev); + if (ret < 0) { + pr_err("%s: Could not get device driver\n", __func__); + return ret; + } + + clk.id = clk_index; + ret = clk_request(dev, &clk); + if (ret < 0) { + pr_err("%s: request to clock device failed...\n", __func__); + return ret; + } + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + return rate; +} + static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) { const char *mmu; + int ret; - dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + ret = dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + if (ret) { + /* if clock-frequency is missing in DT, read it from prci */ + debug("Fetch core clk configured by prci\n"); + info->cpu_freq = riscv_get_clkrate(PRCI_CLK_COREPLL); + } mmu = dev_read_string(dev, "mmu-type"); if (!mmu)