From patchwork Tue Feb 18 17:09:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 236517 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 18 Feb 2020 18:09:30 +0100 Subject: [PATCH V3 1/2] ARM: socfpga: Permit overriding the default timer frequency Message-ID: <20200218170931.14777-1-marex@denx.de> The default timer rate may be different than 25 MHz, permit overriding the default rate in board configuration file. Ultimatelly, this should be properly handled by a clock driver, however that is not available on Gen5 yet. Signed-off-by: Marek Vasut Cc: Ley Foon Tan Cc: Simon Goldschmidt --- V2: Drop misleading comment V3: No change --- include/configs/socfpga_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..54a43569dc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,12 +94,13 @@ * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif /* * L4 Watchdog From patchwork Tue Feb 18 17:09:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 236518 List-Id: U-Boot discussion From: marex at denx.de (Marek Vasut) Date: Tue, 18 Feb 2020 18:09:31 +0100 Subject: [PATCH V3 2/2] ARM: socfpga: Add missing Denali NAND config options In-Reply-To: <20200218170931.14777-1-marex@denx.de> References: <20200218170931.14777-1-marex@denx.de> Message-ID: <20200218170931.14777-2-marex@denx.de> The Denali SPL shim won't build without these options set, set them accordingly to fix the build error and let the SPL shim to work correctly. Signed-off-by: Marek Vasut Cc: Ley Foon Tan Cc: Simon Goldschmidt --- V2: No changes V2: Drop CONFIG_SYS_NAND_USE_FLASH_BBT --- include/configs/socfpga_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 54a43569dc..ec41843695 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -121,6 +121,7 @@ * NAND Support */ #ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS