From patchwork Fri Feb 21 01:25:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 236661 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Fri, 21 Feb 2020 09:25:05 +0800 Subject: [PATCH 1/2] configs: socfpga: Add QSPI support for Cyclone 5 Message-ID: <20200221012506.5042-1-ley.foon.tan@intel.com> Add QSPI boot support to boot target devices list. Platform can provide their own boot settings through SOCFPGA_BOOT_SETTINGS macro if needed. Add SOCFPGA_BOOT_SETTINGS for Cyclone 5. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_common.h | 18 ++++++++++++++++++ include/configs/socfpga_cyclone5_socdk.h | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..f3ddfca289 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -228,11 +228,28 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define BOOT_TARGET_DEVICES_MMC(func) #endif +#ifdef CONFIG_CMD_SF +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=run qspiload; run qspiboot\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ BOOT_TARGET_DEVICES_PXE(func) \ BOOT_TARGET_DEVICES_DHCP(func) +#ifndef SOCFPGA_BOOT_SETTINGS +#define SOCFPGA_BOOT_SETTINGS +#endif + #include #ifndef CONFIG_EXTRA_ENV_SETTINGS @@ -245,6 +262,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "pxefile_addr_r=0x02200000\0" \ "ramdisk_addr_r=0x02300000\0" \ "socfpga_legacy_reset_compat=1\0" \ + SOCFPGA_BOOT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 028db2a09e..62ad001c4b 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -14,6 +14,24 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +/* QSPI boot */ +#define FDT_SIZE __stringify(0x00010000) +#define KERNEL_SIZE __stringify(0x005d0000) +#define QSPI_FDT_ADDR __stringify(0x00220000) +#define QSPI_KERNEL_ADDR __stringify(0x00230000) + +#define SOCFPGA_BOOT_SETTINGS \ + "fdt_size=" FDT_SIZE "\0" \ + "kernel_size=" KERNEL_SIZE "\0" \ + "qspi_fdt_addr=" QSPI_FDT_ADDR "\0" \ + "qspi_kernel_addr=" QSPI_KERNEL_ADDR "\0" \ + "qspiboot=setenv bootargs earlycon " \ + "root=/dev/mtdblock1 rw rootfstype=jffs2; " \ + "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "qspiload=sf probe; " \ + "sf read ${kernel_addr_r} ${qspi_kernel_addr} ${kernel_size}; " \ + "sf read ${fdt_addr_r} ${qspi_fdt_addr} ${fdt_size}\0" + /* The rest of the configuration is shared */ #include From patchwork Fri Feb 21 01:25:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 236662 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Fri, 21 Feb 2020 09:25:06 +0800 Subject: [PATCH 2/2] configs: socfpga: Add QSPI boot for Arria 10 SoCDK In-Reply-To: <20200221012506.5042-1-ley.foon.tan@intel.com> References: <20200221012506.5042-1-ley.foon.tan@intel.com> Message-ID: <20200221012506.5042-2-ley.foon.tan@intel.com> Add QSPI boot settings for Arria 10 SoCDK. Signed-off-by: Ley Foon Tan --- include/configs/socfpga_arria10_socdk.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 645e66e6b0..e1d01c095f 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -39,6 +39,15 @@ /* SPL memory allocation configuration, this is for FAT implementation */ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 +#define KERNEL_FIT_ADDR __stringify(0x1200000) + +#define SOCFPGA_BOOT_SETTINGS \ + "kernelfit_addr=" KERNEL_FIT_ADDR "\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + "root=/dev/mtdblock1 rw rootfstype=jffs2;" \ + "bootm ${scriptaddr}\0" \ + "qspiload=sf probe; sf read ${scriptaddr} ${kernelfit_addr}\0" \ + /* The rest of the configuration is shared */ #include