From patchwork Fri Feb 28 04:54:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Park, Aiden" X-Patchwork-Id: 236969 List-Id: U-Boot discussion From: aiden.park at intel.com (Park, Aiden) Date: Fri, 28 Feb 2020 04:54:35 +0000 Subject: [PATCH] x86: Cache write back at 32-bit entry point Message-ID: In a certain condition, invd causes cache coherence issue. 1. Pre-stage boot code passes memory address to U-Boot 2. The data of the memory address is still in data cache line 3. The invd marks data cache line as invalid without write back 4. U-Boot accesses the memory address 5. Data is invalid Therefore, wbinvd is recommended at the 32-bit entry point even though it consumes extra cpu clock cycles. Signed-off-by: Aiden Park --- arch/x86/cpu/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 26cf995db2..01524635e9 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -50,7 +50,7 @@ _x86boot_start: movl %cr0, %eax orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 - invd + wbinvd /* * Zero the BIST (Built-In Self Test) value since we don't have it.