From patchwork Wed Jul 8 10:05:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241034 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:22 +0530 Subject: [PATCH v2 1/7] arm64: dts: rockchip: Sync v5.7-rc1 rk3399pro.dtsi In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-2-jagan@amarulasolutions.com> Sync linux-next v5.7-rc1 rk3399pro.dtsi. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399pro.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 arch/arm/dts/rk3399pro.dtsi diff --git a/arch/arm/dts/rk3399pro.dtsi b/arch/arm/dts/rk3399pro.dtsi new file mode 100644 index 0000000000..bb5ebf6608 --- /dev/null +++ b/arch/arm/dts/rk3399pro.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + +#include "rk3399.dtsi" + +/ { + compatible = "rockchip,rk3399pro"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie_phy { + status = "okay"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; From patchwork Wed Jul 8 10:05:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241035 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:23 +0530 Subject: [PATCH v2 2/7] arm64: dts: rockchip: Sync v5.7-rc1 VMARC RK3399Pro SOM In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-3-jagan@amarulasolutions.com> VMARC RK3399Pro SOM is a standard SMARC SOM design with Rockchip RK3399Pro SoC, which is designed by Vamrs. Specification: - Rockchip RK3399Pro - PMIC: RK809-3 - SD slot, 16GiB eMMC - 2xUSB-2.0, 1xUSB3.0 - USB-C for power supply - Ethernet, PCIe - HDMI, MIPI-DSI/CSI, eDP Add initial support for VMARC RK3399Pro SOM, this would use with associated carrier board. Sync this dtsi from linux-next v5.7-rc1. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399pro-vmarc-som.dtsi | 333 ++++++++++++++++++++++++++ 1 file changed, 333 insertions(+) create mode 100644 arch/arm/dts/rk3399pro-vmarc-som.dtsi diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi new file mode 100644 index 0000000000..0a516334f1 --- /dev/null +++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include +#include +#include + +/ { + compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + rk809: pmic at 20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_0v9: LDO_REG3 { + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * As per BSP, but schematic not showing any regulator + * pin for LD05. + */ + vdd1v5_dvp: LDO_REG5 { + regulator-name = "vdd1v5_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_3v0: LDO_REG7 { + regulator-name = "vccio_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * As per BSP, but schematic not showing any regulator + * pin for LD09. + */ + vcc_sd: LDO_REG9 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb2: SWITCH_REG1 { + regulator-name = "vcc5v0_usb2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + vccio_3v3: vcc_lan: SWITCH_REG2 { + regulator-name = "vccio_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vccio_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 0 &pcfg_pull_up>; + }; + }; +}; From patchwork Wed Jul 8 10:05:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241036 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:24 +0530 Subject: [PATCH v2 3/7] ARM: dts: rockchip: Sync v5.7-rc1 Radxa Dalang Carrier In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-4-jagan@amarulasolutions.com> Carrier board often referred as baseboard. For making complete SBC or any other industrial boards, these carrier boards will be used with associated SOMs. Radxa has Dalang carrier board which supports on-board peripherals, ports like USB-2.0, USB-3.0, HDMI, MIPI DSI/CSI, eDP, Ethernet, WiFi, PCIe, USB-C, 40-Pin GPIO header and etc. Right now Dalang carrier board is used with two SBC-variants: Rock Pi N10 => VMARC RK3399Por SOM + Dalang carrier board Rock Pi N8 => VMARC RK3288 SOM + Dalang carrier board(+codec) So add this carrier board dtsi as a separate file in ARM directory, so-that the same can reuse it in both rk3288, rk3399pro variants of Rockchip SOMs. Sync this dtsi from linux-next v5.7-rc1. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- .../dts/rockchip-radxa-dalang-carrier.dtsi | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi new file mode 100644 index 0000000000..df3712aedf --- /dev/null +++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + hym8563: hym8563 at 51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + vqmmc-supply = <&vccio_sd>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = + <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; +}; From patchwork Wed Jul 8 10:05:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241037 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:25 +0530 Subject: [PATCH v2 4/7] arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-5-jagan@amarulasolutions.com> Rock Pi N10 is a Rockchip RK3399Pro based SBC, which has - VMARC RK3399Pro SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VAMRC RK3399Pro SOM need to mount on top of radxa dalang carrier board for making Rock Pi N10 SBC. So, add initial support for Rock Pi N10 by including rk3399, rk3399pro vamrc-som and raxda dalang carrier board dtsi files. rk3399pro-rock-pi-n10.dts was synced from linux-next v5.7-rc1. Tested - ROCK PI N10 Model B - ROCK PI N10 Model C - Boot from SD Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 +- .../arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399pro-rock-pi-n10.dts | 18 ++++++++ arch/arm/dts/rk3399pro-u-boot.dtsi | 6 +++ board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/rock-pi-n10-rk3399pro_defconfig | 46 +++++++++++++++++++ 6 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399pro-rock-pi-n10.dts create mode 100644 arch/arm/dts/rk3399pro-u-boot.dtsi create mode 100644 configs/rock-pi-n10-rk3399pro_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 89fa448818..36f3dc6db8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -136,7 +136,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-roc-pc-mezzanine.dtb \ rk3399-rock-pi-4.dtb \ rk3399-rock960.dtb \ - rk3399-rockpro64.dtb + rk3399-rockpro64.dtb \ + rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi new file mode 100644 index 0000000000..946a0230db --- /dev/null +++ b/arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399pro-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts b/arch/arm/dts/rk3399pro-rock-pi-n10.dts new file mode 100644 index 0000000000..6ac2d4d721 --- /dev/null +++ b/arch/arm/dts/rk3399pro-rock-pi-n10.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399pro-vmarc-som.dtsi" +#include + +/ { + model = "Radxa ROCK Pi N10"; + compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som", + "rockchip,rk3399pro"; +}; diff --git a/arch/arm/dts/rk3399pro-u-boot.dtsi b/arch/arm/dts/rk3399pro-u-boot.dtsi new file mode 100644 index 0000000000..7bddc3acdb --- /dev/null +++ b/arch/arm/dts/rk3399pro-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-u-boot.dtsi" diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 792df1087f..578638a58b 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -68,3 +68,9 @@ M: Jagan Teki S: Maintained F: configs/rock-pi-4-rk3399_defconfig F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi + +ROCK-PI-N10 +M: Jagan Teki +S: Maintained +F: configs/rock-pi-n10-rk3399pro_defconfig +F: arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig new file mode 100644 index 0000000000..c705ce01ce --- /dev/null +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -0,0 +1,46 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" +CONFIG_MISC_INIT_R=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y From patchwork Wed Jul 8 10:05:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241038 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:26 +0530 Subject: [PATCH v2 5/7] arm64: dts: rockchip: Trivial cleanups for RockPI N10 In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-6-jagan@amarulasolutions.com> Radxa dalang carrier boards are used to mount vmarc SoM's of rk3399pro and rk3288 to make complete SBC. So, this patch adds trivial changes to properties. - move common properties into radxa dalang carrier dtsi. - maintain ascending order for nodes, properties. - change the order of dtsi include so-that common properties will reflect in main dts. - drop unnecessary header includes. No functionally changes. Signed-off-by: Jagan Teki --- arch/arm/dts/rk3399pro-rock-pi-n10.dts | 2 +- arch/arm/dts/rk3399pro-vmarc-som.dtsi | 98 ++++++++++--------- .../dts/rockchip-radxa-dalang-carrier.dtsi | 67 ++++++------- 3 files changed, 85 insertions(+), 82 deletions(-) diff --git a/arch/arm/dts/rk3399pro-rock-pi-n10.dts b/arch/arm/dts/rk3399pro-rock-pi-n10.dts index 6ac2d4d721..8001635182 100644 --- a/arch/arm/dts/rk3399pro-rock-pi-n10.dts +++ b/arch/arm/dts/rk3399pro-rock-pi-n10.dts @@ -8,8 +8,8 @@ /dts-v1/; #include "rk3399.dtsi" #include "rk3399-opp.dtsi" -#include "rk3399pro-vmarc-som.dtsi" #include +#include "rk3399pro-vmarc-som.dtsi" / { model = "Radxa ROCK Pi N10"; diff --git a/arch/arm/dts/rk3399pro-vmarc-som.dtsi b/arch/arm/dts/rk3399pro-vmarc-som.dtsi index 0a516334f1..63eb498b36 100644 --- a/arch/arm/dts/rk3399pro-vmarc-som.dtsi +++ b/arch/arm/dts/rk3399pro-vmarc-som.dtsi @@ -7,35 +7,12 @@ #include #include -#include / { compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clkin_gmac"; - #clock-cells = <0>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; + chosen { + stdout-path = "serial2:1500000n8"; }; }; @@ -61,17 +38,13 @@ &gmac { assigned-clocks = <&cru SCLK_RMII_SRC>; - assigned-clock-parents = <&clkin_gmac>; - clock_in_out = "input"; phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - tx_delay = <0x28>; - rx_delay = <0x11>; +}; + +&hym8563 { + interrupt-parent = <&gpio4>; + interrupts = ; }; &i2c0 { @@ -297,16 +270,53 @@ }; }; -&io_domains { +&i2c1 { + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; status = "okay"; + + hym8563: hym8563 at 51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + }; +}; + +&io_domains { bt656-supply = <&vcca_1v8>; sdmmc-supply = <&vccio_sd>; gpio1830-supply = <&vccio_3v0>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; + }; + }; }; &pmu_io_domains { - status = "okay"; pmu1830-supply = <&vcc_1v8>; + status = "okay"; }; &sdhci { @@ -317,17 +327,13 @@ status = "okay"; }; +&sdmmc { + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + max-frequency = <150000000>; +}; + &tsadc { - status = "okay"; rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <1>; -}; - -&pinctrl { - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = - <1 RK_PC2 0 &pcfg_pull_up>; - }; - }; + status = "okay"; }; diff --git a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi index df3712aedf..450e5bb5af 100644 --- a/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi @@ -8,36 +8,44 @@ #include / { - chosen { - stdout-path = "serial2:1500000n8"; + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; }; -}; -&gmac { - status = "okay"; -}; + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; -&i2c1 { - status = "okay"; - i2c-scl-rising-time-ns = <140>; - i2c-scl-falling-time-ns = <30>; + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; }; -&i2c2 { +&gmac { + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; - clock-frequency = <400000>; - - hym8563: hym8563 at 51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio4>; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>; - }; }; &pwm0 { @@ -52,10 +60,8 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; vqmmc-supply = <&vccio_sd>; - max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; status = "okay"; @@ -70,12 +76,3 @@ &uart2 { status = "okay"; }; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = - <4 RK_PD6 0 &pcfg_pull_up>; - }; - }; -}; From patchwork Wed Jul 8 10:05:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241039 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:27 +0530 Subject: [PATCH v2 6/7] ARM: dts: rockchip: Add VMARC RK3288 SOM initial support In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-7-jagan@amarulasolutions.com> VMARC RK3288 SOM is a standard SMARC SOM design with Rockchip RK3288 SoC, which is designed by Vamrs. Specification: - Rockchip RK3288 - PMIC: RK808 - eMMC: 16GB/32GB/64GB - SD slot - 2xUSB-2.0, 1xUSB3.0 - USB-C for power supply - Ethernet - HDMI, MIPI-DSI/CSI, eDP Add initial support for VMARC RK3288 SOM, this would use with associated carrier board. Signed-off-by: Jagan Teki --- arch/arm/dts/rk3288-vmarc-som.dtsi | 270 +++++++++++++++++++++++++++++ 1 file changed, 270 insertions(+) create mode 100644 arch/arm/dts/rk3288-vmarc-som.dtsi diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi new file mode 100644 index 0000000000..0bcb9f067d --- /dev/null +++ b/arch/arm/dts/rk3288-vmarc-som.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include +#include + +/ { + compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288"; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + phy-supply = <&vcc_io>; + snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic at 1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_codec: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&io_domains { + bb-supply = <&vcc_io>; + flash0-supply = <&vccio_flash>; + gpio1830-supply = <&vcc_18>; + gpio30-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>, + <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>; + }; + }; +}; From patchwork Wed Jul 8 10:05:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 241040 List-Id: U-Boot discussion From: jagan at amarulasolutions.com (Jagan Teki) Date: Wed, 8 Jul 2020 15:35:28 +0530 Subject: [PATCH v2 7/7] ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support In-Reply-To: <20200708100528.419035-1-jagan@amarulasolutions.com> References: <20200708100528.419035-1-jagan@amarulasolutions.com> Message-ID: <20200708100528.419035-8-jagan@amarulasolutions.com> Rock Pi N8 is a Rockchip RK3288 based SBC, which has - VMARC RK3288 SOM (as per SMARC standard) from Vamrs. - Compatible carrier board from Radxa. VAMRC RK3288 SOM need to mount on top of radxa dalang carrier board for making Rock Pi N8 SBC. So, add initial support for Rock Pi N8 by including rk3288, rk3288 vamrc-som and raxda dalang carrier board dtsi files. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi | 39 +++++++++++++ arch/arm/dts/rk3288-rock-pi-n8.dts | 17 ++++++ arch/arm/dts/rk3288-vmarc-som.dtsi | 9 --- board/rockchip/evb_rk3288/MAINTAINERS | 6 ++ configs/rock-pi-n8-rk3288_defconfig | 66 ++++++++++++++++++++++ 6 files changed, 129 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi create mode 100644 arch/arm/dts/rk3288-rock-pi-n8.dts create mode 100644 configs/rock-pi-n8-rk3288_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 36f3dc6db8..befa9554a8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -91,6 +91,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-miqi.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ + rk3288-rock-pi-n8.dtb \ rk3288-rock2-square.dtb \ rk3288-tinker.dtb \ rk3288-tinker-s.dtb \ diff --git a/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi new file mode 100644 index 0000000000..538607dd73 --- /dev/null +++ b/arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Jagan Teki + */ + +#include "rk3288-u-boot.dtsi" + +/{ + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-rock-pi-n8.dts b/arch/arm/dts/rk3288-rock-pi-n8.dts new file mode 100644 index 0000000000..c9894a60e7 --- /dev/null +++ b/arch/arm/dts/rk3288-rock-pi-n8.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3288.dtsi" +#include +#include "rk3288-vmarc-som.dtsi" + +/ { + model = "Radxa ROCK Pi N8"; + compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som", + "rockchip,rk3288"; +}; diff --git a/arch/arm/dts/rk3288-vmarc-som.dtsi b/arch/arm/dts/rk3288-vmarc-som.dtsi index 0bcb9f067d..0e609e7fd3 100644 --- a/arch/arm/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/dts/rk3288-vmarc-som.dtsi @@ -225,15 +225,6 @@ }; }; -&io_domains { - bb-supply = <&vcc_io>; - flash0-supply = <&vccio_flash>; - gpio1830-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - status = "okay"; -}; - &pinctrl { pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { drive-strength = <8>; diff --git a/board/rockchip/evb_rk3288/MAINTAINERS b/board/rockchip/evb_rk3288/MAINTAINERS index 8a4f127f88..9bd6b1e8a4 100644 --- a/board/rockchip/evb_rk3288/MAINTAINERS +++ b/board/rockchip/evb_rk3288/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3288 F: include/configs/evb_rk3288.h F: configs/evb-rk3288_defconfig + +ROCK-PI-N8 +M: Jagan Teki +S: Maintained +F: configs/rock-pi-n8-rk3288_defconfig +F: arch/arm/dts/rk3288-rock-pi-n8-u-boot.dtsi diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig new file mode 100644 index 0000000000..6b31e19eda --- /dev/null +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00100000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_EVB_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_USE_PREBOOT=y +CONFIG_SILENT_CONSOLE=y +CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_CMD_SPL=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock-pi-n8" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y