From patchwork Wed Oct 4 18:20:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 114791 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3431505qgn; Wed, 4 Oct 2017 11:20:45 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCA8Oi7WnFr9zdiisYRPK5gYQUVzb6wEeyiMcxS9PyBK4smBm4Gi5ZTisAcC+F9kBl7LY5g X-Received: by 10.98.65.156 with SMTP id g28mr3265837pfd.341.1507141245462; Wed, 04 Oct 2017 11:20:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507141245; cv=none; d=google.com; s=arc-20160816; b=DOLjggBS5mA8Rpq6sab/7jLs9V88KIOKKGBWbyMCRpuBtEfEKOQiqTUHib3Sd9FiqU gGwAgBJSYC6GmgmsATzt8UgIGOUVEJ/1DrfOquO0ZIPYTS+FQt10l3bgIAdUOiflKJqG 9ssaIoAnlSyhPR3EHs6JvQQ2Rjz5xFugPnHyH20yVjpIhV0SeCG1wcVvPxt+Bk2jR0pC yTDls5gZmhRHmxuCUUAvOn9MjtToPQka5ablYFOC1i5LlUPxav9tA4ocjDrmqE8qqdPj 4Zuq1T103PsGKxQVWkmRDJIVtXhUwOSR177+rH61lWDRAo4yXgOuv/k1O9AZP2389WUC uYSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature:arc-authentication-results; bh=E+4JeJx1DUsI1pxfdq+neEEtIt+p4Boz2DwfD4z8CgE=; b=eAYkk/xovkH29iupsM1vK3NmI+PW2tQocPEGmL5S7eDJJQDxBCe3lFRs3qynfBmUkb D17PdRHYuXOlCC/g0iZqQ7wzuP3rkNvSL3PODDqxn02DCfmC9jnkP25UHSvQ8U2Z5lgB j8WwxCOV2QHh/ceFF3u7QVdWFa3yLg96dDoPtrrKWVM/4/40ldcUWuxPmAA8oF6yElJM 3fN0EPmDHNSY8w5l8MawUZZfphN7r+IDdnolSAuDyZkOhr/xJnf6klvQNyVbIK7b8uMf jBu3w4un5X2RN5gh11Xlj1PjRsWpaULstvQMSpk+bcfaH0BJFJfL+B7VoDPsBlIjADDe eoYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B9sK7C6d; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g10si11851167pgs.45.2017.10.04.11.20.45; Wed, 04 Oct 2017 11:20:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B9sK7C6d; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751195AbdJDSUn (ORCPT + 8 others); Wed, 4 Oct 2017 14:20:43 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:59369 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750951AbdJDSUl (ORCPT ); Wed, 4 Oct 2017 14:20:41 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v94IKXRk008199; Wed, 4 Oct 2017 13:20:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507141233; bh=RsHZAqNr5qBltDXT/EUPzonRWCQPnp4w+BP86NuyDDA=; h=From:To:CC:Subject:Date; b=B9sK7C6d7sLFb0u5Ubue6XQFiA6GqHASik/YhTGPzItAxRiDI/S6M4tF03L36sNum IRnEfQK6mn1veLfzZjzGIzZRfFUt6onpYMa6wyE5tg3WUgjRPLUDRkKRTmU/oLYEya 3IKf0HC1MkQGH3QXIbtybnIvCIy+OW1ZQImc4FlI= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v94IKXxe023979; Wed, 4 Oct 2017 13:20:33 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 4 Oct 2017 13:20:33 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 4 Oct 2017 13:20:33 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v94IKXxB004028; Wed, 4 Oct 2017 13:20:33 -0500 Received: from localhost ([172.22.138.27]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v94IKX315962; Wed, 4 Oct 2017 13:20:33 -0500 (CDT) From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH 1/3 v2] net: phy: Remove TI DP83822 from DP83848 driver Date: Wed, 4 Oct 2017 13:20:29 -0500 Message-ID: <20171004182031.13794-1-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Removing the DP83822 device from the DP83848 to support the TI DP83822 dedicated driver that will initially support WoL settings. Signed-off-by: Dan Murphy --- v2 - There was no v1 on this patch this is new. drivers/net/phy/dp83848.c | 3 --- 1 file changed, 3 deletions(-) -- 2.14.0 diff --git a/drivers/net/phy/dp83848.c b/drivers/net/phy/dp83848.c index 3de4fe4dda77..3966d43c5146 100644 --- a/drivers/net/phy/dp83848.c +++ b/drivers/net/phy/dp83848.c @@ -20,7 +20,6 @@ #define TI_DP83620_PHY_ID 0x20005ce0 #define NS_DP83848C_PHY_ID 0x20005c90 #define TLK10X_PHY_ID 0x2000a210 -#define TI_DP83822_PHY_ID 0x2000a240 /* Registers */ #define DP83848_MICR 0x11 /* MII Interrupt Control Register */ @@ -80,7 +79,6 @@ static struct mdio_device_id __maybe_unused dp83848_tbl[] = { { NS_DP83848C_PHY_ID, 0xfffffff0 }, { TI_DP83620_PHY_ID, 0xfffffff0 }, { TLK10X_PHY_ID, 0xfffffff0 }, - { TI_DP83822_PHY_ID, 0xfffffff0 }, { } }; MODULE_DEVICE_TABLE(mdio, dp83848_tbl); @@ -110,7 +108,6 @@ static struct phy_driver dp83848_driver[] = { DP83848_PHY_DRIVER(NS_DP83848C_PHY_ID, "NS DP83848C 10/100 Mbps PHY"), DP83848_PHY_DRIVER(TI_DP83620_PHY_ID, "TI DP83620 10/100 Mbps PHY"), DP83848_PHY_DRIVER(TLK10X_PHY_ID, "TI TLK10X 10/100 Mbps PHY"), - DP83848_PHY_DRIVER(TI_DP83822_PHY_ID, "TI DP83822 10/100 Mbps PHY"), }; module_phy_driver(dp83848_driver); From patchwork Wed Oct 4 18:20:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 114793 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3431702qgn; Wed, 4 Oct 2017 11:20:54 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDS5Y90rfBkkZrxyEUC2hatIGq/Au/PleWzQBiZ0BQC7HJHX/pR9WwVDlA64jDB6outBfz2 X-Received: by 10.159.246.8 with SMTP id b8mr20292201pls.252.1507141254231; Wed, 04 Oct 2017 11:20:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507141254; cv=none; d=google.com; s=arc-20160816; b=oiJ25ta7aTX2A4zqt4EuzHdolkdx1unrp1jVClEy9In5NPb6ZtPM0RbtS855+MlBAD xK79i7AbLLeBnkATKL5PJgeECn5nISdUjoPIXun4qw1HRS3fbhLtUaX6dlQYTrd8U2Y9 FcYzOBpHWe/XsTJvmLvBHHG6bx0cbrNurRyhce+vCPGkb+wvtdCTjELBJEWHHS12+7R0 2q9RLZIfz9WFWlDEjoM8Q90mCyaNQQ7ahEnW3ZRUcF7Y8vseMrZDKhP6/HtxiZaHpnbC /6Uq7AQf/YO15Wc6vtpO1abR3vieP5aAgyA80W1dJH90HiPgBoAVLkuoRa/eLxKw1GkP o/PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=89/m2qoFn9EN3GypMz4OCZZu8ttJ9DA8ZU9dqXnpOeg=; b=iMXtccMhkz31sjUFfN5k+DSmjv5ETGG6vdVoqSFPv2wAYL5mr/Dn9/ZMri8XVicTK/ UIsXkmfl5bWtmiLGYX57xRSRFZqT8qdyKSdpuqkRPwYA1AcX5xb8zopfFGiyLVdaIcZn c7paqI56qbYLQsiq74gX5v0sg0BjzH/87/PFcI15TeUQAOHEP1LR74DGVWYN30bNHr67 q0iqxaEk2KoTZ9x05j7CTmo8aGF9ek78nmRklFzCUJ99iPsTzWBSukwqcprmmhlr780L zjHX5wCjhsmmpyb9Jw4fJQ44hRFvYeqOZ+YWBQXR2aPtiqe7IDDoakIOAWl4xker2/SD vF3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Rhbvjo34; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g10si11851167pgs.45.2017.10.04.11.20.53; Wed, 04 Oct 2017 11:20:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Rhbvjo34; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751169AbdJDSUm (ORCPT + 8 others); Wed, 4 Oct 2017 14:20:42 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:59370 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750779AbdJDSUl (ORCPT ); Wed, 4 Oct 2017 14:20:41 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v94IKY2p008207; Wed, 4 Oct 2017 13:20:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507141234; bh=4uOcmOs5Fk+wOUQGPpfcc+Ugcjq9d1I81a0Lv4I5sy4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Rhbvjo34fkXgTjngpFsCi8NU/jbtKEox1wxkbMUcwDxw7Ix4Ym2TrVjpUClovTOF+ fW83trJuiHWkVQEyQBFTsVAOQVaXSzUHHNHJF+/rWEGLpyqEBSaGaLmwHv2apiKFuL RrgcR4/tGrBdv+ntjc68OfXHHb+c1elFwkiMFjkI= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v94IKYlA028469; Wed, 4 Oct 2017 13:20:34 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 4 Oct 2017 13:20:33 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 4 Oct 2017 13:20:33 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v94IKXeD014454; Wed, 4 Oct 2017 13:20:33 -0500 Received: from localhost ([172.22.138.27]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v94IKX315967; Wed, 4 Oct 2017 13:20:33 -0500 (CDT) From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH 2/3 v2] net: phy: DP83822 initial driver submission Date: Wed, 4 Oct 2017 13:20:30 -0500 Message-ID: <20171004182031.13794-2-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20171004182031.13794-1-dmurphy@ti.com> References: <20171004182031.13794-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for the TI DP83822 10/100Mbit ethernet phy. The DP83822 provides flexibility to connect to a MAC through a standard MII, RMII or RGMII interface. Datasheet: http://www.ti.com/product/DP83822I/datasheet Signed-off-by: Dan Murphy --- v2 - Updated per comments. Removed unnessary parantheis, called genphy_suspend/ resume routines and then performing WoL changes, reworked sopass storage and reduced the number of phy reads, and moved WOL_SECURE_ON - https://www.mail-archive.com/netdev@vger.kernel.org/msg191392.html drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83822.c | 306 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 312 insertions(+) create mode 100644 drivers/net/phy/dp83822.c -- 2.14.0 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index cd931cf9dcc2..8e78a482e09e 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -277,6 +277,11 @@ config DAVICOM_PHY ---help--- Currently supports dm9161e and dm9131 +config DP83822_PHY + tristate "Texas Instruments DP83822 PHY" + ---help--- + Supports the DP83822 PHY. + config DP83848_PHY tristate "Texas Instruments DP83848 PHY" ---help--- diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 416df92fbf4f..df3b82ba8550 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CICADA_PHY) += cicada.o obj-$(CONFIG_CORTINA_PHY) += cortina.o obj-$(CONFIG_DAVICOM_PHY) += davicom.o obj-$(CONFIG_DP83640_PHY) += dp83640.o +obj-$(CONFIG_DP83822_PHY) += dp83822.o obj-$(CONFIG_DP83848_PHY) += dp83848.o obj-$(CONFIG_DP83867_PHY) += dp83867.o obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c new file mode 100644 index 000000000000..200a0e39756e --- /dev/null +++ b/drivers/net/phy/dp83822.c @@ -0,0 +1,306 @@ +/* + * Driver for the Texas Instruments DP83822 PHY + * + * Copyright (C) 2017 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DP83822_PHY_ID 0x2000a240 +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_MISR1 0x12 +#define MII_DP83822_MISR2 0x13 +#define MII_DP83822_RESET_CTRL 0x1f + +#define DP83822_HW_RESET BIT(15) +#define DP83822_SW_RESET BIT(14) + +/* MISR1 bits */ +#define DP83822_RX_ERR_HF_INT_EN BIT(0) +#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) +#define DP83822_ANEG_COMPLETE_INT_EN BIT(2) +#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) +#define DP83822_SPEED_CHANGED_INT_EN BIT(4) +#define DP83822_LINK_STAT_INT_EN BIT(5) +#define DP83822_ENERGY_DET_INT_EN BIT(6) +#define DP83822_LINK_QUAL_INT_EN BIT(7) + +/* MISR2 bits */ +#define DP83822_JABBER_DET_INT_EN BIT(0) +#define DP83822_WOL_PKT_INT_EN BIT(1) +#define DP83822_SLEEP_MODE_INT_EN BIT(2) +#define DP83822_MDI_XOVER_INT_EN BIT(3) +#define DP83822_LB_FIFO_INT_EN BIT(4) +#define DP83822_PAGE_RX_INT_EN BIT(5) +#define DP83822_ANEG_ERR_INT_EN BIT(6) +#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) + +/* INT_STAT1 bits */ +#define DP83822_WOL_INT_EN BIT(4) +#define DP83822_WOL_INT_STAT BIT(12) + +#define MII_DP83822_RXSOP1 0x04a5 +#define MII_DP83822_RXSOP2 0x04a6 +#define MII_DP83822_RXSOP3 0x04a7 + +/* WoL Registers */ +#define MII_DP83822_WOL_CFG 0x04a0 +#define MII_DP83822_WOL_STAT 0x04a1 +#define MII_DP83822_WOL_DA1 0x04a2 +#define MII_DP83822_WOL_DA2 0x04a3 +#define MII_DP83822_WOL_DA3 0x04a4 + +/* WoL bits */ +#define DP83822_WOL_MAGIC_EN BIT(1) +#define DP83822_WOL_SECURE_ON BIT(5) +#define DP83822_WOL_EN BIT(7) +#define DP83822_WOL_INDICATION_SEL BIT(8) +#define DP83822_WOL_CLR_INDICATION BIT(11) + +static int dp83822_ack_interrupt(struct phy_device *phydev) +{ + int err = phy_read(phydev, MII_DP83822_MISR1); + + if (err < 0) + return err; + + err = phy_read(phydev, MII_DP83822_MISR2); + if (err < 0) + return err; + + return 0; +} + +static int dp83822_set_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + struct net_device *ndev = phydev->attached_dev; + u16 value; + const u8 *mac; + + if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { + mac = (const u8 *)ndev->dev_addr; + + if (!is_valid_ether_addr(mac)) + return -EINVAL; + + /* MAC addresses start with byte 5, but stored in mac[0]. + * 822 PHYs store bytes 4|5, 2|3, 0|1 + */ + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_DA1, (mac[1] << 8) | mac[0]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_DA2, (mac[3] << 8) | mac[2]); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, + (mac[5] << 8) | mac[4]); + + value = phy_read_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_CFG); + if (wol->wolopts & WAKE_MAGIC) + value |= DP83822_WOL_MAGIC_EN; + else + value &= ~DP83822_WOL_MAGIC_EN; + + if (wol->wolopts & WAKE_MAGICSECURE) { + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP1, + (wol->sopass[1] << 8) | wol->sopass[0]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP2, + (wol->sopass[3] << 8) | wol->sopass[2]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP3, + (wol->sopass[5] << 8) | wol->sopass[4]); + value |= DP83822_WOL_SECURE_ON; + } else { + value &= ~DP83822_WOL_SECURE_ON; + } + + value |= (DP83822_WOL_EN | DP83822_WOL_CLR_INDICATION | + DP83822_WOL_CLR_INDICATION); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, + value); + } else { + value = phy_read_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_CFG); + value &= ~DP83822_WOL_EN; + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, + value); + } + + return 0; +} + +static void dp83822_get_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + int value; + u16 sopass_val; + + wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); + wol->wolopts = 0; + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + if (value & DP83822_WOL_MAGIC_EN) + wol->wolopts |= WAKE_MAGIC; + + if (~value & DP83822_WOL_CLR_INDICATION) + wol->wolopts = 0; + + if (value & DP83822_WOL_SECURE_ON) { + wol->wolopts |= WAKE_MAGICSECURE; + } else { + wol->wolopts &= ~WAKE_MAGICSECURE; + return; + } + + sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP1); + wol->sopass[0] = (sopass_val & 0xff); + wol->sopass[1] = (sopass_val >> 8); + + sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP2); + wol->sopass[2] = (sopass_val & 0xff); + wol->sopass[3] = (sopass_val >> 8); + + sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP3); + wol->sopass[4] = (sopass_val & 0xff); + wol->sopass[5] = (sopass_val >> 8); +} + +static int dp83822_config_intr(struct phy_device *phydev) +{ + int misr_status; + int err; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { + misr_status = phy_read(phydev, MII_DP83822_MISR1); + if (misr_status < 0) + return misr_status; + + misr_status |= (DP83822_RX_ERR_HF_INT_EN | + DP83822_FALSE_CARRIER_HF_INT_EN | + DP83822_ANEG_COMPLETE_INT_EN | + DP83822_DUP_MODE_CHANGE_INT_EN | + DP83822_SPEED_CHANGED_INT_EN | + DP83822_LINK_STAT_INT_EN | + DP83822_ENERGY_DET_INT_EN | + DP83822_LINK_QUAL_INT_EN); + + err = phy_write(phydev, MII_DP83822_MISR1, misr_status); + if (err < 0) + return err; + + misr_status = phy_read(phydev, MII_DP83822_MISR2); + if (misr_status < 0) + return misr_status; + + misr_status |= (DP83822_JABBER_DET_INT_EN | + DP83822_WOL_PKT_INT_EN | + DP83822_SLEEP_MODE_INT_EN | + DP83822_MDI_XOVER_INT_EN | + DP83822_LB_FIFO_INT_EN | + DP83822_PAGE_RX_INT_EN | + DP83822_ANEG_ERR_INT_EN | + DP83822_EEE_ERROR_CHANGE_INT_EN); + + err = phy_write(phydev, MII_DP83822_MISR2, misr_status); + } else { + err = phy_write(phydev, MII_DP83822_MISR1, 0); + if (err < 0) + return err; + + err = phy_write(phydev, MII_DP83822_MISR1, 0); + } + + return err; +} + +static int dp83822_phy_reset(struct phy_device *phydev) +{ + int err; + + err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_HW_RESET); + if (err < 0) + return err; + + return 0; +} + +static int dp83822_suspend(struct phy_device *phydev) +{ + int value; + + mutex_lock(&phydev->lock); + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + mutex_unlock(&phydev->lock); + + if (!(value & DP83822_WOL_EN)) + genphy_suspend(phydev); + + return 0; +} + +static int dp83822_resume(struct phy_device *phydev) +{ + int value; + + genphy_resume(phydev); + + mutex_lock(&phydev->lock); + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | + DP83822_WOL_CLR_INDICATION); + + mutex_unlock(&phydev->lock); + + return 0; +} + +static struct phy_driver dp83822_driver[] = { + { + .phy_id = DP83822_PHY_ID, + .phy_id_mask = 0xfffffff0, + .name = "TI DP83822", + .features = PHY_BASIC_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_init = genphy_config_init, + .soft_reset = dp83822_phy_reset, + .get_wol = dp83822_get_wol, + .set_wol = dp83822_set_wol, + .ack_interrupt = dp83822_ack_interrupt, + .config_intr = dp83822_config_intr, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .suspend = dp83822_suspend, + .resume = dp83822_resume, + }, +}; +module_phy_driver(dp83822_driver); + +static struct mdio_device_id __maybe_unused dp83822_tbl[] = { + { DP83822_PHY_ID, 0xfffffff0 }, + { }, +}; +MODULE_DEVICE_TABLE(mdio, dp83822_tbl); + +MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); +MODULE_AUTHOR("Dan Murphy X-Patchwork-Id: 114792 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3431551qgn; Wed, 4 Oct 2017 11:20:47 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBULBXtZB5DtYg5j9MVAEgfYGsAPSkc4PcuI9U4uA0pYeoUYHlfsP8khAvzTh6GbPGan9U+ X-Received: by 10.99.116.22 with SMTP id p22mr11591113pgc.372.1507141247603; Wed, 04 Oct 2017 11:20:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507141247; cv=none; d=google.com; s=arc-20160816; b=tY/0au2wOkTLXY+Syt/s1va0ynwePu+M5bqCqmpCKzK2XUw9L+fVvP8I1H6uIgiOUf +unTP7tewYqpClV7Hnll9l+BYstsRsUK5L8aV400/eUyUFrmxUxcZtyICXkIwHgqJ+O0 ssIX+6JOV+rXBEEBOsMM/YXpVPjERyx0UqRwj4E7tQvGF7P1c/cfLKK/oA8NU3BzPPjw z+Qb/b1wxG4mZ8LqJhsEOimRpKxANnIbFy9eWC8T02NPzXVi3aiI+0kChePOviae0CdK mHXnAi4GCmj9j1GfccUkGtVyI3AAcPZeciJl4VgwohQE4frXYXuVpUPfaSOmUy3+xa5G GxtQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id g10si11851167pgs.45.2017.10.04.11.20.47; Wed, 04 Oct 2017 11:20:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xcpB+m8P; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751209AbdJDSUp (ORCPT + 8 others); Wed, 4 Oct 2017 14:20:45 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:24915 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751177AbdJDSUn (ORCPT ); Wed, 4 Oct 2017 14:20:43 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v94IKYTm022063; Wed, 4 Oct 2017 13:20:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507141234; bh=beT55en7Sn46HAtoh4o4Y4W7jG9B4jLy0LYw+S5i51I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xcpB+m8PUaTJNcbv6MTYZWiBwd/QOzz+pGP/JIT8boCzKW0VQ54M7WnEB88VFfzx6 UzBKKyPFil9L5Mr3SEQ6YT/7Jrpmf0UfrPYba7Va7kTM7BThWhNXsxqaa3YrdoIhGG aqXrX27rcJcs9/yksedItiiRHykbSoLpPogWaeHU= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v94IKYTR024020; Wed, 4 Oct 2017 13:20:34 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 4 Oct 2017 13:20:34 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 4 Oct 2017 13:20:34 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v94IKYJ0004069; Wed, 4 Oct 2017 13:20:34 -0500 Received: from localhost ([172.22.138.27]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v94IKY315971; Wed, 4 Oct 2017 13:20:34 -0500 (CDT) From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH 3/3 v2] net: phy: Change error to EINVAL for invalid MAC Date: Wed, 4 Oct 2017 13:20:31 -0500 Message-ID: <20171004182031.13794-3-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20171004182031.13794-1-dmurphy@ti.com> References: <20171004182031.13794-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Change the return error code to EINVAL if the MAC address is not valid in the set_wol function. Signed-off-by: Dan Murphy --- v2 - There was no v1 on this patch this is new. drivers/net/phy/at803x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.0 diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c1e52b9dc58d..5f93e6add563 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -167,7 +167,7 @@ static int at803x_set_wol(struct phy_device *phydev, mac = (const u8 *) ndev->dev_addr; if (!is_valid_ether_addr(mac)) - return -EFAULT; + return -EINVAL; for (i = 0; i < 3; i++) { phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,