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Thu, 05 Oct 2017 17:50:56 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.50.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:50:56 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:40 -0700 Message-Id: <79796969192ddd9bebbb7bc4647208443278154f.1507250774.git.raj.khem@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 01/10] site: Add riscv32 and riscv64 X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Signed-off-by: Khem Raj --- meta/site/riscv32-linux | 4 ++++ meta/site/riscv64-linux | 4 ++++ 2 files changed, 8 insertions(+) create mode 100644 meta/site/riscv32-linux create mode 100644 meta/site/riscv64-linux -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux new file mode 100644 index 0000000000..a496bd1aca --- /dev/null +++ b/meta/site/riscv32-linux @@ -0,0 +1,4 @@ +# glib-2.0 +glib_cv_stack_grows=${glib_cv_stack_grows=no} +glib_cv_uscore=${glib_cv_uscore=no} + diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux new file mode 100644 index 0000000000..a496bd1aca --- /dev/null +++ b/meta/site/riscv64-linux @@ -0,0 +1,4 @@ +# glib-2.0 +glib_cv_stack_grows=${glib_cv_stack_grows=no} +glib_cv_uscore=${glib_cv_uscore=no} + From patchwork Fri Oct 6 00:50:41 2017 Content-Type: text/plain; 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Thu, 05 Oct 2017 17:50:57 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.50.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:50:57 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:41 -0700 Message-Id: X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 02/10] insane: Add entries for riscv 32bit/64bit X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Signed-off-by: Khem Raj --- meta/classes/insane.bbclass | 4 ++++ 1 file changed, 4 insertions(+) -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/classes/insane.bbclass b/meta/classes/insane.bbclass index 0a3b528ddb..def9c707a4 100644 --- a/meta/classes/insane.bbclass +++ b/meta/classes/insane.bbclass @@ -94,6 +94,8 @@ def package_qa_get_machine_dict(d): "mipsisa64r6": ( 8, 0, 0, False, 64), "mipsisa64r6el": ( 8, 0, 0, True, 64), "nios2": (113, 0, 0, True, 32), + "riscv": (243, 0, 0, True, 32), + "riscv64": (243, 0, 0, True, 64), "s390": (22, 0, 0, False, 32), "sh4": (42, 0, 0, True, 32), "sparc": ( 2, 0, 0, False, 32), @@ -119,6 +121,8 @@ def package_qa_get_machine_dict(d): "microblaze": (189, 0, 0, False, 32), "microblazeeb":(189, 0, 0, False, 32), "microblazeel":(189, 0, 0, True, 32), + "riscv": (243, 0, 0, True, 32), + "riscv64": (243, 0, 0, True, 64), "sh4": ( 42, 0, 0, True, 32), }, "uclinux-uclibc" : { From patchwork Fri Oct 6 00:50:42 2017 Content-Type: text/plain; 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Thu, 05 Oct 2017 17:50:59 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.50.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:50:58 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:42 -0700 Message-Id: <794e2c27270d2d908672bf4f6bab747e3ff47fd2.1507250774.git.raj.khem@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 03/10] siteinfo: Define data for riscv32 and riscv64 X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Signed-off-by: Khem Raj --- meta/classes/siteinfo.bbclass | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/classes/siteinfo.bbclass b/meta/classes/siteinfo.bbclass index 1aada40695..29cd2aa82b 100644 --- a/meta/classes/siteinfo.bbclass +++ b/meta/classes/siteinfo.bbclass @@ -47,6 +47,8 @@ def siteinfo_data(d): "ppc": "endian-big bit-32 powerpc-common", "ppc64": "endian-big bit-64 powerpc-common", "ppc64le" : "endian-little bit-64 powerpc-common", + "riscv32": "endian-little bit-32 riscv-common", + "riscv64": "endian-little bit-64 riscv-common", "sh3": "endian-little bit-32 sh-common", "sh4": "endian-little bit-32 sh-common", "sparc": "endian-big bit-32", @@ -95,6 +97,10 @@ def siteinfo_data(d): "powerpc64-linux-muslspe": "powerpc-linux powerpc64-linux", "powerpc64-linux": "powerpc-linux", "powerpc64-linux-musl": "powerpc-linux", + "riscv32-linux": "riscv32-linux", + "riscv32-linux-musl": "riscv32-linux", + "riscv64-linux": "riscv64-linux", + "riscv64-linux-musl": "riscv64-linux", "x86_64-cygwin": "bit-64", "x86_64-darwin": "bit-64", "x86_64-darwin9": "bit-64", From patchwork Fri Oct 6 00:50:43 2017 Content-Type: text/plain; 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Thu, 05 Oct 2017 17:51:00 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.50.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:50:59 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:43 -0700 Message-Id: X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 04/10] kernel-arch.bbclass: Add riscv to kernel arch map X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Signed-off-by: Khem Raj --- meta/classes/kernel-arch.bbclass | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/classes/kernel-arch.bbclass b/meta/classes/kernel-arch.bbclass index d036fcf20c..cf0edb6173 100644 --- a/meta/classes/kernel-arch.bbclass +++ b/meta/classes/kernel-arch.bbclass @@ -14,7 +14,7 @@ valid_archs = "alpha cris ia64 \ parisc s390 v850 \ avr32 blackfin \ microblaze \ - nios2 arc xtensa" + nios2 arc riscv xtensa" def map_kernel_arch(a, d): import re @@ -26,6 +26,7 @@ def map_kernel_arch(a, d): elif re.match('aarch64$', a): return 'arm64' elif re.match('aarch64_be$', a): return 'arm64' elif re.match('mips(isa|)(32|64|)(r6|)(el|)$', a): return 'mips' + elif re.match('riscv(32|64|)(eb|)$', a): return 'riscv' elif re.match('p(pc|owerpc)(|64)', a): return 'powerpc' elif re.match('sh(3|4)$', a): return 'sh' elif re.match('bfin', a): return 'blackfin' From patchwork Fri Oct 6 00:50:44 2017 Content-Type: text/plain; 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Thu, 05 Oct 2017 17:51:01 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.51.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:51:00 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:44 -0700 Message-Id: <66bb5b1b170108f30415956f22607bb16d02350c.1507250774.git.raj.khem@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 05/10] runqemu: Add riscv support for qemu machines X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Signed-off-by: Khem Raj --- scripts/runqemu | 4 ++++ 1 file changed, 4 insertions(+) -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/scripts/runqemu b/scripts/runqemu index df76270904..9dc6a05c57 100755 --- a/scripts/runqemu +++ b/scripts/runqemu @@ -1077,6 +1077,10 @@ class BaseConfig(object): qbsys = 'mipsel' elif mach == 'qemumips64el': qbsys = 'mips64el' + elif mach == 'qemuriscv64': + qbsys = 'riscv64' + elif mach == 'qemuriscv32': + qbsys = 'riscv32' return 'qemu-system-%s' % qbsys From patchwork Fri Oct 6 00:50:45 2017 Content-Type: text/plain; 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Thu, 05 Oct 2017 17:51:02 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.51.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:51:02 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:45 -0700 Message-Id: <1231bf23c001d44632edf9061b87ac6629d2fc83.1507250774.git.raj.khem@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 06/10] binutils: Convert SRC_URI and SRCREV to weak defines X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org This makes it easy to override them in bbappends Signed-off-by: Khem Raj --- meta/recipes-devtools/binutils/binutils-2.29.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-devtools/binutils/binutils-2.29.inc b/meta/recipes-devtools/binutils/binutils-2.29.inc index 27d46eb088..35f76cba6d 100644 --- a/meta/recipes-devtools/binutils/binutils-2.29.inc +++ b/meta/recipes-devtools/binutils/binutils-2.29.inc @@ -18,9 +18,10 @@ BINUPV = "${@binutils_branch_version(d)}" UPSTREAM_CHECK_GITTAGREGEX = "binutils-(?P\d+_(\d_?)*)" -SRCREV = "37e991bb143ca2106330bcdc625590d53838b7a1" +SRCREV ?= "37e991bb143ca2106330bcdc625590d53838b7a1" +BINUTILS_GIT_URI ?= "git://sourceware.org/git/binutils-gdb.git;branch=binutils-${BINUPV}-branch;protocol=git" SRC_URI = "\ - git://sourceware.org/git/binutils-gdb.git;branch=binutils-${BINUPV}-branch;protocol=git \ + ${BINUTILS_GIT_URI} \ file://0003-configure-widen-the-regexp-for-SH-architectures.patch \ file://0004-Point-scripts-location-to-libdir.patch \ file://0005-Only-generate-an-RPATH-entry-if-LD_RUN_PATH-is-not-e.patch \ From patchwork Fri Oct 6 00:50:46 2017 Content-Type: text/plain; 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Thu, 05 Oct 2017 17:51:04 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.51.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:51:03 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:46 -0700 Message-Id: <9045558e883211b8abbe8b1d0f6e01070258d485.1507250774.git.raj.khem@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 07/10] gcc: Backport fix for a segfault on riscv X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org seen during kernel compile Signed-off-by: Khem Raj --- meta/recipes-devtools/gcc/gcc-7.2.inc | 1 + ...le-non-legitimate-address-in-riscv_legiti.patch | 50 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 meta/recipes-devtools/gcc/gcc-7.2/0050-RISC-V-Handle-non-legitimate-address-in-riscv_legiti.patch -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-devtools/gcc/gcc-7.2.inc b/meta/recipes-devtools/gcc/gcc-7.2.inc index 796e6b1eef..5883bc61a6 100644 --- a/meta/recipes-devtools/gcc/gcc-7.2.inc +++ b/meta/recipes-devtools/gcc/gcc-7.2.inc @@ -74,6 +74,7 @@ SRC_URI = "\ file://0047-sync-gcc-stddef.h-with-musl.patch \ file://0048-gcc-Enable-static-PIE.patch \ file://fix-segmentation-fault-precompiled-hdr.patch \ + file://0050-RISC-V-Handle-non-legitimate-address-in-riscv_legiti.patch \ ${BACKPORTS} \ " BACKPORTS = "\ diff --git a/meta/recipes-devtools/gcc/gcc-7.2/0050-RISC-V-Handle-non-legitimate-address-in-riscv_legiti.patch b/meta/recipes-devtools/gcc/gcc-7.2/0050-RISC-V-Handle-non-legitimate-address-in-riscv_legiti.patch new file mode 100644 index 0000000000..fe175abecd --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-7.2/0050-RISC-V-Handle-non-legitimate-address-in-riscv_legiti.patch @@ -0,0 +1,50 @@ +From 16210e6270e200cd4892a90ecef608906be3a130 Mon Sep 17 00:00:00 2001 +From: Kito Cheng +Date: Thu, 4 May 2017 02:11:13 +0800 +Subject: [PATCH] RISC-V: Handle non-legitimate address in + riscv_legitimize_move + +GCC may generate non-legitimate address due to we allow some +load/store with non-legitimate address in pic.md. + + 2017-05-12 Kito Cheng + + * config/riscv/riscv.c (riscv_legitimize_move): Handle + non-legitimate address. +--- +Upstream-Status: Backport + + gcc/ChangeLog | 5 +++++ + gcc/config/riscv/riscv.c | 16 ++++++++++++++++ + 2 files changed, 21 insertions(+) + +diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c +index f7fec4bfcf8..d519be1659a 100644 +--- a/gcc/config/riscv/riscv.c ++++ b/gcc/config/riscv/riscv.c +@@ -1385,6 +1385,22 @@ riscv_legitimize_move (enum machine_mode mode, rtx dest, rtx src) + return true; + } + ++ /* RISC-V GCC may generate non-legitimate address due to we provide some ++ pattern for optimize access PIC local symbol and it's make GCC generate ++ unrecognizable instruction during optmizing. */ ++ ++ if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0), ++ reload_completed)) ++ { ++ XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode); ++ } ++ ++ if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0), ++ reload_completed)) ++ { ++ XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode); ++ } ++ + return false; + } + +-- +2.14.2 + From patchwork Fri Oct 6 00:50:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khem Raj X-Patchwork-Id: 115013 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1193466qgn; Thu, 5 Oct 2017 17:52:00 -0700 (PDT) X-Received: by 10.99.150.25 with SMTP id c25mr410638pge.386.1507251119982; Thu, 05 Oct 2017 17:51:59 -0700 (PDT) ARC-Seal: i=1; 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Thu, 05 Oct 2017 17:51:06 -0700 (PDT) Received: from localhost.localdomain ([2601:646:8882:b8c::1f76]) by smtp.gmail.com with ESMTPSA id o128sm259308pga.5.2017.10.05.17.51.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 17:51:05 -0700 (PDT) From: Khem Raj To: openembedded-core@lists.openembedded.org Date: Thu, 5 Oct 2017 17:50:48 -0700 Message-Id: <05a4310d120918678aa3de7654ed21f2433f7e63.1507250774.git.raj.khem@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: References: Subject: [OE-core] [PATCH 09/10] elfutils: Fix missing library on linker cmdline X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Signed-off-by: Khem Raj --- meta/recipes-devtools/elfutils/elfutils_0.170.bb | 1 + ...0001-libasm-may-link-with-libbz2-if-found.patch | 39 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 meta/recipes-devtools/elfutils/files/0001-libasm-may-link-with-libbz2-if-found.patch -- 2.14.2 -- _______________________________________________ Openembedded-core mailing list Openembedded-core@lists.openembedded.org http://lists.openembedded.org/mailman/listinfo/openembedded-core diff --git a/meta/recipes-devtools/elfutils/elfutils_0.170.bb b/meta/recipes-devtools/elfutils/elfutils_0.170.bb index 8a339e48c9..3b81e287b0 100644 --- a/meta/recipes-devtools/elfutils/elfutils_0.170.bb +++ b/meta/recipes-devtools/elfutils/elfutils_0.170.bb @@ -17,6 +17,7 @@ SRC_URI += "\ file://0005-fix-a-stack-usage-warning.patch \ file://0006-Fix-build-on-aarch64-musl.patch \ file://0007-Fix-control-path-where-we-have-str-as-uninitialized-.patch \ + file://0001-libasm-may-link-with-libbz2-if-found.patch \ " SRC_URI_append_libc-musl = " file://0008-build-Provide-alternatives-for-glibc-assumptions-hel.patch" diff --git a/meta/recipes-devtools/elfutils/files/0001-libasm-may-link-with-libbz2-if-found.patch b/meta/recipes-devtools/elfutils/files/0001-libasm-may-link-with-libbz2-if-found.patch new file mode 100644 index 0000000000..fb0b060b4b --- /dev/null +++ b/meta/recipes-devtools/elfutils/files/0001-libasm-may-link-with-libbz2-if-found.patch @@ -0,0 +1,39 @@ +From 7672e363468271b4c63ff58770c5aac15ab8f722 Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Wed, 4 Oct 2017 22:30:46 -0700 +Subject: [PATCH] libasm may link with libbz2 if found + +This can fail to link binaries like objdump +where indirect libraries may be not found by linker + +| /mnt/a/oe/build/tmp/work/riscv64-bec-linux/elfutils/0.170-r0/recipe-sysroot/usr/lib/libbz2.so.1: error adding symbols: DSO missing from command line +| collect2: error: ld returned 1 exit status + +Signed-off-by: Khem Raj +--- +Upstream-Status: Pending + + src/Makefile.am | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/src/Makefile.am b/src/Makefile.am +index e03bc32..9b7e853 100644 +--- a/src/Makefile.am ++++ b/src/Makefile.am +@@ -39,11 +39,11 @@ EXTRA_DIST += make-debug-archive.in + CLEANFILES += make-debug-archive + + if BUILD_STATIC +-libasm = ../libasm/libasm.a ++libasm = ../libasm/libasm.a $(zip_LIBS) + libdw = ../libdw/libdw.a -lz $(zip_LIBS) $(libelf) $(libebl) -ldl + libelf = ../libelf/libelf.a -lz + else +-libasm = ../libasm/libasm.so ++libasm = ../libasm/libasm.so $(zip_LIBS) + libdw = ../libdw/libdw.so $(zip_LIBS) $(libelf) $(libebl) -ldl + libelf = ../libelf/libelf.so + endif +-- +2.14.2 + From patchwork Fri Oct 6 00:50:49 2017 Content-Type: text/plain; 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