From patchwork Fri Oct 6 14:04:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 115067 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1410953edb; Fri, 6 Oct 2017 07:07:59 -0700 (PDT) X-Google-Smtp-Source: AOwi7QB1A8lXH0XJoFSlSrrRJuYsXKs+zZO7JA079ceeThjPRJqVnzTP6eMecSSExEPvvtD3YdvJ X-Received: by 10.101.65.200 with SMTP id b8mr2116386pgq.274.1507298879301; Fri, 06 Oct 2017 07:07:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507298879; cv=none; d=google.com; s=arc-20160816; b=0DIIQ6+fHmqqzT2ljpFRIOBzwRaL9UAVYcLg5JVxD/V4+xGdybaTBxWGUkY0fPJYR2 9g/RVOpwVkHNTCBY0e/F8igL9QPKscRmN5inUv6aJravvuIWcH1lpqdD2mItIY8SYAtR pn9C3EYiTEdRxsJRdwLWjseMMBaX+rtdO8+jkhCMBfK2qyQfIHzsx3LD4Irh9bWuhlvC 8ml3S8Oie+BB3YF8szY/PAw92rn3VHRAfW+qa/tiRzJwARpRdpPkalQGcvylP2juW8gL pyFVc5Z8Nwmaeo50U57Vo0rNpk0NkhiFv/b4zo8x74mPp1sK+9qeLTr94nD9ACO1Q+43 P/Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=86D6vsfwVFtzSoJE97K4oxa7EM44HLvgCg8DlL4Jk2U=; b=g60obkP5Y1zSVfQjCyL69PVQJtnZogKDPeWsPVRfJejSHgfGLni5nASM3Sd4epLp5l dVNQeztviDpw3saDSEa86gc6y6oGOYmvkNn0lLK05s6UmcmXl2AGwhOl6dAoB/DPNFlr kABdxLo1EWo8HErFuRbvvtovN4f9v+5cojHzsTpf1tUBMkks10SZ5rkoTnYH5Rt2lHD+ SQS35IJUjycOtXVwf8Cu4SfxwTVMG/ZaoBnbg/Bd0BmHu3pLuRS/MOjTNrjVfxwazGDL qHI3mq4m2dfasw0Na0O3vr0AybenD4mW3vQLRP9rfOPwXbexQmHwRrvEeR7dvVaXs7Gf Kedg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x33si1300557plb.203.2017.10.06.07.07.58; Fri, 06 Oct 2017 07:07:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751800AbdJFOH6 (ORCPT + 7 others); Fri, 6 Oct 2017 10:07:58 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7498 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751527AbdJFOH5 (ORCPT ); Fri, 6 Oct 2017 10:07:57 -0400 Received: from 172.30.72.58 (EHLO DGGEMS403-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIO33385; Fri, 06 Oct 2017 22:07:53 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.301.0; Fri, 6 Oct 2017 22:07:22 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v9 1/4] ACPI/IORT: Add msi address regions reservation helper Date: Fri, 6 Oct 2017 15:04:47 +0100 Message-ID: <20171006140450.89652-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59D78E39.0286, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d94bd7e6723cbce8f2f339e28dabf0dd Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On some platforms msi parent address regions have to be excluded from normal IOVA allocation in that they are detected and decoded in a HW specific way by system components and so they cannot be considered normal IOVA address space. Add a helper function that retrieves ITS address regions - the msi parent - through IORT device <-> ITS mappings and reserves it so that these regions will not be translated by IOMMU and will be excluded from IOVA allocations. Signed-off-by: Shameer Kolothum [lorenzo.pieralisi@arm.com: updated commit log/added comments] Signed-off-by: Lorenzo Pieralisi --- drivers/acpi/arm64/iort.c | 97 ++++++++++++++++++++++++++++++++++++++-- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- 3 files changed, 102 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 9565d57..876c0e1 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -39,6 +39,7 @@ struct iort_its_msi_chip { struct list_head list; struct fwnode_handle *fw_node; + phys_addr_t base_addr; u32 translation_id; }; @@ -136,14 +137,16 @@ typedef acpi_status (*iort_find_node_callback) static DEFINE_SPINLOCK(iort_msi_chip_lock); /** - * iort_register_domain_token() - register domain token and related ITS ID - * to the list from where we can get it back later on. + * iort_register_domain_token() - register domain token along with related + * ITS ID and base address to the list from where we can get it back later on. * @trans_id: ITS ID. + * @base: ITS base address. * @fw_node: Domain token. * * Returns: 0 on success, -ENOMEM if no memory when allocating list element */ -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node) { struct iort_its_msi_chip *its_msi_chip; @@ -153,6 +156,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node) its_msi_chip->fw_node = fw_node; its_msi_chip->translation_id = trans_id; + its_msi_chip->base_addr = base; spin_lock(&iort_msi_chip_lock); list_add(&its_msi_chip->list, &iort_msi_chip_list); @@ -481,6 +485,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) return -ENODEV; } +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base) +{ + struct iort_its_msi_chip *its_msi_chip; + bool match = false; + + spin_lock(&iort_msi_chip_lock); + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) { + if (its_msi_chip->translation_id == its_id) { + *base = its_msi_chip->base_addr; + match = true; + break; + } + } + spin_unlock(&iort_msi_chip_lock); + + return match ? 0 : -ENODEV; +} + /** * iort_dev_find_its_id() - Find the ITS identifier for a device * @dev: The device. @@ -639,6 +661,73 @@ int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) return err; } + +/** + * iort_iommu_msi_get_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @head: Reserved region list from iommu_get_resv_regions() + * + * Returns: Number of reserved regions on success (0 if no associated msi + * regions), appropriate error value otherwise. The ITS interrupt + * translation space(ITS_base + 0x010000) associated with the device + * are the msi reserved regions. + */ +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct acpi_iort_its_group *its; + struct acpi_iort_node *node, *its_node = NULL; + int i, resv = 0; + + node = iort_find_dev_node(dev); + if (!node) + return -ENODEV; + + /* + * Current logic to reserve ITS regions relies on HW topologies + * where a given PCI or named component maps its IDs to only one + * ITS group; if a PCI or named component can map its IDs to + * different ITS groups through IORT mappings this function has + * to be reworked to ensure we reserve regions for all ITS groups + * a given PCI or named component may map IDs to. + */ + if (dev_is_pci(dev)) { + u32 rid; + + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); + its_node = iort_node_map_id(node, rid, NULL, IORT_MSI_TYPE); + } else { + for (i = 0; i < node->mapping_count; i++) { + its_node = iort_node_map_platform_id(node, NULL, + IORT_MSI_TYPE, i); + if (its_node) + break; + } + } + + if (!its_node) + return 0; + + /* Move to ITS specific data */ + its = (struct acpi_iort_its_group *)its_node->node_data; + + for (i = 0; i < its->its_count; i++) { + phys_addr_t base; + + if (!iort_find_its_base(its->identifiers[i], &base)) { + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + struct iommu_resv_region *region; + + region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K, + prot, IOMMU_RESV_MSI); + if (region) { + list_add_tail(®ion->list, head); + resv++; + } + } + } + + return (resv == its->its_count) ? resv : -ENODEV; +} #else static inline const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) @@ -646,6 +735,8 @@ const struct iommu_ops *iort_fwspec_iommu_ops(struct iommu_fwspec *fwspec) static inline int iort_add_device_replay(const struct iommu_ops *ops, struct device *dev) { return 0; } +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e8d8934..19d1ff6 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3197,7 +3197,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, return -ENOMEM; } - err = iort_register_domain_token(its_entry->translation_id, dom_handle); + err = iort_register_domain_token(its_entry->translation_id, res.start, + dom_handle); if (err) { pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", &res.start, its_entry->translation_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 8d3f0bf..182a577 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,7 +26,8 @@ #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL) #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node); +int iort_register_domain_token(int trans_id, phys_addr_t base, + struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); #ifdef CONFIG_ACPI_IORT @@ -38,6 +39,7 @@ /* IOMMU interface */ void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size); const struct iommu_ops *iort_iommu_configure(struct device *dev); +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head); #else static inline void acpi_iort_init(void) { } static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id) @@ -52,6 +54,9 @@ static inline void iort_dma_setup(struct device *dev, u64 *dma_addr, static inline const struct iommu_ops *iort_iommu_configure(struct device *dev) { return NULL; } +static inline +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head) +{ return -ENODEV; } #endif #endif /* __ACPI_IORT_H__ */ From patchwork Fri Oct 6 14:04:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 115068 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1411029edb; Fri, 6 Oct 2017 07:08:02 -0700 (PDT) X-Google-Smtp-Source: AOwi7QC9dWfeiKDtRxvUpzpoSlV9Rm84uTdP3j9kPKrh30TcfaO0yvgm+L1KfemXnRoPwaFUBzFC X-Received: by 10.98.48.65 with SMTP id w62mr2349450pfw.91.1507298882767; Fri, 06 Oct 2017 07:08:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507298882; cv=none; d=google.com; s=arc-20160816; b=rr7AT01WMcqBVIE4fK+rig0ysmF0KfQoqhzl5bNVEnKPkpbCrCtheZFsmiOa6B2xmB +eLAIKtAGQd6wtkBFgjPoF6aN9rwMrudljNdWBT66Ddqo35DwydG+zFN7QRvIANWtOOs wl33mb1iUNAS3NTdhW+10xG15nClOktaxRDRjy4KBzJGeFHvZE+Or5giTWrpPucG6Abe SLpzzHAqHqyilSjH5H3LDVguvallSFsv3lGBRCj7RSGDyMpt04lZK9BKG68HaqUn8IsD MClT6cgjp4p3+ypWX1uVIrhhtCmjj6xtNy5AbN0g2RLUpZgBvoZWnv8WYC2+hwNxvEjx ZfEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=90NCsH1553NAEej2SLF3aW35aSV1oVht+b3gzu3janE=; b=trnOfzdLgF+V6ndI2wT3RvHXa4+vEIrYm7WkSbaPPuzg44kqCHfCiOM7SVsgJnaD3L sABXSmmnEt4bDL35lB5QG39fyem35BUyKZmqDUks5lUqvh3t1sRtb0zX/jNIvoq0Nfra 2lVth3OQEcQgIiDKXbyefo61/oQpG+knIgAeBuLdO2sppS8r8uWSh5rN40bzKfJgPCDD g+LWMD6PGY4qcp4Qt549KAhqQRaYOtNjYvrGwoPQ83JwhHfa6tJHlkwa4WhndyBbQAWV uo+CfeTW+9yZVQm7h+IkyoC5QLaICDvTYPJwvAKyYWy0yHjdcQr18zlbJf3S5DABZPdj 33sA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r145si1303201pfr.567.2017.10.06.07.08.02; Fri, 06 Oct 2017 07:08:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751866AbdJFOIA (ORCPT + 7 others); Fri, 6 Oct 2017 10:08:00 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7500 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751755AbdJFOH7 (ORCPT ); Fri, 6 Oct 2017 10:07:59 -0400 Received: from 172.30.72.58 (EHLO DGGEMS403-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIO33388; Fri, 06 Oct 2017 22:07:53 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.301.0; Fri, 6 Oct 2017 22:07:26 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Fri, 6 Oct 2017 15:04:48 +0100 Message-ID: <20171006140450.89652-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59D78E39.0312, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ccee44145571a8a2311c8cc4b0d93011 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org IOMMU drivers can use this to implement their .get_resv_regions callback for HW MSI specific reservations(e.g. ARM GICv3 ITS MSI region). Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 20 ++++++++++++++++++++ include/linux/dma-iommu.h | 7 +++++++ 2 files changed, 27 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9d1cebe..bae677e 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -19,6 +19,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -27,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -198,6 +200,24 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(iommu_dma_get_resv_regions); +/** + * iommu_dma_get_msi_resv_regions - Reserved region driver helper + * @dev: Device from iommu_get_resv_regions() + * @list: Reserved region list from iommu_get_resv_regions() + * + * IOMMU drivers can use this to implement their .get_resv_regions + * callback for HW MSI specific reservations. For now, this only + * covers ITS MSI region reservation using ACPI IORT helper function. + */ +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode)) + return iort_iommu_msi_get_resv_regions(dev, list); + + return -ENODEV; +} +EXPORT_SYMBOL(iommu_dma_get_msi_resv_regions); + static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, phys_addr_t start, phys_addr_t end) { diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h index 92f2083..6062ef0 100644 --- a/include/linux/dma-iommu.h +++ b/include/linux/dma-iommu.h @@ -74,6 +74,8 @@ void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg); void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list); + #else struct iommu_domain; @@ -107,6 +109,11 @@ static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_he { } +static inline int iommu_dma_get_msi_resv_regions(struct device *dev, struct list_head *list) +{ + return -ENODEV; +} + #endif /* CONFIG_IOMMU_DMA */ #endif /* __KERNEL__ */ #endif /* __DMA_IOMMU_H */ From patchwork Fri Oct 6 14:04:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 115070 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1411144edb; Fri, 6 Oct 2017 07:08:08 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDlPzjMwxpvHYgDyg+u/n0XScahImQcHLN5/07U2Ud9obfkQy8nGIvuCfyJMvBNA5yTt8L+ X-Received: by 10.98.56.18 with SMTP id f18mr2294866pfa.81.1507298888488; Fri, 06 Oct 2017 07:08:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507298888; cv=none; d=google.com; s=arc-20160816; b=YhiYEOwlKTe2YriRsG2CYpZFrePi/sSpk2qMKdlQDdnLBDo05Dg5AX2SYds1Nq1G5N xFt+Et7jsxsP9gDmAEi5e5ipP7OS8q3EG4FfgA2vgxXgiMzqnVVJMItts0bU4pGQ5a+I wktwyePvY1CT4iwXl+A2NMuvKKilOHOhAT2BF+Mvf8nggDUMIdhtizfJ01J/aNowtTVs 2FGGRHUs1r9MwFmEHcKfG66UvOhdYwSIxu+kIuZ1WzWHomQoPdnzPpow6+cQ4Mj3bSH/ UEIHRC01gyqQInu3rV/k5Cy7P1ptk70NmII1hxRYifLDxKyHOIHK26WUNgBA9y42lDIw S/qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=L2YA/6fLjE9aOcIvNhmR3UKQbSzCT7Pu+RC6x7cQ2fY=; b=Y5WsonmqOYRR284N+wVWBaxklcAiLvDdFn8nZ/NbrhAFihwLK4v/4ja18vLgdrkeCV a5I5Ae5Vt540VPwG/pcaBozYfHyoBtnwuk98JVTSyVFiWDOfRYDP7HERTTXuxnl4L7iA yLViVpPQwM9wv0R68sufTltvq/VJ7Frt2nm9D3guuhLLSsXTIcFj/HRwMWQQNHUY3C6t iiK9v5Lihau5uP4PV3pVKZpvLojg/EvS8MSYQZcsAVok//vyYC+i0KkwI2JCYgXUK8mV Seef/DW5AQpKtb+Q0JjHPHu6zpQuenryniMxdfkjH0PZ+15DnwSelgKwiax2Li+DbLGw wVow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j8si1229982plk.805.2017.10.06.07.08.07; Fri, 06 Oct 2017 07:08:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751654AbdJFOIG (ORCPT + 7 others); Fri, 6 Oct 2017 10:08:06 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7499 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751757AbdJFOIA (ORCPT ); Fri, 6 Oct 2017 10:08:00 -0400 Received: from 172.30.72.58 (EHLO DGGEMS403-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIO33389; Fri, 06 Oct 2017 22:07:53 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.301.0; Fri, 6 Oct 2017 22:07:31 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v9 3/4] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Fri, 6 Oct 2017 15:04:49 +0100 Message-ID: <20171006140450.89652-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59D78E3A.0087, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e0bac6cc5fe5acfa64a483feaa321cba Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm-smmu-v3.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e67ba6c..dd42ae9 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -608,6 +608,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -1934,14 +1935,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2683,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; } From patchwork Fri Oct 6 14:04:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 115071 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1841248qgn; Fri, 6 Oct 2017 07:10:32 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDtG0AcEtv2RC1jgbqjIF3haDHg8CK/c6PENJTHFkJpKb+vuzv7oE46NNqGcAigLKXLQzBh X-Received: by 10.99.43.6 with SMTP id r6mr2100381pgr.353.1507299032383; Fri, 06 Oct 2017 07:10:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507299032; cv=none; d=google.com; s=arc-20160816; b=nfaV0Of/sPJoAjUUjlhkrmkzg2CNsXF3gShUw5JuB5gTeW4jIDVbRv5yYcmwGpOh7t UmBfqy5/aAIzidyatM9I6zHDOpvbi0UG4ZqNTEeBcZthmyWIlB1thlAW4PUgKOvt0eF4 wU2C5I846u7lQDn7UxwR+BhDjC4xEzbpk5/EaFoCry5oYbdoUeEMwtvEhZY2kXvs6RJ1 aEvB/4aGH/QrPPXsFFBWItfM5JFWI6uyPV0eEvbRIfxy39v60WFnLvRVac+3Iv99F4Y7 X1z7mjlu/IKonZMWN2a3Mlprfgmi4IprYai2kkIltraSgVU984crusdJy/Qq0JwGsUQT LZ8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=1O/1BMSlUSmJiWDWoniY23CeoGdoodmDRxOYh5QBrYQ=; b=QIl434dyKctPozX7hcyPtNmDLxOgT5FguuUYOmzDBRE0RS0pc+XQyBlktGRhyTZtVa yaziRVTrGaVKa8E6YATm+2+CZavFDngNUmVMXA0Zj+tbDnvqCVGOXW2K0xOYU6PyZcOe wNQuVyphW80luui+9gB8zqTtrYy8pCTDlO8BW0cL0Ah2KqvtdNAH0KFO7iW8jG+1CKBw O9QvHa9tfF78cX9nFZTqbI50ooerVlGZFAtK0jJ9JxXg5RFGYsJB3rgx2of3CE7BlA9N eTXTQLZQzRRqzsB1ldHKMLAB34w8x/lQJxHJHAUDsQZSaD4ML9DozT4ZH8Rn5KwKRteY b1rg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y131si1329734pfg.299.2017.10.06.07.10.32; Fri, 06 Oct 2017 07:10:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751866AbdJFOKb (ORCPT + 7 others); Fri, 6 Oct 2017 10:10:31 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7502 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751846AbdJFOKa (ORCPT ); Fri, 6 Oct 2017 10:10:30 -0400 Received: from 172.30.72.58 (EHLO DGGEMS403-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIO33673; Fri, 06 Oct 2017 22:10:27 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.301.0; Fri, 6 Oct 2017 22:07:36 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v9 4/4] PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3 Date: Fri, 6 Oct 2017 15:04:50 +0100 Message-ID: <20171006140450.89652-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59D78ED4.0071, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d42ebc258cbaf14df7ac8952d549471a Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. In order to workaround this, ARM SMMUv3 driver requires a quirk to treat the MSI regions separately. Such a quirk is currently missing for DT based systems and therefore we need to blacklist the hip06/hip07 PCIe controllers. Signed-off-by: Shameer Kolothum --- drivers/pci/dwc/pcie-hisi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Gabriele Paoloni Acked-by: Zhou Wang Acked-by: Bjorn Helgaas diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c index a201791..6800747 100644 --- a/drivers/pci/dwc/pcie-hisi.c +++ b/drivers/pci/dwc/pcie-hisi.c @@ -270,6 +270,12 @@ static int hisi_pcie_probe(struct platform_device *pdev) struct resource *reg; int ret; + if ((IS_BUILTIN(CONFIG_ARM_SMMU_V3)) && + of_property_read_bool(dev->of_node, "iommu-map")) { + dev_warn(dev, "HiSilicon erratum 161010801: blacklisting PCIe controllers behind SMMUv3\n"); + return -ENODEV; + } + hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL); if (!hisi_pcie) return -ENOMEM; @@ -340,6 +346,12 @@ static int hisi_pcie_almost_ecam_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct pci_ecam_ops *ops; + if ((IS_BUILTIN(CONFIG_ARM_SMMU_V3)) && + of_property_read_bool(dev->of_node, "iommu-map")) { + dev_warn(dev, "HiSilicon erratum 161010801: blacklisting PCIe controllers behind SMMUv3\n"); + return -ENODEV; + } + ops = (struct pci_ecam_ops *)of_device_get_match_data(dev); return pci_host_common_probe(pdev, ops); }