From patchwork Sat May 9 14:25:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245342 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:09 +0530 Subject: [PATCH v1 1/7] clk: actions: Add Ethernet clocks In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-2-git-send-email-amittomer25@gmail.com> This commit adds clocks needed for ethernet operations for Actions OWL family of SoCs (S700 and S900). Signed-off-by: Amit Singh Tomar --- arch/arm/include/asm/arch-owl/regs_s700.h | 2 ++ arch/arm/include/asm/arch-owl/regs_s900.h | 4 ++++ drivers/clk/owl/clk_owl.c | 9 +++++++++ drivers/clk/owl/clk_owl.h | 2 -- 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h index 2f21c15cca8c..90459ae95eeb 100644 --- a/arch/arm/include/asm/arch-owl/regs_s700.h +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -53,4 +53,6 @@ #define CMU_CVBSPLL 0x00B8 #define CMU_SSTSCLK 0x00C0 +#define CMU_DEVCLKEN1_ETH BIT(23) + #endif diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h index 9e9106ddaab9..084bc9b8c3fb 100644 --- a/arch/arm/include/asm/arch-owl/regs_s900.h +++ b/arch/arm/include/asm/arch-owl/regs_s900.h @@ -61,4 +61,8 @@ #define CMU_TVOUTPLLDEBUG0 (0x00EC) #define CMU_TVOUTPLLDEBUG1 (0x00FC) +#define CMU_DEVCLKEN1_ETH BIT(22) +#define CLK_ETHERNET CLK_ETH_MAC +#define CMU_ETHERNETPLL CMU_ASSISTPLL + #endif diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c index 5607b2b7b516..b80862e17f51 100644 --- a/drivers/clk/owl/clk_owl.c +++ b/drivers/clk/owl/clk_owl.c @@ -85,6 +85,11 @@ int owl_clk_enable(struct clk *clk) /* Enable UART3 interface clock */ setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); break; + case CLK_RMII_REF: + case CLK_ETHERNET: + setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); + setbits_le32(priv->base + CMU_ETHERNETPLL, 5); + break; default: return -EINVAL; } @@ -110,6 +115,10 @@ int owl_clk_disable(struct clk *clk) /* Disable UART3 interface clock */ clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); break; + case CLK_RMII_REF: + case CLK_ETHERNET: + clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); + break; default: return -EINVAL; } diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h index b8d33624c5f5..a2065a726d46 100644 --- a/drivers/clk/owl/clk_owl.h +++ b/drivers/clk/owl/clk_owl.h @@ -59,6 +59,4 @@ struct owl_clk_priv { #define CMU_DEVCLKEN1_UART5 BIT(21) #define CMU_DEVCLKEN1_UART3 BIT(11) -#define CMU_DEVCLKEN1_ETH_S700 BIT(23) - #endif From patchwork Sat May 9 14:25:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245343 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:10 +0530 Subject: [PATCH v1 2/7] net: phy: realtek: Add support for RTL8201F PHY module. In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-3-git-send-email-amittomer25@gmail.com> This patch adds support for Realtek PHY RTL8201F 10/100Mbs (with variants: RTL8201FN and RTL8201FL) PHYceiver. It is present on Actions Semi Cubieboard7 board. Signed-off-by: Amit Singh Tomar --- drivers/net/phy/realtek.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 8f1d75963259..b9c373bfe3cc 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -157,6 +157,14 @@ static int rtl8211x_config(struct phy_device *phydev) return 0; } +/* RealTek RTL8201F */ +static int rtl8201f_config(struct phy_device *phydev) +{ + genphy_config_aneg(phydev); + + return 0; +} + static int rtl8211f_config(struct phy_device *phydev) { u16 reg; @@ -386,12 +394,24 @@ static struct phy_driver RTL8211F_driver = { .writeext = &rtl8211f_phy_extwrite, }; +/* Support for RTL8201F PHY */ +static struct phy_driver RTL8201F_driver = { + .name = "RealTek RTL8201F 10/100Mbps Ethernet", + .uid = 0x1cc816, + .mask = 0xffffff, + .features = PHY_BASIC_FEATURES, + .config = &rtl8201f_config, + .startup = &rtl8211e_startup, + .shutdown = &genphy_shutdown, +}; + int phy_realtek_init(void) { phy_register(&RTL8211B_driver); phy_register(&RTL8211E_driver); phy_register(&RTL8211F_driver); phy_register(&RTL8211DN_driver); + phy_register(&RTL8201F_driver); return 0; } From patchwork Sat May 9 14:25:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245344 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:11 +0530 Subject: [PATCH v1 3/7] net: phy: realtek: Introduce PHY_RTL8201F_S700_RMII_TIMINGS to adjust rx/tx timings In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-4-git-send-email-amittomer25@gmail.com> RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have specific Rx/Tx interface timings requirement for proper PHY operations. These timing values are not documented anywhere and picked from vendor code. This commits lets proper packets to be transmitted over the network. Signed-off-by: Amit Singh Tomar --- drivers/net/phy/Kconfig | 9 +++++++++ drivers/net/phy/realtek.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index d1f049e62ab7..123c17c04458 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -235,6 +235,15 @@ config RTL8211F_PHY_FORCE_EEE_RXC_ON Default n, which means that the PHY state is not changed. To work around the issues, change this setting to y. +config RTL8201F_PHY_S700_RMII_TIMINGS + bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings" + depends on PHY_REALTEK + help + This provides an option to configure specific timing requirements (needed + for proper PHY operations) for the PHY module present on ACTION SEMI S700 + based cubieboard7. Exact timing requiremnets seems to be SoC specific + (and it's undocumented) that comes from vendor code itself. + config PHY_SMSC bool "Microchip(SMSC) Ethernet PHYs support" diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index b9c373bfe3cc..a549a106876f 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -13,6 +13,7 @@ #define PHY_RTL8211x_FORCE_MASTER BIT(1) #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2) #define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3) +#define PHY_RTL8201F_S700_RMII_TIMINGS BIT(4) #define PHY_AUTONEGOTIATE_TIMEOUT 5000 @@ -58,6 +59,15 @@ #define MIIM_RTL8211F_TX_DELAY 0x100 #define MIIM_RTL8211F_LCR 0x10 +#define RTL8201F_RMSR 0x10 + +#define RMSR_RX_TIMING_SHIFT BIT(2) +#define RMSR_RX_TIMING_MASK GENMASK(7, 4) +#define RMSR_RX_TIMING_VAL 0x4 +#define RMSR_TX_TIMING_SHIFT BIT(3) +#define RMSR_TX_TIMING_MASK GENMASK(11, 8) +#define RMSR_TX_TIMING_VAL 0x5 + static int rtl8211f_phy_extread(struct phy_device *phydev, int addr, int devaddr, int regnum) { @@ -112,6 +122,15 @@ static int rtl8211f_probe(struct phy_device *phydev) return 0; } +static int rtl8210f_probe(struct phy_device *phydev) +{ +#ifdef CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS + phydev->flags |= PHY_RTL8201F_S700_RMII_TIMINGS; +#endif + + return 0; +} + /* RealTek RTL8211x */ static int rtl8211x_config(struct phy_device *phydev) { @@ -160,6 +179,21 @@ static int rtl8211x_config(struct phy_device *phydev) /* RealTek RTL8201F */ static int rtl8201f_config(struct phy_device *phydev) { + unsigned int reg; + + if (phydev->flags & PHY_RTL8201F_S700_RMII_TIMINGS) { + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, + 7); + reg = phy_read(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR); + reg &= ~(RMSR_RX_TIMING_MASK | RMSR_TX_TIMING_MASK); + /* Set the needed Rx/Tx Timings for proper PHY operation */ + reg |= (RMSR_RX_TIMING_VAL << RMSR_RX_TIMING_SHIFT) + | (RMSR_TX_TIMING_VAL << RMSR_TX_TIMING_SHIFT); + phy_write(phydev, MDIO_DEVAD_NONE, RTL8201F_RMSR, reg); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, + 0); + } + genphy_config_aneg(phydev); return 0; @@ -400,6 +434,7 @@ static struct phy_driver RTL8201F_driver = { .uid = 0x1cc816, .mask = 0xffffff, .features = PHY_BASIC_FEATURES, + .probe = &rtl8210f_probe, .config = &rtl8201f_config, .startup = &rtl8211e_startup, .shutdown = &genphy_shutdown, From patchwork Sat May 9 14:25:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245345 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:12 +0530 Subject: [PATCH v1 4/7] net: designware: s700: Add glue code for S700 mac In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-5-git-send-email-amittomer25@gmail.com> This patchs adds glue logic to enable designware mac present on Action Semi based S700 SoC, Configures SoC specific bits. Undocumented bit that programs the PHY interface select register comes from vendor source. It has been tested on Cubieboard7-lite based on S700 SoC. Signed-off-by: Amit Singh Tomar --- arch/arm/include/asm/arch-owl/regs_s700.h | 6 +++ drivers/net/Kconfig | 7 ++++ drivers/net/Makefile | 1 + drivers/net/dwmac_s700.c | 66 +++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+) create mode 100644 drivers/net/dwmac_s700.c diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h index 90459ae95eeb..0f79faec69c1 100644 --- a/arch/arm/include/asm/arch-owl/regs_s700.h +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -55,4 +55,10 @@ #define CMU_DEVCLKEN1_ETH BIT(23) +#define GPIO_MFP_PWM (0xE01B0000) +#define MFP_CTL0 (GPIO_MFP_PWM + 0x40) +#define MFP_CTL1 (GPIO_MFP_PWM + 0x44) +#define MFP_CTL2 (GPIO_MFP_PWM + 0x48) +#define MFP_CTL3 (GPIO_MFP_PWM + 0x4C) + #endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a2587a29e165..1a04e333efdf 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -225,6 +225,13 @@ config ETH_DESIGNWARE_SOCFPGA Altera system manager to correctly interface with the PHY. This code handles those SoC specifics. +config ETH_DESIGNWARE_S700 + bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC" + depends on DM_ETH && ETH_DESIGNWARE + help + This provides glue layer to use Synopsys Designware Ethernet MAC + present on Actions S700 SoC. + config ETHOC bool "OpenCores 10/100 Mbps Ethernet MAC" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6d9b8772b1a5..6f01d0169240 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o +obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c new file mode 100644 index 000000000000..a5d544e91e06 --- /dev/null +++ b/drivers/net/dwmac_s700.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Amit Singh Tomar + * + * Actions DWMAC specific glue layer + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "designware.h" +#include + +/* pin control for MAC */ +#define RMII_TXD01_MFP_CTL0 (0x0 << 16) +#define RMII_RXD01_MFP_CTL0 (0x0 << 8) +#define RMII_TXEN_TXER_MFP_CTL0 (0x0 << 13) +#define RMII_REF_CLK_MFP_CTL0 (0x0 << 6) +#define CLKO_25M_EN_MFP_CTL3 BIT(30) + +DECLARE_GLOBAL_DATA_PTR; + +static void dwmac_board_setup(void) +{ + clrbits_le32(MFP_CTL0, (RMII_TXD01_MFP_CTL0 | RMII_RXD01_MFP_CTL0 | + RMII_TXEN_TXER_MFP_CTL0 | RMII_REF_CLK_MFP_CTL0)); + + setbits_le32(MFP_CTL3, CLKO_25M_EN_MFP_CTL3); +} + +static int dwmac_s700_probe(struct udevice *dev) +{ + dwmac_board_setup(); + + /* This is undocumented, phy interface select register */ + writel(0x4, 0xe024c0a0); + + return designware_eth_probe(dev); +} + +static int dwmac_s700_ofdata_to_platdata(struct udevice *dev) +{ + return designware_eth_ofdata_to_platdata(dev); +} + +static const struct udevice_id dwmac_s700_ids[] = { + {.compatible = "actions,s700-ethernet"}, + { } +}; + +U_BOOT_DRIVER(dwmac_s700) = { + .name = "dwmac_s700", + .id = UCLASS_ETH, + .of_match = dwmac_s700_ids, + .ofdata_to_platdata = dwmac_s700_ofdata_to_platdata, + .probe = dwmac_s700_probe, + .ops = &designware_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; From patchwork Sat May 9 14:25:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245346 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:13 +0530 Subject: [PATCH v1 5/7] arm: dts: s700: add node for ethernet controller In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-6-git-send-email-amittomer25@gmail.com> This patch adds node for ethernet controller found on Action Semi OWL S700 SoC. Since, there is no upstream Linux binding exist for S700 ethernet controller, Changes are put in u-boot specific dtsi file. Signed-off-by: Amit Singh Tomar --- arch/arm/dts/s700-u-boot.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/dts/s700-u-boot.dtsi b/arch/arm/dts/s700-u-boot.dtsi index a527cccc75f2..1b2768272c62 100644 --- a/arch/arm/dts/s700-u-boot.dtsi +++ b/arch/arm/dts/s700-u-boot.dtsi @@ -6,6 +6,19 @@ /{ soc { u-boot,dm-pre-reloc; + + gmac: ethernet at e0220000 { + compatible = "actions,s700-ethernet"; + reg = <0 0xe0220000 0 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + local-mac-address = [ 00 18 fe 66 66 66 ]; + clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>; + clock-names = "ethernet", "rmii_ref"; + phy-mode = "rmii"; + status = "okay"; + }; + }; }; From patchwork Sat May 9 14:25:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245347 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:14 +0530 Subject: [PATCH v1 6/7] owl: Kconfig: Enable DM eth for OWL platform In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-7-git-send-email-amittomer25@gmail.com> This patch selects CONFIG_DM_ETH (ethernet driver is base on DM model) for Action semi owl SoC. Signed-off-by: Amit Singh Tomar --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d463088a2e4..80e07f92febc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -904,6 +904,7 @@ config ARCH_MX5 config ARCH_OWL bool "Actions Semi OWL SoCs" select DM + select DM_ETH select DM_SERIAL select OWL_SERIAL select CLK From patchwork Sat May 9 14:25:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Tomer X-Patchwork-Id: 245348 List-Id: U-Boot discussion From: amittomer25 at gmail.com (Amit Singh Tomar) Date: Sat, 9 May 2020 19:55:15 +0530 Subject: [PATCH v1 7/7] configs: Enable mac and phy configs In-Reply-To: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> References: <1589034315-19722-1-git-send-email-amittomer25@gmail.com> Message-ID: <1589034315-19722-8-git-send-email-amittomer25@gmail.com> This patch adds MAC and PHY related configs (needed for proper ethernet operations) for Action Semi S700 SoC. Signed-off-by: Amit Singh Tomar --- configs/cubieboard7_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig index 637dc9e9fb79..c82afc340313 100644 --- a/configs/cubieboard7_defconfig +++ b/configs/cubieboard7_defconfig @@ -10,3 +10,7 @@ CONFIG_BOOTARGS="console=ttyOWL3,115200n8" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot => " CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7" +CONFIG_ETH_DESIGNWARE_S700=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY_REALTEK=y +CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS=y