From patchwork Mon Oct 9 12:03:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 115203 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2473080qgn; Mon, 9 Oct 2017 05:03:26 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBtpyRasPEYUrEd1n0QRsEfQMjliMo7bHvMgmSNCOUCPemm+IRY1a9kPQY43BTpY1cyvdAf X-Received: by 10.99.97.139 with SMTP id v133mr1251502pgb.300.1507550605930; Mon, 09 Oct 2017 05:03:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507550605; cv=none; d=google.com; s=arc-20160816; b=lrQxXxKvD3T8lXjLtWNpBKYmJZRzR2zYUPgngz9UNY2Ppv2UK8t0V7c0GaY2f6ViEi EH8jvbwlWhUgfENlONgpQ107RoRsSVAtd2J8ALBVrIg3QM6Wz2djtzVzYhBBK6YSXU9U RIV4sYLYTJVltxyxpxanPzAM+LxbhHJEaEXAmywU5uXHADPXEP7TDNvhCq+HHhWqwIjj w5aA3OSGVnLmNnwFYEn+C13OD6KmmzOxkuVWfw8b7ZWaHHxGLXeFlQyZmkWGU+U0L+XW a4i9X0SZfEDMLYYaZUAoGz5KwGC+FUgT6erG37yYnY1uquE9oAfzjXdNPAuM/38ugxWb SF8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature:arc-authentication-results; bh=wzlnINk353ASVBoNNrZO4kl45UvJ+8YmR68O1ay1iGk=; b=N1n+BfXkOXs9UnUC6BrGBUZub9SAMLNRmvgSQBV98GJDZKPjYcyMokQgYocYNgvi4R lr6/U/M+xhearqg6vv/FHHdaWDU4tP78dquo+qqmQuBqHTvjlTaE5iGKZBNy0aXynnQb zakXyAelUrhkGAmiulQA+iU/bnGk1HVcqT0R1q+EhdkWirkt3bwaKunhTBMUddIkljrf OySRAlQYWYx6gqVuSUScPh8bXrczWVnMKYHMgotBap9B7Rpui3aUWPL3fP7K3HrnSQI0 AR5F72SJprAnDhGKELiXh/Uw+fovMle7NkD5wd/y0HKg+YENMYXk0KlEB+gDVxr9gf6I Y7+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PUS6jXsw; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 69si6872611pfh.27.2017.10.09.05.03.25; Mon, 09 Oct 2017 05:03:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PUS6jXsw; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754018AbdJIMDS (ORCPT + 8 others); Mon, 9 Oct 2017 08:03:18 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45147 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751581AbdJIMDP (ORCPT ); Mon, 9 Oct 2017 08:03:15 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v99C36Mi005539; Mon, 9 Oct 2017 07:03:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507550586; bh=VsBNitO+An+6R6+P61n54ryZcTBWiROnCxd+mglP2yc=; h=From:To:CC:Subject:Date; b=PUS6jXsw0GuB2Ii535R1vISb5KNUrkurlvIqrGPqTusJnOQZVeGyxSarr3kojgmYj XDh6sf/e/illwTsNqZwamit2LRGMdqOdUhL7tDleuGsIu37/dWIRV1FEWWyfGbZBhZ fLNFVFhq3PRPm1rdn3dxWBLmzWoGBBkMva6JjKnM= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v99C36XW016494; Mon, 9 Oct 2017 07:03:06 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 9 Oct 2017 07:03:06 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 9 Oct 2017 07:03:06 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v99C369X025133; Mon, 9 Oct 2017 07:03:06 -0500 Received: from localhost ([172.22.136.90]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v99C36311496; Mon, 9 Oct 2017 07:03:06 -0500 (CDT) From: Dan Murphy To: , CC: , , , Dan Murphy Subject: [PATCH v3 1/3] net: phy: Remove TI DP83822 from DP83848 driver Date: Mon, 9 Oct 2017 07:03:00 -0500 Message-ID: <20171009120302.23611-1-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Removing the DP83822 device from the DP83848 to support the TI DP83822 dedicated driver that will initially support WoL settings. Signed-off-by: Dan Murphy --- v3 - No changes made v2 - There was no v1 on this patch this is new. drivers/net/phy/dp83848.c | 3 --- 1 file changed, 3 deletions(-) -- 2.14.0 diff --git a/drivers/net/phy/dp83848.c b/drivers/net/phy/dp83848.c index 3de4fe4dda77..3966d43c5146 100644 --- a/drivers/net/phy/dp83848.c +++ b/drivers/net/phy/dp83848.c @@ -20,7 +20,6 @@ #define TI_DP83620_PHY_ID 0x20005ce0 #define NS_DP83848C_PHY_ID 0x20005c90 #define TLK10X_PHY_ID 0x2000a210 -#define TI_DP83822_PHY_ID 0x2000a240 /* Registers */ #define DP83848_MICR 0x11 /* MII Interrupt Control Register */ @@ -80,7 +79,6 @@ static struct mdio_device_id __maybe_unused dp83848_tbl[] = { { NS_DP83848C_PHY_ID, 0xfffffff0 }, { TI_DP83620_PHY_ID, 0xfffffff0 }, { TLK10X_PHY_ID, 0xfffffff0 }, - { TI_DP83822_PHY_ID, 0xfffffff0 }, { } }; MODULE_DEVICE_TABLE(mdio, dp83848_tbl); @@ -110,7 +108,6 @@ static struct phy_driver dp83848_driver[] = { DP83848_PHY_DRIVER(NS_DP83848C_PHY_ID, "NS DP83848C 10/100 Mbps PHY"), DP83848_PHY_DRIVER(TI_DP83620_PHY_ID, "TI DP83620 10/100 Mbps PHY"), DP83848_PHY_DRIVER(TLK10X_PHY_ID, "TI TLK10X 10/100 Mbps PHY"), - DP83848_PHY_DRIVER(TI_DP83822_PHY_ID, "TI DP83822 10/100 Mbps PHY"), }; module_phy_driver(dp83848_driver); From patchwork Mon Oct 9 12:03:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 115204 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2473127qgn; Mon, 9 Oct 2017 05:03:28 -0700 (PDT) X-Google-Smtp-Source: AOwi7QD0nsdIkgsgVEZhW4cfFMMDWixRNzYUk/xtDo4s61NYc6jMvt7nLAGGvaODuVtyM2kW3By0 X-Received: by 10.99.97.149 with SMTP id v143mr9257850pgb.413.1507550608307; Mon, 09 Oct 2017 05:03:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507550608; cv=none; d=google.com; s=arc-20160816; b=DLRPAdrN9DyIb1EOsTyyWqLDhOouAHz4PEk2Cq5esPwBfrwgROpwtDuzvi+7sz4uv9 63oRXt7CfYli2UcUpYdC9AuYgIAswG4xMXXtkad61aKy+n+Z0On3O/i3VWnbcVG8Jx3I Vc7Qp9PkjUls5R3d6OsamYR+FGaTLmYWtP5BDTecY8aIKO9mCLi1H8NJXfEE3+F3601F NgQCRwAwqbmVc1IvZJn6lmvb8TbKy2SWDP50OsXbFQ9CwfkGISjHZtO21fdHQu5+3iHD IRII0AVp8OZZZECXXuiFDUT39Dp4eX3TQ1N6rc/H/V5IitzfWrcsQXWRFbVmY/QTPn/P RyWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=jjz1DvrHl19dcFV+6svvaTdR6ONzAzl0klfwtl4NDd8=; b=Dz21pMghLSrwU/Rwp4rcrTuHxHIck2DXFdYGbHvmpAG/nyVt8d+/xWZowrQQwr1sqq oCckpM/ChbnkWwnVxeguG0VRvb9BtDLyRYHlvG55m3CS0gWau5gLWRVJyuKqXOdWn9Ll jbX2uglspM9hXESW2hpzGCvnk2ax92fQcwejGxga3UfZOJad93yQMW+uDuQYQ5KOcG91 22ObP3mQrGtCdx0arL5coDikuCSQTV0z8vJvTcGQ50aLm7CUNqhBMtO9y+xGf9Ypbr3F gNnZH2yo9aNh1XW4Df2aP321Unqnq9HqMztF0aMj5j7qBBVqX7V4iwEkhcMm0qid8zJP RNOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DPGwbWkU; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 69si6872611pfh.27.2017.10.09.05.03.28; Mon, 09 Oct 2017 05:03:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DPGwbWkU; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753964AbdJIMDR (ORCPT + 8 others); Mon, 9 Oct 2017 08:03:17 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:30035 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdJIMDP (ORCPT ); Mon, 9 Oct 2017 08:03:15 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v99C37Im008317; Mon, 9 Oct 2017 07:03:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507550587; bh=xBbo4Jnzf5MokOu/XWwZtf80JVq7oX66tVXeSgtahjE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DPGwbWkUvY4iZ1gVbiCP5LALQnxnWxA+5VSboIDmiaz7TP8r+t7Ux8JCplwRNnLvH VXj9Q/afC0/yuKGwFzL2pycU5OqBxtUqyiQuaNlpseqyMZlAPDm/BqsBk3tV7OcGBr d1iD1qpiRZgcNdoabzt51UpqsE7XG/LoX8SoLQVs= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v99C3728005656; Mon, 9 Oct 2017 07:03:07 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 9 Oct 2017 07:03:07 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 9 Oct 2017 07:03:06 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v99C36tH005400; Mon, 9 Oct 2017 07:03:07 -0500 Received: from localhost ([172.22.136.90]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v99C36311500; Mon, 9 Oct 2017 07:03:06 -0500 (CDT) From: Dan Murphy To: , CC: , , , Dan Murphy Subject: [PATCH v3 2/3] net: phy: DP83822 initial driver submission Date: Mon, 9 Oct 2017 07:03:01 -0500 Message-ID: <20171009120302.23611-2-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20171009120302.23611-1-dmurphy@ti.com> References: <20171009120302.23611-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for the TI DP83822 10/100Mbit ethernet phy. The DP83822 provides flexibility to connect to a MAC through a standard MII, RMII or RGMII interface. Datasheet: http://www.ti.com/product/DP83822I/datasheet Signed-off-by: Dan Murphy --- v3 - Fixed WoL indication bit and removed mutex for suspend/resume - https://www.mail-archive.com/netdev@vger.kernel.org/msg191891.html and https://www.mail-archive.com/netdev@vger.kernel.org/msg191665.html v2 - Updated per comments. Removed unnessary parantheis, called genphy_suspend/ resume routines and then performing WoL changes, reworked sopass storage and reduced the number of phy reads, and moved WOL_SECURE_ON - https://www.mail-archive.com/netdev@vger.kernel.org/msg191392.html drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83822.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+) create mode 100644 drivers/net/phy/dp83822.c -- 2.14.0 Reviewed-by: Woojung Huh diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index cd931cf9dcc2..8e78a482e09e 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -277,6 +277,11 @@ config DAVICOM_PHY ---help--- Currently supports dm9161e and dm9131 +config DP83822_PHY + tristate "Texas Instruments DP83822 PHY" + ---help--- + Supports the DP83822 PHY. + config DP83848_PHY tristate "Texas Instruments DP83848 PHY" ---help--- diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 416df92fbf4f..df3b82ba8550 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CICADA_PHY) += cicada.o obj-$(CONFIG_CORTINA_PHY) += cortina.o obj-$(CONFIG_DAVICOM_PHY) += davicom.o obj-$(CONFIG_DP83640_PHY) += dp83640.o +obj-$(CONFIG_DP83822_PHY) += dp83822.o obj-$(CONFIG_DP83848_PHY) += dp83848.o obj-$(CONFIG_DP83867_PHY) += dp83867.o obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c new file mode 100644 index 000000000000..de196dbc46cd --- /dev/null +++ b/drivers/net/phy/dp83822.c @@ -0,0 +1,302 @@ +/* + * Driver for the Texas Instruments DP83822 PHY + * + * Copyright (C) 2017 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DP83822_PHY_ID 0x2000a240 +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_MISR1 0x12 +#define MII_DP83822_MISR2 0x13 +#define MII_DP83822_RESET_CTRL 0x1f + +#define DP83822_HW_RESET BIT(15) +#define DP83822_SW_RESET BIT(14) + +/* MISR1 bits */ +#define DP83822_RX_ERR_HF_INT_EN BIT(0) +#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) +#define DP83822_ANEG_COMPLETE_INT_EN BIT(2) +#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) +#define DP83822_SPEED_CHANGED_INT_EN BIT(4) +#define DP83822_LINK_STAT_INT_EN BIT(5) +#define DP83822_ENERGY_DET_INT_EN BIT(6) +#define DP83822_LINK_QUAL_INT_EN BIT(7) + +/* MISR2 bits */ +#define DP83822_JABBER_DET_INT_EN BIT(0) +#define DP83822_WOL_PKT_INT_EN BIT(1) +#define DP83822_SLEEP_MODE_INT_EN BIT(2) +#define DP83822_MDI_XOVER_INT_EN BIT(3) +#define DP83822_LB_FIFO_INT_EN BIT(4) +#define DP83822_PAGE_RX_INT_EN BIT(5) +#define DP83822_ANEG_ERR_INT_EN BIT(6) +#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) + +/* INT_STAT1 bits */ +#define DP83822_WOL_INT_EN BIT(4) +#define DP83822_WOL_INT_STAT BIT(12) + +#define MII_DP83822_RXSOP1 0x04a5 +#define MII_DP83822_RXSOP2 0x04a6 +#define MII_DP83822_RXSOP3 0x04a7 + +/* WoL Registers */ +#define MII_DP83822_WOL_CFG 0x04a0 +#define MII_DP83822_WOL_STAT 0x04a1 +#define MII_DP83822_WOL_DA1 0x04a2 +#define MII_DP83822_WOL_DA2 0x04a3 +#define MII_DP83822_WOL_DA3 0x04a4 + +/* WoL bits */ +#define DP83822_WOL_MAGIC_EN BIT(1) +#define DP83822_WOL_SECURE_ON BIT(5) +#define DP83822_WOL_EN BIT(7) +#define DP83822_WOL_INDICATION_SEL BIT(8) +#define DP83822_WOL_CLR_INDICATION BIT(11) + +static int dp83822_ack_interrupt(struct phy_device *phydev) +{ + int err = phy_read(phydev, MII_DP83822_MISR1); + + if (err < 0) + return err; + + err = phy_read(phydev, MII_DP83822_MISR2); + if (err < 0) + return err; + + return 0; +} + +static int dp83822_set_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + struct net_device *ndev = phydev->attached_dev; + u16 value; + const u8 *mac; + + if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { + mac = (const u8 *)ndev->dev_addr; + + if (!is_valid_ether_addr(mac)) + return -EINVAL; + + /* MAC addresses start with byte 5, but stored in mac[0]. + * 822 PHYs store bytes 4|5, 2|3, 0|1 + */ + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_DA1, (mac[1] << 8) | mac[0]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_DA2, (mac[3] << 8) | mac[2]); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, + (mac[5] << 8) | mac[4]); + + value = phy_read_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_CFG); + if (wol->wolopts & WAKE_MAGIC) + value |= DP83822_WOL_MAGIC_EN; + else + value &= ~DP83822_WOL_MAGIC_EN; + + if (wol->wolopts & WAKE_MAGICSECURE) { + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP1, + (wol->sopass[1] << 8) | wol->sopass[0]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP2, + (wol->sopass[3] << 8) | wol->sopass[2]); + phy_write_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RXSOP3, + (wol->sopass[5] << 8) | wol->sopass[4]); + value |= DP83822_WOL_SECURE_ON; + } else { + value &= ~DP83822_WOL_SECURE_ON; + } + + value |= (DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | + DP83822_WOL_CLR_INDICATION); + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, + value); + } else { + value = phy_read_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_WOL_CFG); + value &= ~DP83822_WOL_EN; + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, + value); + } + + return 0; +} + +static void dp83822_get_wol(struct phy_device *phydev, + struct ethtool_wolinfo *wol) +{ + int value; + u16 sopass_val; + + wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); + wol->wolopts = 0; + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + if (value & DP83822_WOL_MAGIC_EN) + wol->wolopts |= WAKE_MAGIC; + + if (~value & DP83822_WOL_CLR_INDICATION) + wol->wolopts = 0; + + if (value & DP83822_WOL_SECURE_ON) { + wol->wolopts |= WAKE_MAGICSECURE; + } else { + wol->wolopts &= ~WAKE_MAGICSECURE; + return; + } + + sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP1); + wol->sopass[0] = (sopass_val & 0xff); + wol->sopass[1] = (sopass_val >> 8); + + sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP2); + wol->sopass[2] = (sopass_val & 0xff); + wol->sopass[3] = (sopass_val >> 8); + + sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RXSOP3); + wol->sopass[4] = (sopass_val & 0xff); + wol->sopass[5] = (sopass_val >> 8); +} + +static int dp83822_config_intr(struct phy_device *phydev) +{ + int misr_status; + int err; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { + misr_status = phy_read(phydev, MII_DP83822_MISR1); + if (misr_status < 0) + return misr_status; + + misr_status |= (DP83822_RX_ERR_HF_INT_EN | + DP83822_FALSE_CARRIER_HF_INT_EN | + DP83822_ANEG_COMPLETE_INT_EN | + DP83822_DUP_MODE_CHANGE_INT_EN | + DP83822_SPEED_CHANGED_INT_EN | + DP83822_LINK_STAT_INT_EN | + DP83822_ENERGY_DET_INT_EN | + DP83822_LINK_QUAL_INT_EN); + + err = phy_write(phydev, MII_DP83822_MISR1, misr_status); + if (err < 0) + return err; + + misr_status = phy_read(phydev, MII_DP83822_MISR2); + if (misr_status < 0) + return misr_status; + + misr_status |= (DP83822_JABBER_DET_INT_EN | + DP83822_WOL_PKT_INT_EN | + DP83822_SLEEP_MODE_INT_EN | + DP83822_MDI_XOVER_INT_EN | + DP83822_LB_FIFO_INT_EN | + DP83822_PAGE_RX_INT_EN | + DP83822_ANEG_ERR_INT_EN | + DP83822_EEE_ERROR_CHANGE_INT_EN); + + err = phy_write(phydev, MII_DP83822_MISR2, misr_status); + } else { + err = phy_write(phydev, MII_DP83822_MISR1, 0); + if (err < 0) + return err; + + err = phy_write(phydev, MII_DP83822_MISR1, 0); + } + + return err; +} + +static int dp83822_phy_reset(struct phy_device *phydev) +{ + int err; + + err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_HW_RESET); + if (err < 0) + return err; + + return 0; +} + +static int dp83822_suspend(struct phy_device *phydev) +{ + int value; + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + + if (!(value & DP83822_WOL_EN)) + genphy_suspend(phydev); + + return 0; +} + +static int dp83822_resume(struct phy_device *phydev) +{ + int value; + + genphy_resume(phydev); + + value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); + + phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | + DP83822_WOL_CLR_INDICATION); + + + return 0; +} + +static struct phy_driver dp83822_driver[] = { + { + .phy_id = DP83822_PHY_ID, + .phy_id_mask = 0xfffffff0, + .name = "TI DP83822", + .features = PHY_BASIC_FEATURES, + .flags = PHY_HAS_INTERRUPT, + .config_init = genphy_config_init, + .soft_reset = dp83822_phy_reset, + .get_wol = dp83822_get_wol, + .set_wol = dp83822_set_wol, + .ack_interrupt = dp83822_ack_interrupt, + .config_intr = dp83822_config_intr, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .suspend = dp83822_suspend, + .resume = dp83822_resume, + }, +}; +module_phy_driver(dp83822_driver); + +static struct mdio_device_id __maybe_unused dp83822_tbl[] = { + { DP83822_PHY_ID, 0xfffffff0 }, + { }, +}; +MODULE_DEVICE_TABLE(mdio, dp83822_tbl); + +MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); +MODULE_AUTHOR("Dan Murphy X-Patchwork-Id: 115202 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp2472985qgn; Mon, 9 Oct 2017 05:03:21 -0700 (PDT) X-Google-Smtp-Source: AOwi7QC3VIdZHGqA5lXkxC8TW2Elrnh/PquvlkL3qsNi0B5xRlmGLK0nBbdU1O92bIePR/aj1V6C X-Received: by 10.98.158.211 with SMTP id f80mr9969840pfk.156.1507550601620; Mon, 09 Oct 2017 05:03:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507550601; cv=none; d=google.com; s=arc-20160816; b=SskcTBAEAin2afqMrQThEssSaXR3zcVueLT7Fgyf8kh7lbNlJaOSfPmnUQgTmXq3PU jbfHU3jWsROOBtXZsKDp2v0PG19Px+TX+3hnFsRJdgKfqazi0HQwJJqGlyBkRg9hDWT1 anElyhE/XhW3Igc3KmksOcAZRl5JpiOrcqRftcP2DyUIUb3BlMOUF1TGXXC9H+UCXMog L23s4fG9SW68m5IL8Ht2LFUNWcJ1qXE64IUWduXl2Aq7Ls8ZCFw6UTgvmV6yc4JQ9jGi AN2WLCC+NRVnIQvLbwLAAy04cVMrVuutIITa3fr2BKXKjwnYCOSjocHNltnUPYWAWgSN fGiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; 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[209.132.180.67]) by mx.google.com with ESMTP id 69si6872611pfh.27.2017.10.09.05.03.21; Mon, 09 Oct 2017 05:03:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MAkPxAC2; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754049AbdJIMDT (ORCPT + 8 others); Mon, 9 Oct 2017 08:03:19 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45148 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751635AbdJIMDQ (ORCPT ); Mon, 9 Oct 2017 08:03:16 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v99C38St005543; Mon, 9 Oct 2017 07:03:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507550588; bh=hNobTR6px4SY7xk1GMv1ytWl/uK1nWPKM+UBnq5JjiI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MAkPxAC2bBqJJZo99sadwiT2hnGulmTE9U8Hy8ep8oB2ExMLweQpOa0WdCdRxCxRP jrtI8KRJGOOvkmKS5gmRIgg9net42i69VoD1xy/niipzvsP1eJICIKA4N487e7jIOw gTRViL1viDCtxaAxAO4YOScDsTnREhDH7EjH4Gs0= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v99C38GF016515; Mon, 9 Oct 2017 07:03:08 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 9 Oct 2017 07:03:07 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 9 Oct 2017 07:03:07 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v99C37ZC032089; Mon, 9 Oct 2017 07:03:07 -0500 Received: from localhost ([172.22.136.90]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v99C37311505; Mon, 9 Oct 2017 07:03:07 -0500 (CDT) From: Dan Murphy To: , CC: , , , Dan Murphy Subject: [PATCH v3 3/3] net: phy: Change error to EINVAL for invalid MAC Date: Mon, 9 Oct 2017 07:03:02 -0500 Message-ID: <20171009120302.23611-3-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20171009120302.23611-1-dmurphy@ti.com> References: <20171009120302.23611-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Change the return error code to EINVAL if the MAC address is not valid in the set_wol function. Signed-off-by: Dan Murphy --- v3 - No changes made v2 - There was no v1 on this patch this is new. drivers/net/phy/at803x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.14.0 diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index c1e52b9dc58d..5f93e6add563 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -167,7 +167,7 @@ static int at803x_set_wol(struct phy_device *phydev, mac = (const u8 *) ndev->dev_addr; if (!is_valid_ether_addr(mac)) - return -EFAULT; + return -EINVAL; for (i = 0; i < 3; i++) { phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,