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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers Date: Thu, 23 Jul 2020 17:28:01 -0700 Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 5 +++++ target/riscv/fpu_helper.c | 42 +++++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 19 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei Reviewed-by: Chih-Min Chao diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 37d33820ad..9f4ba7d617 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1); #define SEW32 2 #define SEW64 3 +static inline uint64_t nanbox_s(float32 f) +{ + return f | MAKE_64BIT_MASK(32, 32); +} + #endif diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 4379756dc4..72541958a7 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,10 +81,16 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3, int flags) +{ + return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_status)); +} + uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, 0, &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, 0); } uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -96,8 +102,7 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c, - &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c); } uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -110,8 +115,7 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product, - &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product); } uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -124,8 +128,8 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c | - float_muladd_negate_product, &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, + float_muladd_negate_c | float_muladd_negate_product); } uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -137,37 +141,37 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_add(frs1, frs2, &env->fp_status); + return nanbox_s(float32_add(frs1, frs2, &env->fp_status)); } uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_sub(frs1, frs2, &env->fp_status); + return nanbox_s(float32_sub(frs1, frs2, &env->fp_status)); } uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_mul(frs1, frs2, &env->fp_status); + return nanbox_s(float32_mul(frs1, frs2, &env->fp_status)); } uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_div(frs1, frs2, &env->fp_status); + return nanbox_s(float32_div(frs1, frs2, &env->fp_status)); } uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_minnum(frs1, frs2, &env->fp_status); + return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); } uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_maxnum(frs1, frs2, &env->fp_status); + return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status)); } uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1) { - return float32_sqrt(frs1, &env->fp_status); + return nanbox_s(float32_sqrt(frs1, &env->fp_status)); } target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) @@ -209,23 +213,23 @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1) uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1) { - return int32_to_float32((int32_t)rs1, &env->fp_status); + return nanbox_s(int32_to_float32((int32_t)rs1, &env->fp_status)); } uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1) { - return uint32_to_float32((uint32_t)rs1, &env->fp_status); + return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status)); } #if defined(TARGET_RISCV64) uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1) { - return int64_to_float32(rs1, &env->fp_status); + return nanbox_s(int64_to_float32(rs1, &env->fp_status)); } uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) { - return uint64_to_float32(rs1, &env->fp_status); + return nanbox_s(uint64_to_float32(rs1, &env->fp_status)); } #endif @@ -266,7 +270,7 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - return float64_to_float32(rs1, &env->fp_status); + return nanbox_s(float64_to_float32(rs1, &env->fp_status)); } uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) From patchwork Fri Jul 24 00:28:02 2020 Content-Type: text/plain; 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Date: Thu, 23 Jul 2020 17:28:02 -0700 Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not depend on the RVD extension, take input and output via TCGv_i64 instead of fpu regno. Move the function to translate.c so that it can be used in multiple trans_*.inc.c files. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 16 +--------------- target/riscv/translate.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei Reviewed-by: Chih-Min Chao Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 3bfd8881e7..c7057482e8 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -23,20 +23,6 @@ return false; \ } while (0) -/* - * RISC-V requires NaN-boxing of narrower width floating - * point values. This applies when a 32-bit value is - * assigned to a 64-bit FP register. Thus this does not - * apply when the RVD extension is not present. - */ -static void gen_nanbox_fpr(DisasContext *ctx, int regno) -{ - if (has_ext(ctx, RVD)) { - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], - MAKE_64BIT_MASK(32, 32)); - } -} - static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_fpr(ctx, a->rd); + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); tcg_temp_free(t0); mark_fs_dirty(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..12a746da97 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* + * RISC-V requires NaN-boxing of narrower width floating point values. + * This applies when a 32-bit value is assigned to a 64-bit FP register. + * For consistency and simplicity, we nanbox results even when the RVD + * extension is not present. + */ +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); From patchwork Fri Jul 24 00:28:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247103 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1978884ilg; Thu, 23 Jul 2020 17:32:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyCjNToWLGj0s8lyiTAiCrK6sKBqt1nasd/g4XeZ7t1/dyxAUx8kRlYMt04k++9jZRhqKPy X-Received: by 2002:a05:6902:6c8:: with SMTP id m8mr10463990ybt.85.1595550778041; Thu, 23 Jul 2020 17:32:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595550778; cv=none; d=google.com; s=arc-20160816; b=N3fEz37dsEcbim2DOd+xNo8J2ajH8xHaVq8Un1/CKiCUA1ymi82dRlOElWZOmW71Ya DhIvPZGu0+cL+UTRpP6Ab63BHgYNi6ccl4J0oz5DY45d/z5tUhv0/7Kfvp6YIHCsfJLV wCMsdfL6FYoyYS3sB4hMkKJ4KS8kb2P//6d/ORdvfwXxsYZATToS8zwXcJYPry2urQyS cVc8FCXg4I+4M6iaUdLPHt0CeFIAg4Ys8Le0pBqbe+cm3E3jWU7H6sZbKqe8pnYmXaps SIicejZquIChhEUJaWp1fNyn8ug5dbwiU3aEebvP669QBEsWvOq6CpRHH3RBRTzLbQ2A zPZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9BL1gLZ55ebPF1CU6VCPP/FzwVosXUicPzzehG55MPU=; b=BjceGOY78JQkJRQ5YvVOQhaE8psELJ116IZULZYgeh9KkSM8D/e9m/pxilOmH1+GGB b4d8Fd9OaM8mHYLNF0Orv0vOYUtTS/fo24xW4aD4n545IDSnA4pgScnSWbO7ZtM5WWCe HU3kaWo4Kl+WDdjNabdNsJbN3SK+ZUpt5BuZceizetxyyvIueI/HBdeUSjNaVoJirYP8 L8UKrIRm785nntq+9evr9acA7R1lNqlNXwcfffvacQ0pxR7I3fO6h+TU3CgSKzould38 Qvo2ATYqNGaxhRAzC7Ha1zhLP4TpNjqouCtGyJGh5Jkm75/9LorJJWBksU/NcxKLBXlc H0/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qaRmjisP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c Date: Thu, 23 Jul 2020 17:28:03 -0700 Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make sure that all results from inline single-precision scalar operations are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.25.1 Reviewed-by: LIU Zhiwei Reviewed-by: Chih-Min Chao Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index c7057482e8..264d3139f1 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], 0, 31); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); tcg_temp_free_i64(t0); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); tcg_temp_free_i64(t0); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); tcg_temp_free(t0); From patchwork Fri Jul 24 00:28:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247100 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1976527ilg; Thu, 23 Jul 2020 17:29:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuWEGX0nz74oG74txhhID/9u/ko8f+w3OWz3t2JZAp5itPe5l5GLOKBVbO+eu2iP9Ga2M4 X-Received: by 2002:a25:bcca:: with SMTP id l10mr10196153ybm.298.1595550568336; Thu, 23 Jul 2020 17:29:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595550568; cv=none; d=google.com; s=arc-20160816; b=sBDu1N3hTMBbW86xRgy3DapqmnVY9sMv43c2DBRXfohEQ35o4QAoBAVfNKThR+Dk/X ic5ipMceQ1L6bIVXK5SxpEhHhB0g9FKMiBmsOyeQ3kb7pdZ6RF06fEYr0wk24Jk/LdqF pUwANylLqup0NFyUfM0wZQ/DwBMnJxv7LFt2w/7bMfu+7TbJ0N7qKZ8notG1uA19aq8O hEwNR3tV438OhB0TLWOpO5kAKs3emomY/EIe9KfB3554xUEmaM/iO77QWeQhLFw5O0Fw 9TwtY8SwgnmySt5USpbNeFzHZBuUnxkdFnG6ZyGztf8asG5/B80I9YkQvuXH7UbckPjj LdNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1utSzpi1MINPmUJjhg3agUHxuOyctwcD9LWDx9rrV3c=; b=OINF4InkxGZ8esldXRodqKIMUnr3bK5A8hxs4vIcKsrVva2q9gf5R6L1smM4j1TTdF 7WVeNuJEeoOI+ApgkSFyN/QUCfVK7ddrvJQUM7c+/GD+alBpXY3cMHLC9mJtxrjqEKdx Ky8V/69sqrM7oW3JJJ6vM4sU7TCN51OI32xWL3ozT0zkza+HkGBcF9vuqckvmfjwb84N XajgAj/oFNVWbrb1LV1b8iRCOZAc2Xt1lByJ0VnYLMWHcfqmULeMW/re+b5HV3FUKSqi lGk23MMy5oGlFoPxlev66gVV9KwKq3/+zYBehoQwwIKD2hkhs2pngHhhzxsm66eKx8bo F9fA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BX3os+dB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers Date: Thu, 23 Jul 2020 17:28:04 -0700 Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 11 +++++++ target/riscv/fpu_helper.c | 64 ++++++++++++++++++++++++++++----------- 2 files changed, 57 insertions(+), 18 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei Reviewed-by: Chih-Min Chao Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 9f4ba7d617..f1a546dba6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -43,4 +43,15 @@ static inline uint64_t nanbox_s(float32 f) return f | MAKE_64BIT_MASK(32, 32); } +static inline float32 check_nanbox_s(uint64_t f) +{ + uint64_t mask = MAKE_64BIT_MASK(32, 32); + + if (likely((f & mask) == mask)) { + return (uint32_t)f; + } else { + return 0x7fc00000u; /* default qnan */ + } +} + #endif diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 72541958a7..bb346a8249 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,9 +81,12 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } -static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3, int flags) +static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, + uint64_t rs3, int flags) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); + float32 frs3 = check_nanbox_s(rs3); return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_status)); } @@ -139,74 +142,97 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, float_muladd_negate_product, &env->fp_status); } -uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_add(frs1, frs2, &env->fp_status)); } -uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_sub(frs1, frs2, &env->fp_status)); } -uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_mul(frs1, frs2, &env->fp_status)); } -uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_div(frs1, frs2, &env->fp_status)); } -uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); } -uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status)); } -uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1) +uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return nanbox_s(float32_sqrt(frs1, &env->fp_status)); } -target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return float32_le(frs1, frs2, &env->fp_status); } -target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return float32_lt(frs1, frs2, &env->fp_status); } -target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return float32_eq_quiet(frs1, frs2, &env->fp_status); } -target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return float32_to_int32(frs1, &env->fp_status); } -target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return (int32_t)float32_to_uint32(frs1, &env->fp_status); } #if defined(TARGET_RISCV64) -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1) +uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return float32_to_int64(frs1, &env->fp_status); } -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1) +uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return float32_to_uint64(frs1, &env->fp_status); } #endif @@ -233,8 +259,9 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) } #endif -target_ulong helper_fclass_s(uint64_t frs1) +target_ulong helper_fclass_s(uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return fclass_s(frs1); } @@ -275,7 +302,8 @@ uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - return float32_to_float64(rs1, &env->fp_status); + float32 frs1 = check_nanbox_s(rs1); + return float32_to_float64(frs1, &env->fp_status); } uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) From patchwork Fri Jul 24 00:28:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247104 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1979765ilg; Thu, 23 Jul 2020 17:34:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycpwtlJQLZieyBL+AQZCOPT2f984Y5PC6tV/xxcV7Yu9GLe06uqgfb1lJubZ5gZ7p1RUZz X-Received: by 2002:a25:af8b:: with SMTP id g11mr10776874ybh.456.1595550865453; Thu, 23 Jul 2020 17:34:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595550865; cv=none; d=google.com; s=arc-20160816; b=ZMOSZvM9nbllVxYxLmgnfHpCUzAkp6rAJuFqq/nBxWjtJZveCIJMeXKyfRJVEvnnlv tpA3pZ7jfivM0hFZRFXa5iQrot4WW6hvAOQWyHfX6yfedu9trhFzu5Z3I6M2KrmEbzgK GX6PEs1Xk7e9xjxTXbnGWu40tr9xrY6jSSyW+3S1pGN+1dd8LCTdC5O6ImQROczjh7j1 9k0+jcn64h6WQ7PhCIqOYX1iD1qYRy7uCq5lJN33e03zPYBN2xgpj71tAHM8qYAemC49 ya9ULT6fWDpnl7VAMhjSoJqjQnPOZnlt9Z2AFI7Pzgp6AVMypdBOTmhfGDtvHmDdAbgU zn+w== ARC-Message-Signature: i=1; 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c Date: Thu, 23 Jul 2020 17:28:05 -0700 Message-Id: <20200724002807.441147-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. The only inline expansion is for the sign-changing set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S. Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 71 +++++++++++++++++++------ target/riscv/translate.c | 18 +++++++ 2 files changed, 73 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: LIU Zhiwei Reviewed-by: Chih-Min Chao Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 264d3139f1..f9a9e0643a 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -161,47 +161,86 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + if (a->rs1 == a->rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + gen_check_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rs1]); } else { /* FSGNJ */ - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], - 0, 31); + TCGv_i64 rs1 = tcg_temp_new_i64(); + TCGv_i64 rs2 = tcg_temp_new_i64(); + + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* This formulation retains the nanboxing of rs2. */ + tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 31); + tcg_temp_free_i64(rs1); + tcg_temp_free_i64(rs2); } - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) { + TCGv_i64 rs1, rs2, mask; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + if (a->rs1 == a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN); + tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(31, 1)); } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); - tcg_temp_free_i64(t0); + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* + * Replace bit 31 in rs1 with inverse in rs2. + * This formulation retains the nanboxing of rs1. + */ + mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1)); + tcg_gen_andc_i64(rs2, mask, rs2); + tcg_gen_and_i64(rs1, mask, rs1); + tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(mask); + tcg_temp_free_i64(rs2); } - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + tcg_temp_free_i64(rs1); + mark_fs_dirty(ctx); return true; } static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) { + TCGv_i64 rs1, rs2; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + if (a->rs1 == a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN); + tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(31, 1)); } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN); - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); - tcg_temp_free_i64(t0); + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* + * Xor bit 31 in rs1 with that in rs2. + * This formulation retains the nanboxing of rs1. + */ + tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(31, 1)); + tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(rs2); } - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + tcg_temp_free_i64(rs1); + mark_fs_dirty(ctx); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 12a746da97..bf35182776 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,24 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +/* + * A narrow n-bit operation, where n < FLEN, checks that input operands + * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. + * If so, the least-significant bits of the input are used, otherwise the + * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). + * + * Here, the result is always nan-boxed, even the canonical nan. + */ +static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull); + TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull); + + tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); + tcg_temp_free_i64(t_max); + tcg_temp_free_i64(t_nan); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 6/7] target/riscv: Clean up fmv.w.x Date: Thu, 23 Jul 2020 17:28:06 -0700 Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Use tcg_gen_extu_tl_i64 to avoid the ifdef. Signed-off-by: LIU Zhiwei Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.25.1 Reviewed-by: Chih-Min Chao Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index f9a9e0643a..0d04677a02 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); -#if defined(TARGET_RISCV64) - tcg_gen_mov_i64(cpu_fpr[a->rd], t0); -#else - tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); -#endif + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); From patchwork Fri Jul 24 00:28:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247105 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1980697ilg; Thu, 23 Jul 2020 17:35:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxb0mVBDE96znUhMUfsXhg3a2IxWlbJX16I2zVFKweCwAVlG58Io3dSlsKan7LLu6/HQzm0 X-Received: by 2002:a5b:589:: with SMTP id l9mr8520012ybp.404.1595550954922; Thu, 23 Jul 2020 17:35:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595550954; cv=none; d=google.com; s=arc-20160816; b=MUGij6HByk8SBc2zO+Le/QBdVBSqVGeVfSd8ILQKlICluAYq9RAFRIIQk7loM8/U8q f/TwKrmwLshvDOYxf04beF3kCAd55sAxqnXdEoX2d0FW9Ofc7nL2CEJk+GJQkxpYJaXj jnndPiTNxaqI0IO71zsofApnZIxcG45kPAdI6Qv2Djh4KYhSltqIEstPRIQVcELyTYtx 2V8XDKqJ/KcTNodJzBtb++sKZOoUb+IzlE65hbnUJFf//bbR5J9L3glVYNXVF89ayQ6C 4pNScedZpJYpuxhW/YWgf+DKMiAcn50Q3sHnKl77s2qdKLxzoZpm5kTHX04Mn6CamT8B Eizg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jQCpNdFJsrF3Bpi0rRRCXqsUrN96754LDnpff+tQIzo=; b=ZIb+dvcakgC2/3gcSRg2IHf37zaRywn+HmmGaKplY9xPiiMUTCMtgK6tb2VZ9PhaZG j5PAtKzNp4IWdc5r8p0ovM4wDZhpCMJhsaACvbfkeLCJPi/9rIL9vEGLgvyaWwSvThcM RsfP0ODwI+bgm9GhuAhzcRgmej7vteWcnuVYb643/aj0uZ/4fn6FiQX/QDaxNfvCp5qr bnX8uF0vSEEp0WQ7ylbzd+6d58ULeAtKt+38cdURTMqtwpbQJuEK7mD82zcdsgq13AsO hZZuUGZkkD6i72v11cHZ+CDQ2yvgTm991uQ7MXkEHMyWZ0UHfPav4wJvUAUYyXOkQj98 t0hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FScUEfH+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 7/7] target/riscv: check before allocating TCG temps Date: Thu, 23 Jul 2020 17:28:07 -0700 Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org> References: <20200724002807.441147-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++---- target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Chih-Min Chao Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index ea1044f13b..4f832637fa 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -20,10 +20,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 0d04677a02..16df9c5ee2 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -25,10 +25,10 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); @@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);