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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id r191sm7261663pfr.181.2020.07.24.09.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2020 09:38:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/3] hw/arm/boot: Fix PAUTH for EL3 direct kernel boot Date: Fri, 24 Jul 2020 09:38:51 -0700 Message-Id: <20200724163853.504655-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724163853.504655-1-richard.henderson@linaro.org> References: <20200724163853.504655-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, vincenzo.frascino@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When booting an EL3 cpu with -kernel, we set up EL3 and then drop down to EL2. We need to enable access to v8.3-PAuth keys and instructions at EL3 before doing so. Signed-off-by: Richard Henderson --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.25.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index fef4072db1..c44fd3382d 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -736,6 +736,9 @@ static void do_cpu_reset(void *opaque) } else { env->pstate = PSTATE_MODE_EL1h; } + if (cpu_isar_feature(aa64_pauth, cpu)) { + env->cp15.scr_el3 |= SCR_API | SCR_APK; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: From patchwork Fri Jul 24 16:38:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247136 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2615478ilg; Fri, 24 Jul 2020 09:40:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOK6sB4cwr6vxMRlZfHSaHJS+Dc/LHakPKizfrZt/AV64wjbkCb5j2K9W27AzwOzCrUzzQ X-Received: by 2002:a25:da10:: with SMTP id n16mr16386890ybf.373.1595608844923; Fri, 24 Jul 2020 09:40:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595608844; cv=none; d=google.com; s=arc-20160816; b=NV412JfmKsICPCVI9FfR9QVmDLjwWkN3WVEjYhLtCut2/ZN1SQXtMhy7+vAg+AZ/Qo Y48O1V9/UYJif9KPSbOf70/90xdQd8W61xL9Fc11IZqXtF7gQriFbXvZ+zwPSKDZl7tE 6vwHEczVnPyhExHnZblLCejcue0+05O0NA6YqBJ3r8iM+Fqge9xLt7bEnrRf+A9ugIbE dMBaJiNlbBtV66ByMHu+ro+rk5FxtRxI329DBH92Xbtj48VJ5MbTdEFFVm5iAS15OC9n HUdt3pkdfALuQ0l0x6TFblULEvLbSDF8wIwjI94L+7OkM2wlVNnN6sQjW2v2Besy6QXj ESww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lOHdNtnGRgA8GSOMatWc2CH3AkgDKMG7+oF07eCfw/c=; b=bLgFYOxJBykS9SqnfySDahrAmLICLfvNsMR6LJC3QSk8SOhFXr+5ecUjYMwHR3YvEz KuXT/EFj+zbIVgBipcoXziIgyhVaVAQqnw9eBQDykGSB3fQPovG1Jt90u5F2vzLn1jk8 0vcPgLGJeJFVy3SAvcygMsoZMLiAy/lJvypJUNLm10Oo99rVeFAW8UafQlLfiJYfLJe1 3Pbun+h1Plu12mGcp+8gRDeormzmaZaYqOOCQayJ73EInUnvbrjtQo2GqX1ww1/1BtXJ fm0+PpznbtseyxYFGH6yCzoK7Y64WODnWXvOr2K8qgKf5kO0W59E/TIptnT/3s2LYddZ OIWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jLJPYVYh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id r191sm7261663pfr.181.2020.07.24.09.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2020 09:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/3] hw/arm/boot: Fix MTE for EL3 direct kernel boot Date: Fri, 24 Jul 2020 09:38:52 -0700 Message-Id: <20200724163853.504655-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724163853.504655-1-richard.henderson@linaro.org> References: <20200724163853.504655-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, vincenzo.frascino@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When booting an EL3 cpu with -kernel, we set up EL3 and then drop down to EL2. We need to enable access to v8.5-MemTag tag allocation at EL3 before doing so. Reported-by: Peter Maydell Signed-off-by: Richard Henderson --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.25.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index c44fd3382d..3e9816af80 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -739,6 +739,9 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_pauth, cpu)) { env->cp15.scr_el3 |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + env->cp15.scr_el3 |= SCR_ATA; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: From patchwork Fri Jul 24 16:38:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 247135 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2614660ilg; Fri, 24 Jul 2020 09:39:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyLHRJaAgRv+T4VaOxvtZZIwIGlxOU+XpDmLLnLG7aM7A0Vzo/8qg6jQvaJHDpMeiXzPU+D X-Received: by 2002:a25:803:: with SMTP id 3mr16809257ybi.518.1595608779448; Fri, 24 Jul 2020 09:39:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595608779; cv=none; d=google.com; s=arc-20160816; b=pnIGZnJUWUimNaY1BC51D2G6Kt6Tamb9be1OWmuKrjiWfp3duB7uYR3IYt1uTjnvUo USsHQ54m0U/F1gvqIMCuzW/mCSz0GZFN2agOHwwD7DdY6AXDticMs76IwZJnMIxIak4K Tey3esbdtHoh0pwpcQ0pn57i1s2toUlxHo5CwPfUn86BoOGdZjJRQ76TGtLT4XZgAXVc 7rvsBK8NqmnsjbL82D29fAWznXPYqaRro/AdPczs6gPK3MgumGbhVZvJO7NZC+HkvMDs eUjIUrLxflf6jKc9hZnoRVYrHHvB/qyeLlM2nCfVLVAVjvEq2cKL0pPE0f37hMi2QrTi h3iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GFpd1WzRdKHPdu50aGofJzb2YYZBrwx+q9wbcazemUg=; b=pSPeUHrWtRqBXJcNhoqISwU7zdSt4O1i9WM0ib1TFoXE5gxmg1IQQTilkpvtsJkEdd h66CxDvSW2GfjKkblJgrNYtO8STrmMssCJ2plPJ71dd2wnrehl0Hj0HvW8Ck9A1VRYpf qL0/ZYfVaX9WVc/uBuk/2DxXLRi5NQL0Mj5QcpqblkX8OCLh3xCZmxIicNTlvn1phL/V 8VnHVJFukI+D0boXo8RNMPTPlTa49GH17tKv8pqZXjo4nGDjknjbDIXpcxTqpf68Ofd1 vsBHrrO9Hc0Rfzlq0G8d34QxU/0PU1MSEa1It8mIrbOCmuDKfciC3pLMlPIm22LuXCbI r+QA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O3G1OrLb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id r191sm7261663pfr.181.2020.07.24.09.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2020 09:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Improve IMPDEF algorithm for IRG Date: Fri, 24 Jul 2020 09:38:53 -0700 Message-Id: <20200724163853.504655-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200724163853.504655-1-richard.henderson@linaro.org> References: <20200724163853.504655-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, vincenzo.frascino@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF, and the kernel is not expected to have set RGSR_EL1. Force a non-zero value into SEED, so that we do not continually return the same tag. Reported-by: Vincenzo Frascino Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 5ea57d487a..104752041f 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -24,6 +24,8 @@ #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "qapi/error.h" +#include "qemu/guest-random.h" static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) @@ -211,16 +213,37 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) { - int rtag; - - /* - * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if - * GCR_EL1.RRND==0, always producing deterministic results. - */ uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); + int rrnd = extract32(env->cp15.gcr_el1, 16, 1); int start = extract32(env->cp15.rgsr_el1, 0, 4); int seed = extract32(env->cp15.rgsr_el1, 8, 16); - int offset, i; + int offset, i, rtag; + + /* + * Our IMPDEF choice for GCR_EL1.RRND==1 is to continue to use the + * deterministic algorithm. Except that with RRND==1 the kernel is + * not required to have set RGSR_EL1.SEED != 0, which is required for + * the deterministic algorithm to function. So we force a non-zero + * SEED for that case. + */ + if (unlikely(seed == 0) && rrnd) { + do { + Error *err = NULL; + uint16_t two; + + if (qemu_guest_getrandom(&two, sizeof(two), &err) < 0) { + /* + * Failed, for unknown reasons in the crypto subsystem. + * Best we can do is log the reason and use a constant seed. + */ + qemu_log_mask(LOG_UNIMP, "IRG: Crypto failure: %s\n", + error_get_pretty(err)); + error_free(err); + two = 1; + } + seed = two; + } while (seed == 0); + } /* RandomTag */ for (i = offset = 0; i < 4; ++i) {