From patchwork Mon Jul 27 15:19:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247189 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4890808ilg; Mon, 27 Jul 2020 08:20:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3KTKbLmbo9v6uz/uYbWp/cxczgtQdRFH24EJAj2MyAlB+5efP48TlIeAnDFJ7he2mzxL0 X-Received: by 2002:a25:bdcb:: with SMTP id g11mr33081215ybk.464.1595863217648; Mon, 27 Jul 2020 08:20:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863217; cv=none; d=google.com; s=arc-20160816; b=RoETxSBykf1GH24VmesntmwpfXcgNAOgx1X49TCdDYDU2ZqoMXjLGtZ441WFKlPGvt c7xheByCebfJ0gx5QBZBcHsAJeTTx5/crQg2ORR6PAH4DFBvar0qikO+jSHR3aKLTqug d6CrkgswuTQc54ZbmY13dXGKvhgK+/Ty7a5GQ3hNexv4W8rKwrQIsTw4ROSInmkIUNfD DbjrEOkXBbqh2/rxfNHLjFFC6NW09XLBU+urUsXhErin4A1yXeclSuhtKGkh+Fi6leRU BavZgBsELfJ6OSEyMOMnNDvDNQllePtvRlu9Z6OW1tQPEsx+kVWLSHaFRx1jTM6ecF06 qQAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uOYlhryYGKuk9GHY1annootwLvGZo9Yx/GyMtSFdjtA=; b=LX3NThnT00fg/Q7D4dt2EPLZN3qBWtpzPU5AdRjox/p3+ccDSXLVST6T1fLE84l/iS hFuk8XnXwhflL15UV7TVaF0mMNqMqQRFx/FAgKkQ2bN5kwABNwtZq1NljZtg6yv36fnx N9A5YOFnnpeyzsX8phAIQZ2300iVIQ5Ud4BvH+O557LE+d3cwcwLELS5AkPHZn+KahEF USeG3MbEE3UvmfCIJfSyjZmbGj84NIsp2RRNjOSt2LPmxI9wVJLruirdZHmZwdR7p4PL /YfK4w1isqRtdzO4jiz9x4AM4Xqj98pGtoQU8FThUtdhF8MTmk528JzZAMWLSA2ywxH3 TnYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Kqm0/B/W"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g4si10484682ybj.172.2020.07.27.08.20.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Jul 2020 08:20:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Kqm0/B/W"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k04vJ-0001bp-3F for patch@linaro.org; Mon, 27 Jul 2020 11:20:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k04uZ-0001Yw-B4 for qemu-devel@nongnu.org; Mon, 27 Jul 2020 11:19:31 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41559) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k04uX-0001MB-KZ for qemu-devel@nongnu.org; Mon, 27 Jul 2020 11:19:31 -0400 Received: by mail-wr1-x42b.google.com with SMTP id r2so10202892wrs.8 for ; Mon, 27 Jul 2020 08:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uOYlhryYGKuk9GHY1annootwLvGZo9Yx/GyMtSFdjtA=; b=Kqm0/B/WozkP+XG2CKFgyPXDYDrLMQnhkh1nKqwyl9HbOmzMU0Fv4i0DcYrXGpY43h wfyf827TtCrhfJRS+d2jQd8PrU5Bjq+o+AGP4gzBUBYbM9S/u7QbEK1bQN+Ae48aMXEK ajzVXiTZuuFyCHHhK8vmqySZ7O/ip8fp3y+V8uMW4hI3JK1nHPsboNBmfUUgRL6L04UM +Mi2pFZOI2dWcXw3VknOZocy75p95BhQasd/9WoLELR0/lL1zYO4uIG5RfvHd1rfP/zO PAom2mv8lX5DTbPedvyHJSWeeLTiyZos6YTBfr+BareInztzvEQrh7/GJHhNTf74gtju U/iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uOYlhryYGKuk9GHY1annootwLvGZo9Yx/GyMtSFdjtA=; b=dRFRmw8XOf3fn6yZze6xl/lfGgo7LIzYYQLs9chBtkan8JU2pRixe7p9n6tfGaOF/s e0htcddJMagEYmCXSAAqUcTK01M00R2ghem7+Do4+YVB9qnc+XKt/IY3jnwu5fgjQYNc PpL3BhLfSju4Xuo9K8QF31OOmnggmNmCq0ifBB8gss6X+dTlEWQJpDLuzgNDASdIxeDO cWXxlGZ7AyrcY/aprSfLCH/DRIdjHVwolr8v6BfkxvyWO3Y8E3/PGwR1+O5t5G1fodya 46m9FCIS3b2O3wZtU1UCkhQNleTfGbXgrT1k6gr4o+HAb4liilv5NSmY7iXHaVfjZEwJ bIIQ== X-Gm-Message-State: AOAM5324CxWO+rDoZivbR0C0xnHiGkwR88W62ZejJZKGYbewI5thoKgk C4WmPhP50En4oPtLVgp+ih2tefo82eR2sg== X-Received: by 2002:a5d:48c8:: with SMTP id p8mr20277745wrs.84.1595863164850; Mon, 27 Jul 2020 08:19:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/7] ACPI: Assert that we don't run out of the preallocated memory Date: Mon, 27 Jul 2020 16:19:14 +0100 Message-Id: <20200727151920.19150-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Dongjiu Geng data_length is a constant value, so we use assert instead of condition check. Signed-off-by: Dongjiu Geng Message-id: 20200622113146.33421-1-gengdongjiu@huawei.com Reviewed-by: Michael S. Tsirkin Signed-off-by: Peter Maydell --- hw/acpi/ghes.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index b363bc331d0..f0ee9f51caa 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -204,16 +204,12 @@ static int acpi_ghes_record_mem_error(uint64_t error_block_address, /* This is the length if adding a new generic error data entry*/ data_length = ACPI_GHES_DATA_LENGTH + ACPI_GHES_MEM_CPER_LENGTH; - /* - * Check whether it will run out of the preallocated memory if adding a new - * generic error data entry + * It should not run out of the preallocated memory if adding a new generic + * error data entry */ - if ((data_length + ACPI_GHES_GESB_SIZE) > ACPI_GHES_MAX_RAW_DATA_LENGTH) { - error_report("Not enough memory to record new CPER!!!"); - g_array_free(block, true); - return -1; - } + assert((data_length + ACPI_GHES_GESB_SIZE) <= + ACPI_GHES_MAX_RAW_DATA_LENGTH); /* Build the new generic error status block header */ acpi_ghes_generic_error_status(block, ACPI_GEBS_UNCORRECTABLE, From patchwork Mon Jul 27 15:19:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247191 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4892063ilg; Mon, 27 Jul 2020 08:21:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlZPC5STFcD0KXmpA5LOoHm24l16B718u/85l7pbKYI5iIL9CkuB9CE76LL1F+Ttw7gZeY X-Received: by 2002:a25:bb07:: with SMTP id z7mr32616778ybg.343.1595863311711; Mon, 27 Jul 2020 08:21:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863311; cv=none; d=google.com; s=arc-20160816; b=wV6ECuHSGzn1zvPHtgEzYMJ6CWpMmCuTSGgpZAEI1cuCTP7KQVILhpCRewteREkjzP /zinVl2XfQ9TgM72GciPHXUBtdwlXrM8plOkO0Cl2l8vTGqgsIwyKP1ULvjAfYTHdrDe dUw4t/e/QlCnT7OnrhZGI6bJf4RyyZGelazy4jST3bsmFn17FIv7ndtJBeutnQYpuoBe /JUC9yVBPTqi2kzS6yad59XPszWEPJP3Ndml5aLQZK9gX03ELgTvcjECOz1Q8vr39eiG E7G9BoPexLItDOo52+2hEcDkDcT0Q+QrKtYXRAOc3YJi7eqvF53OKqNbk9PGOle29hSN 1eZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=I7vtUCKWCL7jNAPS28tV4Fp/0HKktgVJJq19XFkLoME=; b=ifirQ3anIrvGEO8gIe6W3Al6nKAub46Dw44K3S96Qw26eL6eXR/Xy04KqNeaHsM5El Cl3fxr4wTGbRUYkzJo6OgUxlwjTBV+L0j0m1+mc/41dtwTlWK5dlu87m2LJFGaeofaQg ilT2ggM24gV9OgEgjD5pHZFk/023hk+fUgddET61uIMEtpl3WaI6cHMIpq4lKPMHaTs2 mgtgpxdCqwde8R08LmLIitz/BTfBA54gy2f3DQXA57oRdwa2TsO2D7WZq7dkxnZI7PzB whGPRE3gZ+MdtAapH1n2iIKz5EsgtsFfUEUyvNDsGFm2G6KkPH+il8QG71Z6hh/163in liRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gk4F3Wpk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/7] hw/misc/aspeed_sdmc: Fix incorrect memory size Date: Mon, 27 Jul 2020 16:19:15 +0100 Message-Id: <20200727151920.19150-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The SDRAM Memory Controller has a 32-bit address bus, thus supports up to 4 GiB of DRAM. There is a signed to unsigned conversion error with the AST2600 maximum memory size: (uint64_t)(2048 << 20) = (uint64_t)(-2147483648) = 0xffffffff40000000 = 16 EiB - 2 GiB Fix by using the IEC suffixes which are usually safer, and add an assertion check to verify the memory is valid. This would have caught this bug: $ qemu-system-arm -M ast2600-evb qemu-system-arm: hw/misc/aspeed_sdmc.c:258: aspeed_sdmc_realize: Assertion `asc->max_ram_size < 4 * GiB' failed. Aborted (core dumped) Fixes: 1550d72679 ("aspeed/sdmc: Add AST2600 support") Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/misc/aspeed_sdmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 0737d8de81d..855848b7d23 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -255,6 +255,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) AspeedSDMCState *s = ASPEED_SDMC(dev); AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); + assert(asc->max_ram_size < 4 * GiB); /* 32-bit address bus */ s->max_ram_size = asc->max_ram_size; memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s, @@ -341,7 +342,7 @@ static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); dc->desc = "ASPEED 2400 SDRAM Memory Controller"; - asc->max_ram_size = 512 << 20; + asc->max_ram_size = 512 * MiB; asc->compute_conf = aspeed_2400_sdmc_compute_conf; asc->write = aspeed_2400_sdmc_write; asc->valid_ram_sizes = aspeed_2400_ram_sizes; @@ -408,7 +409,7 @@ static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); dc->desc = "ASPEED 2500 SDRAM Memory Controller"; - asc->max_ram_size = 1024 << 20; + asc->max_ram_size = 1 * GiB; asc->compute_conf = aspeed_2500_sdmc_compute_conf; asc->write = aspeed_2500_sdmc_write; asc->valid_ram_sizes = aspeed_2500_ram_sizes; @@ -485,7 +486,7 @@ static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass); dc->desc = "ASPEED 2600 SDRAM Memory Controller"; - asc->max_ram_size = 2048 << 20; + asc->max_ram_size = 2 * GiB; asc->compute_conf = aspeed_2600_sdmc_compute_conf; asc->write = aspeed_2600_sdmc_write; asc->valid_ram_sizes = aspeed_2600_ram_sizes; From patchwork Mon Jul 27 15:19:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247194 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4892977ilg; Mon, 27 Jul 2020 08:23:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZBrZwpo0v2GK6HGXEMiLH1ay4I8fZmwCLIDO9zffuEofOhwtAVTN/iCC+L5ulj9WQw5O3 X-Received: by 2002:a25:248d:: with SMTP id k135mr10946141ybk.386.1595863385448; Mon, 27 Jul 2020 08:23:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863385; cv=none; d=google.com; s=arc-20160816; b=PKtZx50M2GslmfzLIakAJEt4Ob+l8o7wyJ86DIVEtJL1DFmDIoXQveD6kfYMLFVZzw sUjtHTcp82BDs6VGO68BEUF7ZbqONakVOP7TBdvBP6lIWurf69TYbn2aWGKNgMMh1SYZ 5lJ545qe8kmuIkhh3GnRlby0lYzJ4FMn2xpjBGRAXyv33cXwIHcIw7uiDuuMonSq0ac4 KYmP0AlASUz+OqwiXX95W4qSqI4ZR2RWxnM3bAtIUK49qKbEQJePyItbE6RPi2v8qGBU dL4O5Vwu7M3O/TKE0qnOnIA3Zzm3aXgUAo+4DRiMpNA68MhSQ3Ygu9uC/t1UJpC4qvlA qRXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=R9nya5qllTCM3YMYSzF0QauvCLw6C0mO2StmL8/Bb3Y=; b=syfE988CxGKUpz8IbJ9o2TF9FEm2Kf7cg4JUjkP49hOVAHAK/IzcWtPJLxxhNyv3F5 GtTsuEcIWvuGAh7bu73Si4tPLhWyvKNLGtb4l3XxIA6BVaGj4ooZh5sQ0FUFowA1JVh+ 804ZiTpyQeTgTg+fpxclO7fyosPrRYj3Tsaz7uMO0IhR4jdXJkPsq9NgWwjOfGOh8a6f u1Li3mkliXftLq4vfTByVLzgzDY+I6H2xwnpfqGoyV5pvdI0w08zEWQqrVytqFAL+/ST dhEt4vxvwDRFDq355qxgyLgUAFZKuJ/5c6jhLUx+j+ZomBfudJnBLPS3OfLPvSDqXA6n WSLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D4Jcadsb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/7] target/arm: Always pass cacheattr in S1_ptw_translate Date: Mon, 27 Jul 2020 16:19:16 +0100 Message-Id: <20200727151920.19150-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When we changed the interface of get_phys_addr_lpae to require the cacheattr parameter, this spot was missed. The compiler is unable to detect the use of NULL vs the nonnull attribute here. Fixes: 7e98e21c098 Reported-by: Jan Kiszka Signed-off-by: Richard Henderson Tested-by: Jan Kiszka Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index c69a2baf1d3..8ef0fb478f4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10204,21 +10204,11 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, int s2prot; int ret; ARMCacheAttrs cacheattrs = {}; - ARMCacheAttrs *pcacheattrs = NULL; - - if (env->cp15.hcr_el2 & HCR_PTW) { - /* - * PTW means we must fault if this S1 walk touches S2 Device - * memory; otherwise we don't care about the attributes and can - * save the S2 translation the effort of computing them. - */ - pcacheattrs = &cacheattrs; - } ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2, false, &s2pa, &txattrs, &s2prot, &s2size, fi, - pcacheattrs); + &cacheattrs); if (ret) { assert(fi->type != ARMFault_None); fi->s2addr = addr; @@ -10226,8 +10216,11 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, fi->s1ptw = true; return ~0; } - if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { - /* Access was to Device memory: generate Permission fault */ + if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) { + /* + * PTW set and S1 walk touched S2 Device memory: + * generate Permission fault. + */ fi->type = ARMFault_Permission; fi->s2addr = addr; fi->stage2 = true; From patchwork Mon Jul 27 15:19:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247190 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4890821ilg; Mon, 27 Jul 2020 08:20:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeCPLC/19Il6wNg4Bbsy6jZXXyn1aC5qCxk4fiK60/ITVXt2VMj3YTNyFWjYQ0Tab0O1bB X-Received: by 2002:a25:e90a:: with SMTP id n10mr37695982ybd.71.1595863218436; Mon, 27 Jul 2020 08:20:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863218; cv=none; d=google.com; s=arc-20160816; b=GlHyVUABtK9wVRbIvmuLk+Vkk2nOWI8O+aNKdlq1/qFp9AGQhmkMkxjtME3+DlSjXe ZaHNwbpXovXTGy2ZkaIejMnh0Y5gSbtO60dppGNXcAdg4JnFy19Ce7c1dti9/oX/v7/d LvGQSo6fBBVLFf1/tkePPrsylYnYrf/VOSa5LdbBtjCmPk0taoM/GvHnlZb8MAFENuLe HO6kj4juQ55sz+ZD8+f61+TAjy5zmTCJTst4/1L3tEZVi4y8fIr71r6/cCbAcwmBMS8H lU7mpOHA99TYxqLDrGd4b1LzqpGVUmgwzoGPWxhv/h8CTChpM6m3oal7rujqD1veHW4x mE+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PZFpVZfQpAAFemnJfw1bta1je15PzH0gg3ZsQFBq8iI=; b=d+n5jFfbhvYU3WMKyDAKRLdo29gYK3kjdpftism2DeXP9AH8875+o9bC8yrw5PtYvP uM0HSgM2zHn7M6mVUumKclZt6op5a5zyhOb7U+iASXMlPvpp4onc7xzcLZSoiaQmqkoJ yumHRYiOGUuV+f+fiC+EWWWftFRy+qUFmNpKCWJJRbcf7iRHRJ0IrCzWBEuVukNTUGdq qxLhgRc58TYpIKN9ptnCtmqZaq6OOvbTXT+rS9JSYheo1CjiY/rkw4S0LLXg4EKVeWPB mwj5LcDIjPDhIa5ebXHLfdZiCPRVHl4/CyYa1cm31PeqQvB1G5+X81jqZnjvu5cXn0ex y5IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VIf8x036; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/7] docs/system/arm/virt: Document 'mte' machine option Date: Mon, 27 Jul 2020 16:19:17 +0100 Message-Id: <20200727151920.19150-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Commit 6a0b7505f1fd6769c which added documentation of the virt board crossed in the post with commit 6f4e1405b91da0d0 which added a new 'mte' machine option. Update the docs to include the new option. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- docs/system/arm/virt.rst | 4 ++++ 1 file changed, 4 insertions(+) -- 2.20.1 diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 6621ab7205d..32dc5eb22ee 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -79,6 +79,10 @@ virtualization Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the Arm Virtualization Extensions. The default is ``off``. +mte + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Memory Tagging Extensions. The default is ``off``. + highmem Set ``on``/``off`` to enable/disable placing devices and RAM in physical address space above 32 bits. The default is ``on`` for machine types From patchwork Mon Jul 27 15:19:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247193 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4892143ilg; Mon, 27 Jul 2020 08:21:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx3FpfOhtgtqyc8kXjn2VF/B0KqChR36blewk1cagUSWrK8EB4ozCzi4EC5ahLytvU4jDo0 X-Received: by 2002:a25:248d:: with SMTP id k135mr10938418ybk.386.1595863317752; Mon, 27 Jul 2020 08:21:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863317; cv=none; d=google.com; s=arc-20160816; b=0m8873oyTwCx4r9V+jxbpUZrEyQGV6o47Nj/o/5x36LnqMV5ehJsp+XalBkceK1D4y GbF/rpXNWCZA/YqnYOqpjAXEHFZspIzfLIHWuRRDzm6WLG3UkQITMsRt1cmnfi6n8q16 I0Ss6EKX8zH2gS89kAiQCcYMPZ6wcOEHvH+6jjUJuGMc0y5HwvjdMgFTjaRWWVlRq3wW y28LcfytCS5sA3Pkzt+GyD6sYo7Sll6xXSSsBzatOXJSmaDm1rjhAZI5yS7wwBjaVO7M rypyLaVzOW1HMe9pP6zPl7jfkIAzLLHAdJmZXnJ15wV5xHbc87rq0z63q6wM2rIN3Wht NwvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CzXyfsRq8ddGHiV45tDKp7Cox+Mr2SFib9wJfNHDSi4=; b=EzLEwXSTagRI7LUsVSc35Zqufwmm7AixkyIIKbeLPSCfpUPL+RNomAJC0GdGM01eqv 2tY2uToN+2YuvjpEycFMW3ptCJmHfqCQzfhXKEdexdOXUUqvAN1OKwgJdc5Sr44eoKk0 tJsz615ks94ANthZaBIgUWO71AeOghBmcXZRq+qpEAlopD19SchbcGQR/KkyWAkqLZkD u+EHpVybo2OTCjeR67W4rUY/Dg2QoWsIEyQPzS/QGIHa7eYYii885o89CFikyeX4Gl+u D9tTCE3BnJCaw4tazEVSY21Wbn1LTHAEn31emj+1d3HFpa5fe+hGoNK3mHL9lZ2rZ6BN 9eBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=etTSnAIc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/7] hw/arm/boot: Fix PAUTH for EL3 direct kernel boot Date: Mon, 27 Jul 2020 16:19:18 +0100 Message-Id: <20200727151920.19150-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When booting an EL3 cpu with -kernel, we set up EL3 and then drop down to EL2. We need to enable access to v8.3-PAuth keys and instructions at EL3 before doing so. Signed-off-by: Richard Henderson Message-id: 20200724163853.504655-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.20.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index fef4072db16..c44fd3382dd 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -736,6 +736,9 @@ static void do_cpu_reset(void *opaque) } else { env->pstate = PSTATE_MODE_EL1h; } + if (cpu_isar_feature(aa64_pauth, cpu)) { + env->cp15.scr_el3 |= SCR_API | SCR_APK; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: From patchwork Mon Jul 27 15:19:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247195 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4893458ilg; Mon, 27 Jul 2020 08:23:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzgpnWfYXl7Qj+Da6KoazF68ilgrdTuhwYFUreqtnRcQ9RSUwollixMc1GwQytOxu8HB8T X-Received: by 2002:a25:7602:: with SMTP id r2mr32128481ybc.424.1595863418708; Mon, 27 Jul 2020 08:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863418; cv=none; d=google.com; s=arc-20160816; b=LCPn1tGNcha/HwMb/5KCfL1TWHr2NglPwng+R9hQg22O4VSDV41TneeXnofnV636sd 6z4iIjx/8igRPtE7OfQTZQoSREFZfrN/wcOjiBTQ6ipJPG+lgAGsoJlTvNAcLTJd7++6 I1eUyNJ+mgJ5h7uCWbL/olZA5i9EW3+PBVEHzgrdt92crDaLnBSng8Tl89k9u9alvcRr o6pUDGD4SScgmlyt33KxV60RHG+V/aE1ZIXV5sA/uPOEUr5LiDCD5r/rAtVRspYhpi4n ZihYRUeqeD/oZqaJnuM4ERxwqwBeACoDu8oypjk+N1KTrbAFbY9c3ehtdK+k+mMA45Up GCIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=AgiFp36fAcCMfqysVIITkhhp2lHAb79FkVULIdw4Y1E=; b=cFXVfTMkuQDrNS5IsCjoXOit3mTYNKPqdIiuYy98buIQ/vzKACN+UoUr3wPzWsXteh 1J9t16H4WB81aNfm0rd36wSTVcTqbP8vw1YWV2l5S2H5PoAN9V9GFNsctDfJo8FoosMd 3rM5FH5XZPyfYC0LGOaEu1e/vhFrmPvf7iLldIhvom7sgMpBAUCU0CWMSYsYyfSNiRjD aKuJaU5qex4v9RjGEyVDa04VLO/rxUEQ5sgY46nkaB34cTxfZBbMcTIzdYOMnwZ1vobb fU8b15tKTfKjK9Oks8EgtVI1De1kHAvUlUExtFVn6hv0AtZA2i3Bt1k15l4HiUBPclnl zSAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DBOmFpim; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/7] hw/arm/boot: Fix MTE for EL3 direct kernel boot Date: Mon, 27 Jul 2020 16:19:19 +0100 Message-Id: <20200727151920.19150-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When booting an EL3 cpu with -kernel, we set up EL3 and then drop down to EL2. We need to enable access to v8.5-MemTag tag allocation at EL3 before doing so. Reported-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200724163853.504655-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.20.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index c44fd3382dd..3e9816af803 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -739,6 +739,9 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_pauth, cpu)) { env->cp15.scr_el3 |= SCR_API | SCR_APK; } + if (cpu_isar_feature(aa64_mte, cpu)) { + env->cp15.scr_el3 |= SCR_ATA; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: From patchwork Mon Jul 27 15:19:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247192 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp4892129ilg; Mon, 27 Jul 2020 08:21:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxefuqyRKDbkMlMqwctBYcX/1I2srfE8t1Rslz+JhJIYLJeFNRxoT8NMWdzhHDAY6z/LnnC X-Received: by 2002:a25:31d4:: with SMTP id x203mr35929314ybx.396.1595863317014; Mon, 27 Jul 2020 08:21:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595863317; cv=none; d=google.com; s=arc-20160816; b=Ych+nys1VYZ2YMdY/nOAK46eVYDKb7VVbKOvz1Vq5Fvkvq8+lRswQS89oWTjA0s9Cu RuncP0NxU/eoJtldoVbuFlwYWA2PrArFvnioN3qXy0EeBk/MNGFSl8v5K4senLPTrWad Mnrdh2ZyWUmWFz3V5JBk1leYtTKyljL6yXWCHMTTx9XSI6DAiX/aB0EzDHXJIwskkmVt XynCvezNStRgw+j+2a45Up91/KUtshhlTDuRhuRTeN1NihT9db//Xvyr2s4S/IALeXI6 dah+MKVo9WPS41PIlgGSIr9ZLgOqsoXZ/yG4vvVuzW5pHS8FxfATzleP6Vyo6Hny3M9C z9gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Df26pyr1FoUci06b9bgZLyVGVD2YeeZNhUfL4mWRueY=; b=pezwIrpvF8WW/UAAjyGr6NnKuxxI55/L3J+2sFeeCUy+S3PnvCNGWz58eJHpePFfyf o4crLP+KpDZlOCUWpKITSJWkiq/NWevIAW8a5xXzBacYisphvsSa88nLv3ql8KA29evI kSGMgsmSxnjHhUuKJgPqK5soPeVbqgMK45vBhObJTa7rQ/exL4t9hl1CwHUxKGo+Tiom UFMKCt7+URA/ssWnbQId9aKlXckAFAdkopp3Kzs5vItzuc85r2cQfkl/lduWKkVnLDBP 5QUl1WLRNoX7Yo+/9mr5ReQvklfE9D1u9Js+azla7XzBta7jewPgRaBiskqYQSo0+Gvt LMdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uL8MCJQl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h199sm18744996wme.42.2020.07.27.08.19.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2020 08:19:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/arm: Improve IMPDEF algorithm for IRG Date: Mon, 27 Jul 2020 16:19:20 +0100 Message-Id: <20200727151920.19150-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org> References: <20200727151920.19150-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF, and the kernel is not expected to have set RGSR_EL1. Force a non-zero value into SEED, so that we do not continually return the same tag. Reported-by: Vincenzo Frascino Signed-off-by: Richard Henderson Message-id: 20200724163853.504655-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 5ea57d487a4..104752041f7 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -24,6 +24,8 @@ #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "qapi/error.h" +#include "qemu/guest-random.h" static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) @@ -211,16 +213,37 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) { - int rtag; - - /* - * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if - * GCR_EL1.RRND==0, always producing deterministic results. - */ uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16); + int rrnd = extract32(env->cp15.gcr_el1, 16, 1); int start = extract32(env->cp15.rgsr_el1, 0, 4); int seed = extract32(env->cp15.rgsr_el1, 8, 16); - int offset, i; + int offset, i, rtag; + + /* + * Our IMPDEF choice for GCR_EL1.RRND==1 is to continue to use the + * deterministic algorithm. Except that with RRND==1 the kernel is + * not required to have set RGSR_EL1.SEED != 0, which is required for + * the deterministic algorithm to function. So we force a non-zero + * SEED for that case. + */ + if (unlikely(seed == 0) && rrnd) { + do { + Error *err = NULL; + uint16_t two; + + if (qemu_guest_getrandom(&two, sizeof(two), &err) < 0) { + /* + * Failed, for unknown reasons in the crypto subsystem. + * Best we can do is log the reason and use a constant seed. + */ + qemu_log_mask(LOG_UNIMP, "IRG: Crypto failure: %s\n", + error_get_pretty(err)); + error_free(err); + two = 1; + } + seed = two; + } while (seed == 0); + } /* RandomTag */ for (i = offset = 0; i < 4; ++i) {