From patchwork Mon Aug 3 11:18:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247363 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1120458ilo; Mon, 3 Aug 2020 04:19:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMag43K+45dvnpnsDzN7poi4F0Xwm8ZJ+uJXqnMG+NyKJvLUB2WLlVeSC9UPz2JfTbRdX2 X-Received: by 2002:a05:6902:4a8:: with SMTP id r8mr23095952ybs.424.1596453549753; Mon, 03 Aug 2020 04:19:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453549; cv=none; d=google.com; s=arc-20160816; b=CS1FQMdRHSzVsj1t+EcUEE6f6DB3Yx2FHgsRi1H3QP44pI25wrylNAJUCwHqQxmxlV YoRPqW3DZZ0qQ6UlZPSqtHvdbHdOSKN9WZmwEn8C8EHXo7kCI/SyBD7m3ej83SLViZf1 wuo141gSdgAYlqdgwDQq6f6zjc5lva2SXLf44AT8qY9F9QjMpZ649skLZza9oI09cn6v NP+LsIP5oMeV9sm8GsFnCBhgT6kIsBN/C8GTe+rQiwIPWM2NdaDsSzsKbXpr9e1J2NO/ ujqSR+2U0te0DQsFpT+6DaVCXdogY7TZC61mXto8I9e/AXltm3LE2Er3NUAFkTU35UNQ i7rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/neSeNxwoki6I3Nz+WJ6z9QBWGfcGKIdgejdhynD3JY=; b=UrwjvmyDWTqkLN65g9lU9Bb7c80g4XmeqRucRpuIN6EnMdZJsvh3OCl40n8/x3q7Lq sxJUgeBo24qaXyA9cjiimYh62n35gtKq3asOQmpdRgpBqtT61huLewpXl9ZFcYmmWebx nqtN+SBT4YugLs8ZA/ra6RSGIFl3jgmfFLOdk1U7PZLDUds+05hNouyvAnE7uDPx57Lf hNQyQY4mkdeHKaNqwbK5qGK+JYPKy2aBlspQp+Re9km2O/9CmEr5PVkE5+28/2bvuH5D 6KpH+5S5Ga0RjNuu1PUxivxK5QjrjfdVccF1PCtALzopLF25C3/cerGmCv+ftLlFKZeh Qreg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nnNtqdEv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f14si1939201ybj.343.2020.08.03.04.19.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Aug 2020 04:19:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nnNtqdEv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k2YUn-0003hv-4w for patch@linaro.org; Mon, 03 Aug 2020 07:19:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k2YUa-0003h1-Vf for qemu-devel@nongnu.org; Mon, 03 Aug 2020 07:18:56 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:50799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k2YUZ-0004s2-4p for qemu-devel@nongnu.org; Mon, 03 Aug 2020 07:18:56 -0400 Received: by mail-wm1-x344.google.com with SMTP id c80so13985255wme.0 for ; Mon, 03 Aug 2020 04:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/neSeNxwoki6I3Nz+WJ6z9QBWGfcGKIdgejdhynD3JY=; b=nnNtqdEvagU3M94UKB7O0AlcjUn6f382ygY/Gg4IVF4k6TqQkCLqVGp3ssTzrGgbtp l4OMMKRYEj1wxbrDL8Yl18i1HBlbBKavpGmvVloUpGsHJB08eoBlSQctu6zRdKwgZ0hU 8c4kEdDhRS3hnwMj43r8+OQU5l8+gclQExE2mfJ5JxapnuKUwQWZ53rsoX1+zLSJr/X3 jCN5QxtgbKgTojBQlJ8MQGXS3c7hFXJ4vuqWfjIIZ6y0dJkoO1ECI8kKJQudCNBSV2Er Zr0yNoJJV6S/36QWpEKHJ/fqnZ8dekQ7lAY0wtzPR5hIAG43NQdsYMxsMdoXDmxxT+1I f+wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/neSeNxwoki6I3Nz+WJ6z9QBWGfcGKIdgejdhynD3JY=; b=mq54AnXnk0lZDProULItsdw/yVTXUjo+sQrGGnf5nkSIIMlOCKVKTXiONCFy/xJ3FW mm3jQLs9oR4ojAFZVJqkBcYnbP9KeqE1AHEf0VoVP4DE/hCjNa7ri9hrqcpxN3Xbtw7c QOjntymWDTS1kgDRy+E66qbbkGb/QusW85JHXwn0XTZRn6pIDHPBGkyJhHawp7g01Pgp ckmj5s4RQmSSaVmOFXG/ALnY//FHNXOTM4379vpoCQ6nIH95Eqk/H0qiNNY9CZQQBadU kE1wIzml9s0ZUS0qYS8HBd3NfZ7FRjWLu/AMUPtJXeYmSw6qEs7nGtyL/kMoeLvR2XWf tBTQ== X-Gm-Message-State: AOAM531iOl7PVovBK2VN/KO5FeJoskUZ6Hm+oYYd7bMZLn+Ax3z/u82t +k3XHcaj5G4FBPj7ZxE8TJoRzg== X-Received: by 2002:a7b:c2aa:: with SMTP id c10mr14860688wmk.86.1596453533557; Mon, 03 Aug 2020 04:18:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:18:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/7] target/arm: Pull handling of XScale insns out of disas_coproc_insn() Date: Mon, 3 Aug 2020 12:18:43 +0100 Message-Id: <20200803111849.13368-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the moment we check for XScale/iwMMXt insns inside disas_coproc_insn(): for CPUs with ARM_FEATURE_XSCALE all copro insns with cp 0 or 1 are handled specially. This works, but is an odd place for this check, because disas_coproc_insn() is called from both the Arm and Thumb decoders but the XScale case never applies for Thumb (all the XScale CPUs were ARMv5, which has only Thumb1, not Thumb2 with the 32-bit coprocessor insn encodings). It also makes it awkward to convert the real copro access insns to decodetree. Move the identification of XScale out to its own function which is only called from disas_arm_insn(). Signed-off-by: Peter Maydell --- target/arm/translate.c | 44 ++++++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 15 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index c39a929b938..a2765fc60b2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4551,20 +4551,6 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) cpnum = (insn >> 8) & 0xf; - /* First check for coprocessor space used for XScale/iwMMXt insns */ - if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) { - if (extract32(s->c15_cpar, cpnum, 1) == 0) { - return 1; - } - if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { - return disas_iwmmxt_insn(s, insn); - } else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { - return disas_dsp_insn(s, insn); - } - return 1; - } - - /* Otherwise treat as a generic register access */ is64 = (insn & (1 << 25)) == 0; if (!is64 && ((insn & (1 << 4)) == 0)) { /* cdp */ @@ -4823,6 +4809,23 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) return 1; } +/* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */ +static void disas_xscale_insn(DisasContext *s, uint32_t insn) +{ + int cpnum = (insn >> 8) & 0xf; + + if (extract32(s->c15_cpar, cpnum, 1) == 0) { + unallocated_encoding(s); + } else if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { + if (disas_iwmmxt_insn(s, insn)) { + unallocated_encoding(s); + } + } else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { + if (disas_dsp_insn(s, insn)) { + unallocated_encoding(s); + } + } +} /* Store a 64-bit value to a register pair. Clobbers val. */ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) @@ -8270,15 +8273,26 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0xc: case 0xd: case 0xe: - if (((insn >> 8) & 0xe) == 10) { + { + /* First check for coprocessor space used for XScale/iwMMXt insns */ + int cpnum = (insn >> 8) & 0xf; + + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) { + disas_xscale_insn(s, insn); + break; + } + + if ((cpnum & 0xe) == 10) { /* VFP, but failed disas_vfp. */ goto illegal_op; } + if (disas_coproc_insn(s, insn)) { /* Coprocessor. */ goto illegal_op; } break; + } default: illegal_op: unallocated_encoding(s); From patchwork Mon Aug 3 11:18:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247368 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1123191ilo; Mon, 3 Aug 2020 04:23:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSWbPAHZdZhbdY65gddKQW6FFFXwlNva6SB3R0mXXF5fJPe91cy7q1QaQAA8VlbVyWvUJZ X-Received: by 2002:a25:b741:: with SMTP id e1mr25030231ybm.178.1596453815695; Mon, 03 Aug 2020 04:23:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453815; cv=none; d=google.com; s=arc-20160816; b=yHuF/WZtEeQ4eHGRhgVW9whVcOmFXQynAGSjjEQzBg3JmIWv4Bge1o67PmZyGRMbF1 mXrYOTPMMlUG7eaE4WMx7jteKkZUEYi+Ok2af6FG+f8CiH/3B2bb5T/3zTr7q5bZU/nk W9SSborBUZeF20d2fF5NR2/BfrkntzmT06RuvgQof/jfri0Zs+Ptxs5eznV7x86MepKf qOsq2vtP0JXkGqyd6i4t3H/WeO7+K0bZaAzsKnkbBhjBzPhN7xiHEms5vgeC8ux9WKFQ X5tHsHkaCH7vEzOIt8t8O1urTaZ7k+JrauBS362VwPMF/5c57rFp0Q+2pjUZJsjjdF7d xyDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GdK1Bc8JNmdYj342FXS0zCz0nM9XuyCr0eFVY1VBs2Q=; b=W6A1v9LwmQ8x7H4GuiAr7g0O6wnj+CksoHty2kpYxFjUFd83ZtlZ7/wa3nQg6gIXe5 Ecqk3ncopHfknedy/rcAAftA0nm4jSO/v0NRPIoTm1R4TXLrYSPplUTeWbku7g6wdNm+ q67523vD0wbTxNsC/GUgM1MosRpYlYhD5NngIrmHOPHMctCJRtXK3IMBA5Qt55beCduG HNTOW5VmycJovNNZIBGNQQfnvDgwv+m067dHEAlqRBQhk49yxImwTpqV1gv0cDbYcBvz sPxeN+cA/2v4ENcB39BrERY6OoNY/WlfRRXrGio/1fqZZmRJnBP7xMua9pDlalD+1gsX SlCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xLByYNFX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:18:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/7] target/arm: Separate decode from handling of coproc insns Date: Mon, 3 Aug 2020 12:18:44 +0100 Message-Id: <20200803111849.13368-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As a prelude to making coproc insns use decodetree, split out the part of disas_coproc_insn() which does instruction decoding from the part which does the actual work, and make do_coproc_insn() handle the UNDEF-on-bad-permissions and similar cases itself rather than returning 1 to eventually percolate up to a callsite that calls unallocated_encoding() for it. Signed-off-by: Peter Maydell --- target/arm/translate.c | 76 ++++++++++++++++++++++++------------------ 1 file changed, 44 insertions(+), 32 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index a2765fc60b2..cfdcf5281d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4544,34 +4544,12 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); } -static int disas_coproc_insn(DisasContext *s, uint32_t insn) +static void do_coproc_insn(DisasContext *s, int cpnum, int is64, + int opc1, int crn, int crm, int opc2, + bool isread, int rt, int rt2) { - int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; const ARMCPRegInfo *ri; - cpnum = (insn >> 8) & 0xf; - - is64 = (insn & (1 << 25)) == 0; - if (!is64 && ((insn & (1 << 4)) == 0)) { - /* cdp */ - return 1; - } - - crm = insn & 0xf; - if (is64) { - crn = 0; - opc1 = (insn >> 4) & 0xf; - opc2 = 0; - rt2 = (insn >> 16) & 0xf; - } else { - crn = (insn >> 16) & 0xf; - opc1 = (insn >> 21) & 7; - opc2 = (insn >> 5) & 7; - rt2 = 0; - } - isread = (insn >> 20) & 1; - rt = (insn >> 12) & 0xf; - ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { @@ -4579,7 +4557,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { - return 1; + unallocated_encoding(s); + return; } if (s->hstr_active || ri->accessfn || @@ -4653,14 +4632,15 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) /* Handle special cases first */ switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { case ARM_CP_NOP: - return 0; + return; case ARM_CP_WFI: if (isread) { - return 1; + unallocated_encoding(s); + return; } gen_set_pc_im(s, s->base.pc_next); s->base.is_jmp = DISAS_WFI; - return 0; + return; default: break; } @@ -4720,7 +4700,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) /* Write */ if (ri->type & ARM_CP_CONST) { /* If not forbidden by access permissions, treat as WI */ - return 0; + return; } if (is64) { @@ -4786,7 +4766,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) gen_lookup_tb(s); } - return 0; + return; } /* Unknown register; this might be a guest error or a QEMU @@ -4806,7 +4786,39 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) s->ns ? "non-secure" : "secure"); } - return 1; + unallocated_encoding(s); + return; +} + +static int disas_coproc_insn(DisasContext *s, uint32_t insn) +{ + int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; + + cpnum = (insn >> 8) & 0xf; + + is64 = (insn & (1 << 25)) == 0; + if (!is64 && ((insn & (1 << 4)) == 0)) { + /* cdp */ + return 1; + } + + crm = insn & 0xf; + if (is64) { + crn = 0; + opc1 = (insn >> 4) & 0xf; + opc2 = 0; + rt2 = (insn >> 16) & 0xf; + } else { + crn = (insn >> 16) & 0xf; + opc1 = (insn >> 21) & 7; + opc2 = (insn >> 5) & 7; + rt2 = 0; + } + isread = (insn >> 20) & 1; + rt = (insn >> 12) & 0xf; + + do_coproc_insn(s, cpnum, is64, opc1, crn, crm, opc2, isread, rt, rt2); + return 0; } /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */ From patchwork Mon Aug 3 11:18:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247365 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1121242ilo; Mon, 3 Aug 2020 04:20:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwEhUHhqpQtFMQ4a1oL3hvbeswnygxAamVbJ+P3FAyz03j9337O9u76sU+3Y2ibvn4CLwcq X-Received: by 2002:a25:df05:: with SMTP id w5mr26195211ybg.354.1596453621978; Mon, 03 Aug 2020 04:20:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453621; cv=none; d=google.com; s=arc-20160816; b=uEAojlry1d6cMTAeGmEnqCv2fDIBDJg7KzRpUb53epiMz5sXioVJ49kUQs2f+POr3p 5UjTuCIwZXrcY6HgPxS4ljTfwUFyt9X8E8LqI0LWL9Vp/R62aUHp8yiwpwkfnxoT243t SA1Xybi2bt+iJZuQu34jgfMuLEGNrzkhwW9zh75dcqiT+zQ3JXC7+yXJde1ckosZ8qrf h6iKuYKGMn4F9p8GnyGuct6icMsOVbs/ymJ1U0y2gcidXaDEbrvxGj9m3Dd89oJCEiKe 7f5oXbrV9kfXnQsvb5Hivq8q02omqvjbKy3FtDwy+J+VNqGN8aO7sRxTE4Jtea32/EM6 xyGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WVrz2TM2NyRna3FiFYVkgyDOwt7IGSm5Yz6r2adar/U=; b=yuaD4eqOGQkNJ98WGzBStt4hRteHSAaPxJLfl5cGQuwp9ISS3QLGS7V5cbEkznLhVv tAr/baJEGaNJp7Xa9d9T8w+eeRpEaJUezsUHn3wNeNnkMYixvlqJIJAzK6+DXuayYcfY 0ssp9OTV/BnJwFnu7T1Ydl4eDMO4eeGAxc681kD6NUIpm1rd5c6VQkW0FbCqsHtVl3Co pRkWUToADBLJzfohiuxZ/WbUgmy9+8CHKdcTu5HO3zhYjcF9UhBNrJ4B8nN2P3Wk9ZcI 3DElNsHdvt/xZURN0fusqmTygRsaPlgSvA08ffy4zT22+z/0nSenbPusxa0eFuArcHqg E9Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NvSGWSoB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:18:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/7] target/arm: Convert A32 coprocessor insns to decodetree Date: Mon, 3 Aug 2020 12:18:45 +0100 Message-Id: <20200803111849.13368-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the A32 coprocessor instructions to decodetree. Note that this corrects an underdecoding: for the 64-bit access case (MRRC/MCRR) we did not check that bits [24:21] were 0b0010, so we would incorrectly treat LDC/STC as MRRC/MCRR rather than UNDEFing them. The decodetree versions of these insns assume the coprocessor is in the range 0..7 or 14..15. This is architecturally sensible (as per the comments) and OK in practice for QEMU because the only uses of the ARMCPRegInfo infrastructure we have that aren't for coprocessors 14 or 15 are the pxa2xx use of coprocessor 6. We add an assertion to the define_one_arm_cp_reg_with_opaque() function to catch any accidental future attempts to use it to define coprocessor registers for invalid coprocessors. Signed-off-by: Peter Maydell --- target/arm/a32.decode | 19 +++++++++++ target/arm/helper.c | 29 +++++++++++++++++ target/arm/translate.c | 74 +++++++++++++++++++++++++++++++++++------- 3 files changed, 111 insertions(+), 11 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 0bd952c0692..4dfd9139bf3 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -47,6 +47,8 @@ &bfi rd rn lsb msb &sat rd rn satimm imm sh &pkh rd rn rm imm tb +&mcr cp opc1 crn crm opc2 rt +&mcrr cp opc1 crm rt rt2 # Data-processing (register) @@ -529,6 +531,23 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block B .... 1010 ........................ @branch BL .... 1011 ........................ @branch +# Coprocessor instructions + +# We decode MCR, MCR, MRRC and MCRR only, because for QEMU the +# other coprocessor instructions always UNDEF. +# The trans_ functions for these will ignore cp values 8..13 for v7 or +# earlier, and 0..13 for v8 and later, because those areas of the +# encoding space may be used for other things, such as VFP or Neon. + +@mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr +@mcrr ---- .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 &mcrr + +MCRR .... 1100 0100 .... .... .... .... .... @mcrr +MRRC .... 1100 0101 .... .... .... .... .... @mcrr + +MCR .... 1110 ... 0 .... .... .... ... 1 .... @mcr +MRC .... 1110 ... 1 .... .... .... ... 1 .... @mcr + # Supervisor call SVC ---- 1111 imm:24 &i diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ef0fb478f4..b0acc90e075 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8462,6 +8462,35 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); + /* + * This API is only for Arm's system coprocessors (14 and 15) or + * (M-profile or v7A-and-earlier only) for implementation defined + * coprocessors in the range 0..7. Our decode assumes this, since + * 8..13 can be used for other insns including VFP and Neon. See + * valid_cp() in translate.c. Assert here that we haven't tried + * to use an invalid coprocessor number. + */ + switch (r->state) { + case ARM_CP_STATE_BOTH: + /* 0 has a special meaning, but otherwise the same rules as AA32. */ + if (r->cp == 0) { + break; + } + /* fall through */ + case ARM_CP_STATE_AA32: + if (arm_feature(&cpu->env, ARM_FEATURE_V8) && + !arm_feature(&cpu->env, ARM_FEATURE_M)) { + assert(r->cp >= 14 && r->cp <= 15); + } else { + assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); + } + break; + case ARM_CP_STATE_AA64: + assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); + break; + default: + g_assert_not_reached(); + } /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 * encodes a minimum access level for the register. We roll this * runtime check into our general permission check code, so check diff --git a/target/arm/translate.c b/target/arm/translate.c index cfdcf5281d3..b1be4cb9d60 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5237,6 +5237,68 @@ static int t16_pop_list(DisasContext *s, int x) #include "decode-t32.inc.c" #include "decode-t16.inc.c" +static bool valid_cp(DisasContext *s, int cp) +{ + /* + * Return true if this coprocessor field indicates something + * that's really a possible coprocessor. + * For v7 and earlier, coprocessors 8..15 were reserved for Arm use, + * and of those only cp14 and cp15 were used for registers. + * cp10 and cp11 were used for VFP and Neon, whose decode is + * dealt with elsewhere. With the advent of fp16, cp9 is also + * now part of VFP. + * For v8A and later, the encoding has been tightened so that + * only cp14 and cp15 are valid, and other values aren't considered + * to be in the coprocessor-instruction space at all. v8M still + * permits coprocessors 0..7. + */ + if (arm_dc_feature(s, ARM_FEATURE_V8) && + !arm_dc_feature(s, ARM_FEATURE_M)) { + return cp >= 14; + } + return cp < 8 || cp >= 14; +} + +static bool trans_MCR(DisasContext *s, arg_MCR *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, + false, a->rt, 0); + return true; +} + +static bool trans_MRC(DisasContext *s, arg_MRC *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, + true, a->rt, 0); + return true; +} + +static bool trans_MCRR(DisasContext *s, arg_MCRR *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, + false, a->rt, a->rt2); + return true; +} + +static bool trans_MRRC(DisasContext *s, arg_MRRC *a) +{ + if (!valid_cp(s, a->cp)) { + return false; + } + do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, + true, a->rt, a->rt2); + return true; +} + /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) { @@ -8293,17 +8355,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) disas_xscale_insn(s, insn); break; } - - if ((cpnum & 0xe) == 10) { - /* VFP, but failed disas_vfp. */ - goto illegal_op; - } - - if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ - goto illegal_op; - } - break; + /* fall through */ } default: illegal_op: From patchwork Mon Aug 3 11:18:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247364 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1120827ilo; Mon, 3 Aug 2020 04:19:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzle4KzPgUSvPmF26l8S4rb7RbjABEH+Eq5MZlE/hJQv4GIW/NS8SspTTibKREgkS3WhMR4 X-Received: by 2002:a25:d702:: with SMTP id o2mr9905290ybg.379.1596453583174; Mon, 03 Aug 2020 04:19:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453583; cv=none; d=google.com; s=arc-20160816; b=lNcUSdgXTSSV1Zw3vPNPuM1rcxiiqqlduZryrH4xSrT+aNaSfidQ2evg7+SRcYlhEU EtPAIfvE3SpEpGXCTap1yFbvtiYjbhRbhay8WZ4m8epZuqwsqD4mgRuJdoFtAAl45KrK eAXArWXhfXBSyX313CweRwAxTPPTG36p+KLNqvJONwPz87VqzUpd4ix5GJyGArsg9pM6 AW0S5KdlfylIjCbvCES4WkjMpZd6Yk8gMjNifHIya3yaZ2KmlzZsgOTw8/Ryc7cNBq3v rdorrWF1hsFec9i0p5O5I6EH17cED26wU79tfz2QC1khCl9Hjdslm0ZN3idNygZ+t1nT v6lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BExTigTa/EjWPG8Q5yXKlYgwozNoOz78Qwl9+pJrCfg=; b=V7VnPFDUwdFNZZWyzUxJHOKwKif33nBiGzep0A5J/gClqKruNzhV8NXJqakC4nzI4J Pz9XLjWO4Kj6SLND29vBc3wZra2TEv8Jd8tD9kLdwfU7DiPLBSLPN7DowCHj5lDjlb39 I9hIUmz1wAw8ZP2tKJ9YqCyXYXtOwp0EsuR9xnf2dO4Zm54g7/ma7jWpUb1V3lOpT+k4 HDeZLewvm4MdFYkaK08YFvQ8KlyRoKuIhB9az/pHXq3hJAyoknyOW9XByOpetw0dH/YB eyGipemC43PcjYhSx7FdP37K1sMJCwhVyz34iPWlysutnmxkGRWkJh6nQQKO0UfWuXAI d4Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WBoyAtyO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:18:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/7] target/arm: Tidy up disas_arm_insn() Date: Mon, 3 Aug 2020 12:18:46 +0100 Message-Id: <20200803111849.13368-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only thing left in the "legacy decoder" is the handling of disas_xscale_insn(), and we can simplify the code. Signed-off-by: Peter Maydell --- target/arm/translate.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index b1be4cb9d60..639fe121a2e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8342,26 +8342,18 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; } /* fall back to legacy decoder */ - - switch ((insn >> 24) & 0xf) { - case 0xc: - case 0xd: - case 0xe: - { - /* First check for coprocessor space used for XScale/iwMMXt insns */ - int cpnum = (insn >> 8) & 0xf; - - if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cpnum < 2)) { + /* TODO: convert xscale/iwmmxt decoder to decodetree ?? */ + if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) { + if (((insn & 0x0c000e00) == 0x0c000000) + && ((insn & 0x03000000) != 0x03000000)) { + /* Coprocessor insn, coprocessor 0 or 1 */ disas_xscale_insn(s, insn); - break; + return; } - /* fall through */ - } - default: - illegal_op: - unallocated_encoding(s); - break; } + +illegal_op: + unallocated_encoding(s); } static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) From patchwork Mon Aug 3 11:18:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247366 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1121402ilo; Mon, 3 Aug 2020 04:20:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw0EtnnenhQlyHOHoUh0q4RzsfTEPpeUfO/BJwV5GE2dkqtVu6fj7dE48z2orq8mayUw0Um X-Received: by 2002:a5b:b45:: with SMTP id b5mr24761157ybr.294.1596453638704; Mon, 03 Aug 2020 04:20:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453638; cv=none; d=google.com; s=arc-20160816; b=AKa88HQwcdQRNLXBdHcOVXMpopZ3KE/6QYJ4wbrNfq/v34jx4NZizI08plsbKkxorD xpEAGtu6nGkIXzUysCv6vzJrwFfs2B823maTVCz+DVk9ysCs7sC9byR53kaXNC4Ebl1T ANaqPUSwTSc4NXwfAVxxuzJ3tnMV0P/U8DJ/bWcLAhIksmVMI4JiOACWDt0mh02GDL38 p/OxYrE98jdSGfDs4YvlTK6UC/J8luNS7912FW4GDTSRLSc+yI8UHwUnsXy67CqRw7wy M7SRhJH8gIYuqawt23mrziD66SBEoakHVJgQmSA/el19FYnAEko4lrHjUmXRmOdijhTJ Zd6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Jk9fS55Yi0cM18IUj1sLUkIZI7PH5doTh14I0Z0+qSY=; b=yLcVFUnDgtFCmR01t1bjEeW4aN80a5985OTKSrc5+s6DPzSHg4+JFmjq+iIhGjwpTA 3eJDL8wIPPxqy+3P5QRmg4/gsZ/KqkShu38IegI8WdHio3HKVEvGyJoC9eCuqbcKCUzW b9jGq6mirwNTFzu/ZnZ89xOtg9qpVMzaj5GqHKrnJTRCPtWdqVw08azrb2LcUzg7M6IG HjwE4Q429t8bqX+IkCTbsUPF+USaqGgQvsQ/MKMwuIRCOvHIwkGTsWOg9QSyicnqxoPH UwmvgG5nequjAu8I8HMLSDhvo3fiL+f/89qm8tLBj1B+hJ5tnLCqYPlN4jDjWfqi2alN TMcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FdReBHCR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:18:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/7] target/arm: Do M-profile NOCP checks early and via decodetree Date: Mon, 3 Aug 2020 12:18:47 +0100 Message-Id: <20200803111849.13368-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For M-profile CPUs, the architecture specifies that the NOCP exception when a coprocessor is not present or disabled should cover the entire wide range of coprocessor-space encodings, and should take precedence over UNDEF exceptions. (This is the opposite of A-profile, where checking for a disabled FPU has to happen last.) Implement this with decodetree patterns that cover the specified ranges of the encoding space. There are a few instructions (VLLDM, VLSTM, and in v8.1 also VSCCLRM) which are in copro-space but must not be NOCP'd: these must be handled also in the new m-nocp.decode so they take precedence. This is a minor behaviour change: for unallocated insn patterns in the VFP area (cp=10,11) we will now NOCP rather than UNDEF when the FPU is disabled. As well as giving us the correct architectural behaviour for v8.1M and the recommended behaviour for v8.0M, this refactoring also removes the old NOCP handling from the remains of the 'legacy decoder' in disas_thumb2_insn(), paving the way for cleaning that up. Since we don't currently have a v8.1M feature bit or any v8.1M CPUs, the minor changes to this logic that we'll need for v8.1M are marked up with TODO comments. Signed-off-by: Peter Maydell --- target/arm/m-nocp.decode | 42 +++++++++++++++++++++++++++ target/arm/vfp.decode | 2 -- target/arm/translate-vfp.inc.c | 52 +++++++++++++++++++++++++++------- target/arm/translate.c | 30 ++++++++++---------- target/arm/Makefile.objs | 6 ++++ 5 files changed, 105 insertions(+), 27 deletions(-) create mode 100644 target/arm/m-nocp.decode -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode new file mode 100644 index 00000000000..7182d7d1217 --- /dev/null +++ b/target/arm/m-nocp.decode @@ -0,0 +1,42 @@ +# M-profile UserFault.NOCP exception handling +# +# Copyright (c) 2020 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# For M-profile, the architecture specifies that NOCP UsageFaults +# should take precedence over UNDEF faults over the whole wide +# range of coprocessor-space encodings, with the exception of +# VLLDM and VLSTM. (Compare v8.1M IsCPInstruction() pseudocode and +# v8M Arm ARM rule R_QLGM.) This isn't mandatory for v8.0M but we choose +# to behave the same as v8.1M. +# This decode is handled before any others (and in particular before +# decoding FP instructions which are in the coprocessor space). +# If the coprocessor is not present or disabled then we will generate +# the NOCP exception; otherwise we let the insn through to the main decode. + +{ + # Special cases which do not take an early NOCP: VLLDM and VLSTM + VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 + # TODO: VSCCLRM (new in v8.1M) is similar: + #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 + + NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- + NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- + # TODO: From v8.1M onwards we will also want this range to NOCP + #NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- cp=10 +} diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 5fd70f975ae..2c793e3e87f 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -213,5 +213,3 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ vd=%vd_sp vm=%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ vd=%vd_sp vm=%vm_dp - -VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index afa8a5f8885..463253de90b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -95,14 +95,11 @@ static inline long vfp_f16_offset(unsigned reg, bool top) static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(), - s->fp_excp_el); - } else { - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), - s->fp_excp_el); - } + /* M-profile handled this earlier, in disas_m_profile_nocp() */ + assert (!arm_dc_feature(s, ARM_FEATURE_M)); + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); return false; } @@ -2842,9 +2839,14 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) !arm_dc_feature(s, ARM_FEATURE_V8)) { return false; } - /* If not secure, UNDEF. */ + /* + * If not secure, UNDEF. We must emit code for this + * rather than returning false so that this takes + * precedence over the m-nocp.decode NOCP fallback. + */ if (!s->v8m_secure) { - return false; + unallocated_encoding(s); + return true; } /* If no fpu, NOP. */ if (!dc_isar_feature(aa32_vfp, s)) { @@ -2863,3 +2865,33 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) s->base.is_jmp = DISAS_UPDATE_EXIT; return true; } + +static bool trans_NOCP(DisasContext *s, arg_NOCP *a) +{ + /* + * Handle M-profile early check for disabled coprocessor: + * all we need to do here is emit the NOCP exception if + * the coprocessor is disabled. Otherwise we return false + * and the real VFP/etc decode will handle the insn. + */ + assert(arm_dc_feature(s, ARM_FEATURE_M)); + + if (a->cp == 11) { + a->cp = 10; + } + /* TODO: in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ + + if (a->cp != 10) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), default_exception_el(s)); + return true; + } + + if (s->fp_excp_el != 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + return false; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 639fe121a2e..adcd2127290 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1176,6 +1176,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) #define ARM_CP_RW_BIT (1 << 20) /* Include the VFP and Neon decoders */ +#include "decode-m-nocp.inc.c" #include "translate-vfp.inc.c" #include "translate-neon.inc.c" @@ -8433,6 +8434,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) ARCH(6T2); } + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * NOCP takes precedence over any UNDEF for (almost) the + * entire wide range of coprocessor-space encodings, so check + * for it first before proceeding to actually decode eg VFP + * insns. This decode also handles the few insns which are + * in copro space but do not have NOCP checks (eg VLLDM, VLSTM). + */ + if (disas_m_nocp(s, insn)) { + return; + } + } + if ((insn & 0xef000000) == 0xef000000) { /* * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq @@ -8481,21 +8495,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */ - if (extract32(insn, 24, 2) == 3) { - goto illegal_op; /* op0 = 0b11 : unallocated */ - } - - if (((insn >> 8) & 0xe) == 10 && - dc_isar_feature(aa32_fpsp_v2, s)) { - /* FP, and the CPU supports it */ - goto illegal_op; - } else { - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), - default_exception_el(s)); - } - break; + goto illegal_op; } if (((insn >> 24) & 3) == 3) { /* Neon DP, but failed disas_neon_dp() */ diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index fa39fd7c831..7abb12868ae 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,6 +43,11 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-m-nocp.inc.c: $(SRC_PATH)/target/arm/m-nocp.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_m_nocp -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) $(call quiet-command,\ $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ @@ -69,6 +74,7 @@ target/arm/translate.o: target/arm/decode-neon-dp.inc.c target/arm/translate.o: target/arm/decode-neon-ls.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-m-nocp.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c From patchwork Mon Aug 3 11:18:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247370 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1124596ilo; Mon, 3 Aug 2020 04:26:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFvjtdPwkd8/xuJm+pIFBTi79WMLqgDgmyxlsh2fE6SgtQramc0IYh5+wplrM7t5Pdi4AH X-Received: by 2002:a25:9904:: with SMTP id z4mr25290059ybn.150.1596453961446; Mon, 03 Aug 2020 04:26:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453961; cv=none; d=google.com; s=arc-20160816; b=rwApoOo+xJxqU5DxAyQajPvzVzEngQdyfIHK2D5PArVWoqtIL2iFhjvKBTllKamoD1 n7iNbxVO4JtKXZw9X6S3C0Qx6m6Et9QG+DlcmYvnSndi2nH5S3udlq30TzQKihXmn7vA ig0Q+fZz2QCBUkdDPgZUSGOmMsRdjq/TwunEY/l16+bRJe4+qnXgOcbhfmzZBGtY/Cax a6+MOXColT6Jjlf9vg0zEQ+0at7MrQIq90UbdXwHSVE6MWf66q/KkrwTEhRnOYnrRVNN qMNsVtl3j2+Qza+DBkLyIZuSvgguwC2Dlrnib+HRB7yTeH+3WYQkWOYT2RCSzkSxxyzN KTUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uE/zSzU3YCUj+8keAlvLyFX2oijQycTIyZcK1gVRSqY=; b=vxAWtC48tN1V3ALS0e17o3E45DrIZ+XpPVxsXE5Mt9Bkx63gLNEImUjvD87fhefivU pUybGJI99uTkW24IKE2V8tJloilcShT2ojYGtWNU/Taab2m4dSmDOx1C2VD01RlKqCKZ QaKyK8zD1QfSZJbkXnR/iEIVQm+G9Mq+M/xg60hHOLeVhHmVgbfnvbV5yfxtVRbKp5bN u54vcm4G0mzv3GaL+2oGN9uTzc1fQ1QNOkuHQvihP6giy20b8gEOp525WeZpTaQ30c75 YaAAK5i4lUFwh9euC18rUOWqrhLoM8FsgDBTEmZPJ8SqwcMy1xuDAH8Ucuy502zyIx9p 46SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yHOeXGR2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:19:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/7] target/arm: Convert T32 coprocessor insns to decodetree Date: Mon, 3 Aug 2020 12:18:48 +0100 Message-Id: <20200803111849.13368-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert the T32 coprocessor instructions to decodetree. As with the A32 conversion, this corrects an underdecoding where we did not check that MRRC/MCRR [24:21] were 0b0010 and so treated some kinds of LDC/STC and MRRC/MCRR rather than UNDEFing them. Signed-off-by: Peter Maydell --- target/arm/t32.decode | 19 +++++++++++++ target/arm/translate.c | 64 ++---------------------------------------- 2 files changed, 21 insertions(+), 62 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c21a988f971..7069d821fde 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -45,6 +45,8 @@ &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb &cps !extern mode imod M A I F +&mcr !extern cp opc1 crn crm opc2 rt +&mcrr !extern cp opc1 crm rt rt2 # Data-processing (register) @@ -621,6 +623,23 @@ RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1 SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2 SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1 +# Coprocessor instructions + +# We decode MCR, MCR, MRRC and MCRR only, because for QEMU the +# other coprocessor instructions always UNDEF. +# The trans_ functions for these will ignore cp values 8..13 for v7 or +# earlier, and 0..13 for v8 and later, because those areas of the +# encoding space may be used for other things, such as VFP or Neon. + +@mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 +@mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 + +MCRR 1110 1100 0100 .... .... .... .... .... @mcrr +MRRC 1110 1100 0101 .... .... .... .... .... @mcrr + +MCR 1110 1110 ... 0 .... .... .... ... 1 .... @mcr +MRC 1110 1110 ... 1 .... .... .... ... 1 .... @mcr + # Branches %imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 diff --git a/target/arm/translate.c b/target/arm/translate.c index adcd2127290..59d6e43611a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4791,37 +4791,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, return; } -static int disas_coproc_insn(DisasContext *s, uint32_t insn) -{ - int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; - - cpnum = (insn >> 8) & 0xf; - - is64 = (insn & (1 << 25)) == 0; - if (!is64 && ((insn & (1 << 4)) == 0)) { - /* cdp */ - return 1; - } - - crm = insn & 0xf; - if (is64) { - crn = 0; - opc1 = (insn >> 4) & 0xf; - opc2 = 0; - rt2 = (insn >> 16) & 0xf; - } else { - crn = (insn >> 16) & 0xf; - opc1 = (insn >> 21) & 7; - opc2 = (insn >> 5) & 7; - rt2 = 0; - } - isread = (insn >> 20) & 1; - rt = (insn >> 12) & 0xf; - - do_coproc_insn(s, cpnum, is64, opc1, crn, crm, opc2, isread, rt, rt2); - return 0; -} - /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */ static void disas_xscale_insn(DisasContext *s, uint32_t insn) { @@ -8485,38 +8454,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) ((insn >> 28) == 0xe && disas_vfp(s, insn))) { return; } - /* fall back to legacy decoder */ - switch ((insn >> 25) & 0xf) { - case 0: case 1: case 2: case 3: - /* 16-bit instructions. Should never happen. */ - abort(); - case 6: case 7: case 14: case 15: - /* Coprocessor. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */ - goto illegal_op; - } - if (((insn >> 24) & 3) == 3) { - /* Neon DP, but failed disas_neon_dp() */ - goto illegal_op; - } else if (((insn >> 8) & 0xe) == 10) { - /* VFP, but failed disas_vfp. */ - goto illegal_op; - } else { - if (insn & (1 << 28)) - goto illegal_op; - if (disas_coproc_insn(s, insn)) { - goto illegal_op; - } - } - break; - case 12: - goto illegal_op; - default: - illegal_op: - unallocated_encoding(s); - } +illegal_op: + unallocated_encoding(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) From patchwork Mon Aug 3 11:18:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 247367 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1122190ilo; Mon, 3 Aug 2020 04:22:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2bwxu1mxS6y4C8sS3QT0W2m7CQMTtWJai/w2i8AWDfasFt0mw1qiWvL5KnyOAv/qKoYiG X-Received: by 2002:a25:410f:: with SMTP id o15mr22884229yba.328.1596453722041; Mon, 03 Aug 2020 04:22:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596453722; cv=none; d=google.com; s=arc-20160816; b=C2wO59C9/v8GxfNHOLLXePzSBl0aM4+UrjcppxBzQ/XZGtx+JngjzSJlH5StmDxF7e YHm1bqFcgZcas56P3nKpYtOjGMft2EudpmDvH6LwwL00SG4nfu9odAJ8iRS0eqGYo674 sTqsmdy/2N+4KKSMuiHbkvlXiBE8Ji6483wFdyIqjRksQ3r0pQ6lgpwh7LqrteazxPi6 T97P4ftJMerrR9I4rsX/dmWCUX7fmVtGMmiNzomBIiOFfE0crS0//nj2Uuyl5zkCATBq aS/VDdaONYjid2FFPAdrX/al/clx+p5KgMyDBpSe26iPBBu/GuQGoRfUGtaVgn99jdwb mU3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rAgcA7IrGXsmYiY0CiUqcWe2vzUpbrPD30xAx0l2H2U=; b=cqVuCo98NXsD8qPbRsogw1rSXH+7rAHaYBwWFv7X5X0XbIk7txfU6s29UDfqvloMp4 /7xEQ5GdNiTQ7QgWcDAQgT8A5CgFcw8QyuyvWL0EbHgJpd594euQDxf2FXCORcc1eDYH fI91Sn9uDn2dT+53ZNo9t4EirRcbRXPyoBMen8THKncQ93oWgyiylxpkkJHcjDJwERtP 8bFcJ0gUMBS/r3nSLpbq65S1+J5mJcvfUGqAsQ5N94zlQB64GPHQ/yFt3JW23gDCam8w VcOtRNKlBLeowliTxTPgV7PG6GzUX8Z8dSV0yHCg9KpUvGXywXUsrENps4EDlXkbgnCR 3o2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JSIulD2q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:19:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 7/7] target/arm: Remove ARCH macro Date: Mon, 3 Aug 2020 12:18:49 +0100 Message-Id: <20200803111849.13368-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200803111849.13368-1-peter.maydell@linaro.org> References: <20200803111849.13368-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ARCH() macro was used a lot in the legacy decoder, but there are now just two uses of it left. Since a macro which expands out to a goto is liable to be confusing when reading code, replace the last two uses with a simple open-coded qeuivalent. Signed-off-by: Peter Maydell --- target/arm/translate.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index 59d6e43611a..37d4985d7e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -49,8 +49,6 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) -#define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) - #include "translate.h" #if defined(CONFIG_USER_ONLY) @@ -7909,7 +7907,7 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { TCGv_i32 tmp; - /* For A32, ARCH(5) is checked near the start of the uncond block. */ + /* For A32, ARM_FEATURE_V5 is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } @@ -8275,7 +8273,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. */ - ARCH(5); + if (!arm_dc_feature(s, ARM_FEATURE_V5)) { + unallocated_encoding(s); + return; + } /* Unconditional instructions. */ /* TODO: Perhaps merge these into one decodetree output file. */ @@ -8400,7 +8401,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } } else if ((insn & 0xf800e800) != 0xf000e800) { - ARCH(6T2); + if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { + unallocated_encoding(s); + return; + } } if (arm_dc_feature(s, ARM_FEATURE_M)) {