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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:38 -0700 Message-Id: <20171010005600.28735-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL 01/23] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Note that this change also requires updating the accessors to tlb_flush_count to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) -- 2.13.6 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f848d..e43ff8346b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f941783c5..c91db211bc 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bcbcc4db6c..5b1ef1442c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_func fn, } } -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count = 0; + + CPU_FOREACH(cpu) { + CPUArchState *env = cpu->env_ptr; + + count += atomic_read(&env->tlb_flush_count); + } + return count; +} /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); tb_lock(); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2d1ed06065..6b5d4bece2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1936,7 +1936,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); tb_unlock(); From patchwork Tue Oct 10 00:55:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115313 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3168619qgn; Mon, 9 Oct 2017 18:01:05 -0700 (PDT) X-Received: by 10.200.38.3 with SMTP id u3mr17493681qtu.257.1507597265206; Mon, 09 Oct 2017 18:01:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597265; cv=none; d=google.com; s=arc-20160816; b=WhvLMkuLzS6OYfMUkkXZ22QQEzIWS49lb5svAsKFpM2KoaN0LoSaVhKF6K9TSlyDz6 iLdfvVxviogaWaKKaCAQ2wX+mex/zucKuu+8L2mUKlz74bbMEWn2kfhfP+MnIc8Lk/03 So9lmP1dHfRu49EyyykiTbucQ+UNnReC5sDCrddaENoJ+94UVQYPeJZ3A2M4040LR7Pm kPGIPkE0E3fI4A/YyjYs2aSTCNBzgJiJuUNn/nszS7Xi1BonFlA97JV+73ITwa5srqzq KoBiC7FCJk+jxbrBO1+Xkd2z/3OixdBaS91KWXQKKnGfzjQNWhaxw242Ww992h5JoDVZ 5DDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uWX8ltUJ41jzpP0mhxc6dOVFBO5YtrjkEa7vnTfdaYc=; b=KEdDFsu0dgIBq7A4xciD9aK2bU0/9nupg/7xALq4LtMYOvNkJ5kT+JCFYMAjNji5LQ 4tgcLGoqOkl63I5MIngnoWL7S3+LGhjBk9ESrTWDsdG1wuUV3y/6nnE9i5CZEMVNr6J5 r+9MS1uA4ZCkCNaGK6Y4/1xsvY0Ivl+WMfkQ3tKSckqUgaWdJllYRCpdAOAi3dOKpTkq yIJaGybe+ulWJgBuVwwDP0i0mr0urgy4LamWResMTomRW8dlVLH5e5jRs4SNsUqDEizu uWcYKcR+SC82qyqVgb61VmtlnnbNa6MnSLuZcIyEoYNOdMCSvay4vWxSqRxSJ9FLgGLx 4HGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kp1BUMNE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:39 -0700 Message-Id: <20171010005600.28735-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 02/23] tcg: fix corruption of code_time profiling counter upon tb_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Whenever there is an overflow in code_gen_buffer (e.g. we run out of space in it and have to flush it), the code_time profiling counter ends up with an invalid value (that is, code_time -= profile_getclock(), without later on getting += profile_getclock() due to the goto). Fix it by using the ti variable, so that we only update code_time when there is no overflow. Note that in case there is an overflow we fail to account for the elapsed coding time, but this is quite rare so we can probably live with it. "info jit" before/after, roughly at the same time during debian-arm bootup: - before: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 998 JIT cycles -615191529184601 (-256329.804 s at 2.4 GHz) translated TBs 302310 (aborted=0 0.0%) avg ops/TB 48.4 max=438 deleted ops/TB 8.54 avg temps/TB 32.31 max=38 avg host code/TB 361.5 avg search data/TB 24.5 cycles/op -42014693.0 cycles/in byte -121444900.2 cycles/out byte -5629031.1 cycles/search byte -83114481.0 gen_interm time -0.0% gen_code time 100.0% optim./code time -0.0% liveness/code time -0.0% cpu_restore count 6236 avg cycles 110.4 - after: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 1010 JIT cycles 1996899624 (0.832 s at 2.4 GHz) translated TBs 297961 (aborted=0 0.0%) avg ops/TB 48.5 max=438 deleted ops/TB 8.56 avg temps/TB 32.31 max=38 avg host code/TB 361.8 avg search data/TB 24.5 cycles/op 138.2 cycles/in byte 398.4 cycles/out byte 18.5 cycles/search byte 273.1 gen_interm time 14.0% gen_code time 86.0% optim./code time 19.4% liveness/code time 10.3% cpu_restore count 6372 avg cycles 111.0 Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.13.6 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b5d4bece2..b3bfe65059 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1300,7 +1300,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; tcg_ctx.interm_time += profile_getclock() - ti; - tcg_ctx.code_time -= profile_getclock(); + ti = profile_getclock(); #endif /* ??? Overflow could be handled better here. In particular, we @@ -1318,7 +1318,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } #ifdef CONFIG_PROFILER - tcg_ctx.code_time += profile_getclock(); + tcg_ctx.code_time += profile_getclock() - ti; tcg_ctx.code_in_len += tb->size; tcg_ctx.code_out_len += gen_code_size; tcg_ctx.search_out_len += search_size; From patchwork Tue Oct 10 00:55:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115309 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3165419qgn; Mon, 9 Oct 2017 17:56:34 -0700 (PDT) X-Received: by 10.55.38.193 with SMTP id m62mr12292208qkm.21.1507596994017; Mon, 09 Oct 2017 17:56:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507596994; cv=none; d=google.com; s=arc-20160816; b=TXcoxwyPykcdXCFanFVwRYh2jxFntW9qQKud3a7APMV+7z1r4EQ5TRczhviD/bMvNE yfPkBUzS95lzZeK46TNQw9i8F4hYIwkJmxP2BULsZ9cu/W8N3gNykZoCIL0OedaySeTK yeGBeqxi/ZQNawJodHYZmdaY+gPaAoYssmQt1gJ8ZUCo2hnUz0vRY99sr9qemHAV9tnd pTHfHe39usTt4wPKRbj8rOJi4BS8yY1JlLoSstLoULxWXmqtijUG/MSUvMXFSzNRm2tZ f6rDDB4fHDy1EuOmuKDeCKlWC0L5A+HqZrNWBrOjrxhjhacV3ox41jwk6tPaHyvZHhcw gfoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7R+gio33UwF3vi2Cvaa4aXxIYtef4+3eg4MJuM1tI6k=; b=VEDhoexdq+Pghsp24spLYZzlKBt/upMnqkaLqMky3R5HSyXR3bYBCd+7NZ8rlmy8wN enWIw7QNmPZuUoRXWL2ulmLP9wppZkdx5PaXIt3JaiDvHlzW1bpJ52SK1DUNGcvH6rgt HxMQqzMXxCi+XADkyFDZOu5VCCk8OP0kExNKFA/vilZROHBnjuuaA9p4+M3GTuwTj/Vo VoN3ku9IVGar7e3cvvyqnIWo5LKFc/mIx2kdoierTXUeYSrX+cIn78y03eAhrCrokXXL Kk81gFOucKaWGITAxSsOUjLB4EQ/8VvWuEyUksJq8V86ZCEIUwUxP9oaRFR5dElxm6vv xS1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WQrawERe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:40 -0700 Message-Id: <20171010005600.28735-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 03/23] exec-all: fix typos in TranslationBlock's documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.13.6 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 673fc066d0..a9a8bb6f83 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -332,7 +332,7 @@ struct TranslationBlock { /* The following data are used to directly call another TB from * the code of this one. This can be done either by emitting direct or * indirect native jump instructions. These jumps are reset so that the TB - * just continue its execution. The TB can be linked to another one by + * just continues its execution. The TB can be linked to another one by * setting one of the jump targets (or patching the jump instruction). Only * two of such jumps are supported. */ @@ -340,7 +340,7 @@ struct TranslationBlock { #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ uintptr_t jmp_target_arg[2]; /* target address or offset */ - /* Each TB has an assosiated circular list of TBs jumping to this one. + /* Each TB has an associated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. * Since each TB can have two jumps, it can participate in two lists. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:41 -0700 Message-Id: <20171010005600.28735-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL 04/23] translate-all: make have_tb_lock static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" It is only used by this object, and it's not exported to any other. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.6 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b3bfe65059..a7c1d4e3f2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -139,7 +139,7 @@ TCGContext tcg_ctx; bool parallel_cpus; /* translation block context */ -__thread int have_tb_lock; +static __thread int have_tb_lock; static void page_table_config_init(void) { From patchwork Tue Oct 10 00:55:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115312 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3168603qgn; Mon, 9 Oct 2017 18:01:04 -0700 (PDT) X-Received: by 10.55.118.195 with SMTP id r186mr11894830qkc.7.1507597264050; Mon, 09 Oct 2017 18:01:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597264; cv=none; d=google.com; s=arc-20160816; b=S5B7bDo0KZbMiGL/O8qar6uVTOLPzgDfWXAwaa0b+gc23531cNsQzOI8HAEplkqACg poLEQjEqu5gA4aG+7lqS5vNPy84MPuY9UW+5IMqY/3jpi6umkmiAA7I306TnM/6pH4bo 8PqhKvNQizCZMcx274l01c93+fc688luhLROQdKCf1jqHnHOV9BH1IZKwLgarvjS2d7P eRAuBB4cQqbSxU447J7cfuiBwIRlIMo9zicQGR9c1Ze6Oj9QvRP+CWk4npIhqAaCsWV+ cvNqfHq8bJqIGjdBpc7ZaUrwIVgUpTTcdD6M60Dif9JEqTUKknhmjg3CyH3j1pVs+C2g GI8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Jmmg93vGlfXYGCWPpMGtBaYKMC23pLLXYbM9fkFhyDY=; b=l1uj9tcjuyb5lD3RBogDLgWDeSzypf6/mA7+xiNsLt5kSvhs64g0PmE0OEWPeJm6AZ aAfdeSmHRVtehU8ONVng+Mz43XWcs9edN0xAMSa7JMeB0AqaO+J50vHUnIj6LgG9tjYi FovvNm4RFhKKqT+rbLX4isvDhNIYZwv86DPtOKZQeyIs4jcEfsKgU4lR3GRwkWWAnSKY AYuwRgefT+rsRdg/xXMKwuoxhscjMLgfx7An250JLlv3GFuP8wPcojckhaI79BgFst5E BSnft7ao8vpn3G1BLt1Ylx2U9lZyu2VBMiY3M/oHwIyZnDUJZ912kfxCkB2OYHoteeRq Qn4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WJErV/y3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:42 -0700 Message-Id: <20171010005600.28735-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL 05/23] cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reusing the have_tb_lock name, which is also defined in translate-all.c, makes code reviewing unnecessarily harder. Avoid potential confusion by renaming the local have_tb_lock variable to something else. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.13.6 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff6866624a..32104b8d8c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -372,7 +372,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - bool have_tb_lock = false; + bool acquired_tb_lock = false; /* we record a subset of the CPU state. It will always be the same before a given translated block @@ -391,7 +391,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, */ mmap_lock(); tb_lock(); - have_tb_lock = true; + acquired_tb_lock = true; /* There's a chance that our desired tb has been translated while * taking the locks so we check again inside the lock. @@ -419,15 +419,15 @@ static inline TranslationBlock *tb_find(CPUState *cpu, #endif /* See if we can patch the calling TB. */ if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - if (!have_tb_lock) { + if (!acquired_tb_lock) { tb_lock(); - have_tb_lock = true; + acquired_tb_lock = true; } if (!tb->invalid) { tb_add_jump(last_tb, tb_exit, tb); } } - if (have_tb_lock) { + if (acquired_tb_lock) { tb_unlock(); } return tb; From patchwork Tue Oct 10 00:55:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115315 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3169613qgn; Mon, 9 Oct 2017 18:02:09 -0700 (PDT) X-Received: by 10.55.201.149 with SMTP id m21mr10916434qkl.330.1507597329541; Mon, 09 Oct 2017 18:02:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597329; cv=none; d=google.com; s=arc-20160816; b=m7VPS/PlZWu6R/oLQqjqB5R0+P/zpEFyL/nuNO3/R5qzTjgRV3k8adjdUbjV9x/DB+ pFV6MYMIcyVu9iLXxqPu2CXMVSzPqapl82q0dPDWh3uxIqKPihyXikwKVyuYuLYbJOdB U6PCIXNlzpXRWJpsga7OWDOhhGYhLq8elPNJJxl2O96VfxL8Ji0IbOGo7MSDtdCgLeO1 QTbdqCg6UYpOzdviaInx0EH8rpecZUdDMqFu92hukyJNFnuLmqwVLc5lZNFwJqVyCM1Y COAdcXxW4KUcyf8HGhSidTpp2f9Pycq7EECcafBN5Nuh3fakj4wnwta6X5WoN+lms4m1 ECVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ldxUa5xmFXm5OESHWBxV8Hz1PBcjUVlLDSHgmwg+rLo=; b=QYubqTgJrivxTtoRcGzWCFK4E1B49ajSDjVCZpPaQcTaruTT4wZpo5BHH9OeHBtFZJ KN2J+DoiU1k616j4EkqaomarEs3ZKPApYZRL3AnJYw4ESgbT/Evf5toamw+EyWUAPsLX 5PAJxq9lEhx+XOGHiatVHvAcDg+d1mdzje2GDM3C7U5cV/Y+9OKlD41N3g5//rhcEjFj BwcelxOs0wuEvDTwJ1q+vQ1Pd8U0XHMlyPAlcJ2mXvgZlaW7OcpX3Ai4PNNPlE0LMMVM 5Zoh6npOnGiiwH9guv1fUmO9FNE8d19/o1MBHXQN0HYFPKtpSDIcv0C8mS/wncvlDrsM gJHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LScE9Y5V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:43 -0700 Message-Id: <20171010005600.28735-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 06/23] tcg/i386: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.6 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 69e49c9f58..63d27f10e7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2499,7 +2499,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) return NULL; } -static int tcg_target_callee_save_regs[] = { +static const int tcg_target_callee_save_regs[] = { #if TCG_TARGET_REG_BITS == 64 TCG_REG_RBP, TCG_REG_RBX, From patchwork Tue Oct 10 00:55:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115317 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3169673qgn; Mon, 9 Oct 2017 18:02:13 -0700 (PDT) X-Received: by 10.55.41.226 with SMTP id p95mr12034175qkp.336.1507597333549; Mon, 09 Oct 2017 18:02:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597333; cv=none; d=google.com; s=arc-20160816; b=k5jFhQV7gZhYBI/tDvtbUMLR5HHiS9XvarShQ4qc06cpqdHA1cruuXJrXoe14uMqbB mE0LQj1Y/OJvniL50/ygMOfcrSXyCvCxCauXLb9S6D+8QPCZH1APoFBrXNyf2Ks/grEp vvk5wr9li6TYMaZApdb5EIjugyUyigriETUWMZkb9vcompuJM+kescmRjbIvTn9LW0+w Ba3YGIG10VpKZtq66Aa/DwyRl2IPdjCJKnDTbEeYK0b1BIa9j9oWbW2zbpFfk8NMafm1 16VYF9gq1w04shf492nN+A559xpvjNzv6Sikr2icYAjhfz/2eqiKtyXrdta5PurdQ3AZ G57Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8GK3TdJPE5M/4MhRTJRRgyiuGlONH/hqYkF1/ZHU9HY=; b=A+NBVTqq1f3SkiHTEDfq5WbyWbUE1ifrLA/ZLj088YcMi2ds3PgqSlYkAo6tsxSPeD hNqe4osU+RLVz7N1Dv2xS2r1PJprjf1yk8mBUVwlnwaKlDBXlGeq/IOHY7GwEEHPs1zx EiOXH82xQqW6tRJvP+ZdOCZTT46gb40A8y5FnehIUFYJ49gy0x+AxCSnw2VTyheWVuUB zzE++y1KeK33W8iFQpcgGaS7qqQ35pEsY+yT4eExUpwlu7XJM3CsND+Dzg1zDzcWwg99 I1zUmKsPhWR8WTOEEYjwqRLCr3R9MuLf1/sR3+rJ7WrZiMwvNXpytJu78Jvg8xoKu845 +GGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hnaJ5Z4C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:44 -0700 Message-Id: <20171010005600.28735-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::232 Subject: [Qemu-devel] [PULL 07/23] tcg/mips: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.6 diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index ce4030602f..e993138930 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2341,7 +2341,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) } } -static int tcg_target_callee_save_regs[] = { +static const int tcg_target_callee_save_regs[] = { TCG_REG_S0, /* used for the global env (TCG_AREG0) */ TCG_REG_S1, TCG_REG_S2, From patchwork Tue Oct 10 00:55:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115319 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3172203qgn; Mon, 9 Oct 2017 18:05:08 -0700 (PDT) X-Received: by 10.200.22.168 with SMTP id r37mr10539255qtj.21.1507597508087; Mon, 09 Oct 2017 18:05:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597508; cv=none; d=google.com; s=arc-20160816; b=FzwsuogoVmx5YJ3vq4AMrsOTSWGY7iC4FDvkTj0qzhx6+kR0oEbx+39RoV1w4jPFLT +l75fZBqZsY5F8+D8VgeomeRBKw/2VOdKMU5VDGmwxm19vhCahLKdOdVZelCGr5rhOk/ ijahW6zH5OQU0G9tYi2Jrz3QKBAiMGADwbajwohocktjvl5eVuzB2GG7SDkBt9gpldDg 5daEsufnpNqfBvRdF+npAY5JdbNC82g5dtYs33lI3TtpPilwtIuwGvyoN+Hs0TrP7ltJ EjOK5YOrDlA70xK3LIWq+JM7LcCm364+Iz7cjeDYbRpVDdXrXhmqJ+oiRdezJ3tI+seR n3FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wd457BU/eqZFjwvIL+UFhAthcD+IPHmAi9wwvo87F4M=; b=MROiqLumFb6WkTYddsGu9JG8e5HDBEKzNeYiM3V5IOV0u+z2yHrHDl7BG9Hemscl2V oADN4hcoAuLXUzqldp8nnHTKnu2KucgzPbRXkTWIVjHdxWEfJPe7DZ1ktxpxjaatuFoU 309AByb+Je9h683n9Van2TSj9Y9QPisNjKt7oYYS/YmFyCiTu9fC86jqwJAdOOJc6W+K 5D3YxpTseHuq5phL/amKkV2c07W+gBVb+/aFbWb9x12MgCPMNu84/lBkn51zcgZy1xby atrhx1KjHA6p6lr2hdCR01tGmYNZMZ+agOMMlQPXH9y+8iJ+ToSIF8F4NMbjmF5Po4iS zAIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Dc1Yy+4B; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:45 -0700 Message-Id: <20171010005600.28735-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PULL 08/23] tcg: remove addr argument from lookup_tb_ptr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 +- tcg/tcg-op.h | 4 ++-- accel/tcg/tcg-runtime.c | 20 ++++++++++---------- target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 5 +---- target/hppa/translate.c | 6 +++--- target/i386/translate.c | 17 +++++------------ target/mips/translate.c | 4 ++-- target/s390x/translate.c | 2 +- target/sh4/translate.c | 4 ++-- tcg/tcg-op.c | 4 ++-- 12 files changed, 32 insertions(+), 42 deletions(-) -- 2.13.6 diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index c41d38a557..1df17d0ba9 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) -DEF_HELPER_FLAGS_2(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env, tl) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..18d01b2f43 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -797,7 +797,7 @@ static inline void tcg_gen_exit_tb(uintptr_t val) void tcg_gen_goto_tb(unsigned idx); /** - * tcg_gen_lookup_and_goto_ptr() - look up a TB and jump to it if valid + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid * @addr: Guest address of the target TB * * If the TB is not valid, jump to the epilogue. @@ -805,7 +805,7 @@ void tcg_gen_goto_tb(unsigned idx); * This operation is optional. If the TCG backend does not implement goto_ptr, * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. */ -void tcg_gen_lookup_and_goto_ptr(TCGv addr); +void tcg_gen_lookup_and_goto_ptr(void); #if TARGET_LONG_BITS == 32 #define tcg_temp_new() tcg_temp_new_i32() diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index aafb171294..b75394aba8 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -144,33 +144,33 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } -void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) +void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, addr_hash; + uint32_t flags, hash; - addr_hash = tb_jmp_cache_hash_func(addr); - tb = atomic_rcu_read(&cpu->tb_jmp_cache[addr_hash]); cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + hash = tb_jmp_cache_hash_func(pc); + tb = atomic_rcu_read(&cpu->tb_jmp_cache[hash]); if (unlikely(!(tb - && tb->pc == addr + && tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags && tb->trace_vcpu_dstate == *cpu->trace_dstate))) { - tb = tb_htable_lookup(cpu, addr, cs_base, flags); + tb = tb_htable_lookup(cpu, pc, cs_base, flags); if (!tb) { return tcg_ctx.code_gen_epilogue; } - atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); + atomic_set(&cpu->tb_jmp_cache[hash], tb); } - qemu_log_mask_and_addr(CPU_LOG_EXEC, addr, + qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, addr, - lookup_symbol(addr)); + tb->tc_ptr, cpu->cpu_index, pc, + lookup_symbol(pc)); return tb->tc_ptr; } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 5a92c4accb..f32c95b9a1 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3029,7 +3029,7 @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) /* FALLTHRU */ case DISAS_PC_UPDATED: if (!use_exit_tb(ctx)) { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; } /* FALLTHRU */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 899ffb96fc..a39b9d3633 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -379,7 +379,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); s->base.is_jmp = DISAS_NORETURN; } } @@ -11363,7 +11363,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_a64_set_pc_im(dc->pc); /* fall through */ case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; case DISAS_EXIT: tcg_gen_exit_tb(0); diff --git a/target/arm/translate.c b/target/arm/translate.c index ab1a12a1b8..fdc46cc525 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4173,10 +4173,7 @@ static inline bool use_goto_tb(DisasContext *s, target_ulong dest) static void gen_goto_ptr(void) { - TCGv addr = tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, cpu_R[15]); - tcg_gen_lookup_and_goto_ptr(addr); - tcg_temp_free(addr); + tcg_gen_lookup_and_goto_ptr(); } /* This will end the TB but doesn't guarantee we'll return to diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b6e2652341..26242f4b3c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -505,7 +505,7 @@ static void gen_goto_tb(DisasContext *ctx, int which, if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -1515,7 +1515,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, if (link != 0) { tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, DISAS_NEXT); } else { cond_prep(&ctx->null_cond); @@ -3873,7 +3873,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/i386/translate.c b/target/i386/translate.c index a8986f4c1a..a74e7bb177 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -2511,7 +2511,7 @@ static void gen_bnd_jmp(DisasContext *s) If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of S->TF. This is used by the syscall/sysret insns. */ static void -do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) +do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) { gen_update_cc_op(s); @@ -2532,12 +2532,8 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) tcg_gen_exit_tb(0); } else if (s->tf) { gen_helper_single_step(cpu_env); - } else if (!TCGV_IS_UNUSED(jr)) { - TCGv vaddr = tcg_temp_new(); - - tcg_gen_add_tl(vaddr, jr, cpu_seg_base[R_CS]); - tcg_gen_lookup_and_goto_ptr(vaddr); - tcg_temp_free(vaddr); + } else if (jr) { + tcg_gen_lookup_and_goto_ptr(); } else { tcg_gen_exit_tb(0); } @@ -2547,10 +2543,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) static inline void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf) { - TCGv unused; - - TCGV_UNUSED(unused); - do_gen_eob_worker(s, inhibit, recheck_tf, unused); + do_gen_eob_worker(s, inhibit, recheck_tf, false); } /* End of block. @@ -2569,7 +2562,7 @@ static void gen_eob(DisasContext *s) /* Jump to register */ static void gen_jr(DisasContext *s, TCGv dest) { - do_gen_eob_worker(s, false, false, dest); + do_gen_eob_worker(s, false, false, true); } /* generate a jump to eip. No segment change must happen before as a diff --git a/target/mips/translate.c b/target/mips/translate.c index d16d879df7..ac05f3aa09 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4303,7 +4303,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); } } @@ -10883,7 +10883,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); break; default: fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 9ef95141f9..165d2cac3e 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5949,7 +5949,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) } else if (use_exit_tb(&dc) || status == EXIT_PC_STALE_NOCHAIN) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(psw_addr); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 10191073b2..8db9fba26e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -261,7 +261,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -278,7 +278,7 @@ static void gen_jump(DisasContext * ctx) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 688d91755b..d3c0e4799e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2588,11 +2588,11 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, idx); } -void tcg_gen_lookup_and_goto_ptr(TCGv addr) +void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { TCGv_ptr ptr = tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env, addr); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { From patchwork Tue Oct 10 00:55:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115316 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3169621qgn; Mon, 9 Oct 2017 18:02:10 -0700 (PDT) X-Received: by 10.200.51.39 with SMTP id t36mr7588967qta.337.1507597330287; Mon, 09 Oct 2017 18:02:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597330; cv=none; d=google.com; s=arc-20160816; b=k5iiLd4sHw5XBeAtbfbKG+ny3LYNmDiRj1kDuwQiS+JKcV0OqASpwAoGS1jpUeIFSN yrBKUf5MajEppdvjJvmu3rmdOu9eYe1EMJ5lkkKrhfs25yVk8JtavbE53sHNYdI5WF8t rjSf4qoHKaBCIJGRPr06sjFFHXPh9a4gULE/v3Re9EBX6ccnAp5qmAog/mcEtvTXkiSv 6B8W9gMMBf4IpiSXIIpLUMkn+xpKlqXKG8BfV/xKdXV+vSFu84hChNwnsob/5NzTPSof uIrpFrv4OSCCRP4x43sA0sZNLzemeJcflfAN78R4bM1oQVpl7UzA0bHZU7Z5sTT2bIwn V3kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=w/K6G1uL/Y5M6sFMk/lh/F5fVU0kU85wSm3FWNOsRgc=; b=yqVi+ZBiU3IX4UrXcTVpNbOFVUuaJw6ikVnbpy1OEWXqqIJouDjkrUGQ2PkYIFXWVa eM5zyWiFTNecNSIJTL5MGeRl73atwdazxv9ENwgUgcrpVappqPEFgL4pPJiPYzh03FKS sFPiQGAW+PkO4QjqAR265f72OAO4F0UsgQ1KV+JT2+gxtI87aHqXgalqUMueNTI66/kT 8mPPfWHP+mcOmelqDCXwBo0DamEckKgw+WY/IdHQW/vVWu/XPwMbLc3+TFrZLrnRurcJ 2UBHC/VLA+Q/ckE09PjeY3W1RAaaP3XrW5f1a9W2X6opkLHyPJmnENjam+MosWHA9Eyj ee3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=igA0YPUG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:46 -0700 Message-Id: <20171010005600.28735-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 09/23] tcg: consolidate TB lookups in tb_lookup__cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" This avoids duplicating code. cpu_exec_step will also use the new common function once we integrate parallel_cpus into tb->cflags. Note that in this commit we also fix a race, described by Richard Henderson during review. Think of this scenario with threads A and B: (A) Lookup succeeds for TB in hash without tb_lock (B) Sets the TB's tb->invalid flag (B) Removes the TB from tb_htable (B) Clears all CPU's tb_jmp_cache (A) Store TB into local tb_jmp_cache Given that order of events, (A) will keep executing that invalid TB until another flush of its tb_jmp_cache happens, which in theory might never happen. We can fix this by checking the tb->invalid flag every time we look up a TB from tb_jmp_cache, so that in the above scenario, next time we try to find that TB in tb_jmp_cache, we won't, and will therefore be forced to look it up in tb_htable. Performance-wise, I measured a small improvement when booting debian-arm. Note that inlining pays off: Performance counter stats for 'taskset -c 0 qemu-system-arm \ -machine type=virt -nographic -smp 1 -m 4096 \ -netdev user,id=unet,hostfwd=tcp::2222-:22 \ -device virtio-net-device,netdev=unet \ -drive file=jessie.qcow2,id=myblock,index=0,if=none \ -device virtio-blk-device,drive=myblock \ -kernel kernel.img -append console=ttyAMA0 root=/dev/vda1 \ -name arm,debug-threads=on -smp 1' (10 runs): Before: 18714.917392 task-clock # 0.952 CPUs utilized ( +- 0.95% ) 23,142 context-switches # 0.001 M/sec ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 10,558 page-faults # 0.001 M/sec ( +- 0.95% ) 53,957,727,252 cycles # 2.883 GHz ( +- 0.91% ) [83.33%] 24,440,599,852 stalled-cycles-frontend # 45.30% frontend cycles idle ( +- 1.20% ) [83.33%] 16,495,714,424 stalled-cycles-backend # 30.57% backend cycles idle ( +- 0.95% ) [66.66%] 76,267,572,582 instructions # 1.41 insns per cycle # 0.32 stalled cycles per insn ( +- 0.87% ) [83.34%] 12,692,186,323 branches # 678.186 M/sec ( +- 0.92% ) [83.35%] 263,486,879 branch-misses # 2.08% of all branches ( +- 0.73% ) [83.34%] 19.648474449 seconds time elapsed ( +- 0.82% ) After, w/ inline (this patch): 18471.376627 task-clock # 0.955 CPUs utilized ( +- 0.96% ) 23,048 context-switches # 0.001 M/sec ( +- 0.48% ) 1 CPU-migrations # 0.000 M/sec 10,708 page-faults # 0.001 M/sec ( +- 0.81% ) 53,208,990,796 cycles # 2.881 GHz ( +- 0.98% ) [83.34%] 23,941,071,673 stalled-cycles-frontend # 44.99% frontend cycles idle ( +- 0.95% ) [83.34%] 16,161,773,848 stalled-cycles-backend # 30.37% backend cycles idle ( +- 0.76% ) [66.67%] 75,786,269,766 instructions # 1.42 insns per cycle # 0.32 stalled cycles per insn ( +- 1.24% ) [83.34%] 12,573,617,143 branches # 680.708 M/sec ( +- 1.34% ) [83.33%] 260,235,550 branch-misses # 2.07% of all branches ( +- 0.66% ) [83.33%] 19.340502161 seconds time elapsed ( +- 0.56% ) After, w/o inline: 18791.253967 task-clock # 0.954 CPUs utilized ( +- 0.78% ) 23,230 context-switches # 0.001 M/sec ( +- 0.42% ) 1 CPU-migrations # 0.000 M/sec 10,563 page-faults # 0.001 M/sec ( +- 1.27% ) 54,168,674,622 cycles # 2.883 GHz ( +- 0.80% ) [83.34%] 24,244,712,629 stalled-cycles-frontend # 44.76% frontend cycles idle ( +- 1.37% ) [83.33%] 16,288,648,572 stalled-cycles-backend # 30.07% backend cycles idle ( +- 0.95% ) [66.66%] 77,659,755,503 instructions # 1.43 insns per cycle # 0.31 stalled cycles per insn ( +- 0.97% ) [83.34%] 12,922,780,045 branches # 687.702 M/sec ( +- 1.06% ) [83.34%] 261,962,386 branch-misses # 2.03% of all branches ( +- 0.71% ) [83.35%] 19.700174670 seconds time elapsed ( +- 0.56% ) Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/tb-lookup.h | 49 ++++++++++++++++++++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 47 ++++++++++++++++++---------------------------- accel/tcg/tcg-runtime.c | 24 ++++++------------------ 3 files changed, 73 insertions(+), 47 deletions(-) create mode 100644 include/exec/tb-lookup.h -- 2.13.6 diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h new file mode 100644 index 0000000000..9d32cb0c6e --- /dev/null +++ b/include/exec/tb-lookup.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017, Emilio G. Cota + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef EXEC_TB_LOOKUP_H +#define EXEC_TB_LOOKUP_H + +#include "qemu/osdep.h" + +#ifdef NEED_CPU_H +#include "cpu.h" +#else +#include "exec/poison.h" +#endif + +#include "exec/exec-all.h" +#include "exec/tb-hash.h" + +/* Might cause an exception, so have a longjmp destination ready */ +static inline TranslationBlock * +tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base, + uint32_t *flags) +{ + CPUArchState *env = (CPUArchState *)cpu->env_ptr; + TranslationBlock *tb; + uint32_t hash; + + cpu_get_tb_cpu_state(env, pc, cs_base, flags); + hash = tb_jmp_cache_hash_func(*pc); + tb = atomic_rcu_read(&cpu->tb_jmp_cache[hash]); + if (likely(tb && + tb->pc == *pc && + tb->cs_base == *cs_base && + tb->flags == *flags && + tb->trace_vcpu_dstate == *cpu->trace_dstate && + !atomic_read(&tb->invalid))) { + return tb; + } + tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags); + if (tb == NULL) { + return NULL; + } + atomic_set(&cpu->tb_jmp_cache[hash], tb); + return tb; +} + +#endif /* EXEC_TB_LOOKUP_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 32104b8d8c..f8a1d68db7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "qemu/rcu.h" #include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "exec/log.h" #include "qemu/main-loop.h" #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) @@ -368,43 +369,31 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) { - CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock = false; - /* we record a subset of the CPU state. It will - always be the same before a given translated block - is executed. */ - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]); - if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base || - tb->flags != flags || - tb->trace_vcpu_dstate != *cpu->trace_dstate)) { - tb = tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - - /* mmap_lock is needed by tb_gen_code, and mmap_lock must be - * taken outside tb_lock. As system emulation is currently - * single threaded the locks are NOPs. - */ - mmap_lock(); - tb_lock(); - acquired_tb_lock = true; - - /* There's a chance that our desired tb has been translated while - * taking the locks so we check again inside the lock. - */ - tb = tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - /* if no translated code available, then translate it now */ - tb = tb_gen_code(cpu, pc, cs_base, flags, 0); - } + tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb == NULL) { + /* mmap_lock is needed by tb_gen_code, and mmap_lock must be + * taken outside tb_lock. As system emulation is currently + * single threaded the locks are NOPs. + */ + mmap_lock(); + tb_lock(); + acquired_tb_lock = true; - mmap_unlock(); + /* There's a chance that our desired tb has been translated while + * taking the locks so we check again inside the lock. + */ + tb = tb_htable_lookup(cpu, pc, cs_base, flags); + if (likely(tb == NULL)) { + /* if no translated code available, then translate it now */ + tb = tb_gen_code(cpu, pc, cs_base, flags, 0); } + mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup */ atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index b75394aba8..d0edd944b0 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -27,7 +27,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" @@ -149,24 +149,12 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu = ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, hash; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - hash = tb_jmp_cache_hash_func(pc); - tb = atomic_rcu_read(&cpu->tb_jmp_cache[hash]); - - if (unlikely(!(tb - && tb->pc == pc - && tb->cs_base == cs_base - && tb->flags == flags - && tb->trace_vcpu_dstate == *cpu->trace_dstate))) { - tb = tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - return tcg_ctx.code_gen_epilogue; - } - atomic_set(&cpu->tb_jmp_cache[hash], tb); - } + uint32_t flags; + tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb == NULL) { + return tcg_ctx.code_gen_epilogue; + } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", tb->tc_ptr, cpu->cpu_index, pc, From patchwork Tue Oct 10 00:55:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115321 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3173369qgn; Mon, 9 Oct 2017 18:06:39 -0700 (PDT) X-Received: by 10.55.43.227 with SMTP id r96mr12493576qkr.216.1507597599448; Mon, 09 Oct 2017 18:06:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597599; cv=none; d=google.com; s=arc-20160816; b=RWuHQxJGaB01YwkwlNxqkC+RL/ppycR14nbcX+ty7v0JZ0POJIAoIXKxEE9EJC8BTh I542GrE22dx2AiPTLAb+zoOCiP5OwIO0uE3vVQCy9juI/TcxNpija1Q39ePdrxU3NRw1 50sqSlwLiAMkn7y6Fa17gHNrV+ylRSWNC6jxYHo7zQZ6pt/KVBkAYMzWUPRkhAM5LQkG h63L0XVffY3qlcAw4aPxSDMLZ7q1xCgFXqnZFoQQ9ze8+CgA6+Gpx/4wmPj5s13HCujT LG/S7Q4d+Ul9+bKbQYiwHafrHnBldaRfMoXFxLL8lVkHdeVoveSA78gQPQMkN7ZlAJjU Tf/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=AlG96ZS7wj0sBsmbSuh4GY4IomgcygTB/0W6OfuBaEA=; b=mGN3JVIZCxRRenUaYUO95MTgr1uk3psvg0WtuDmdaTO2xhsMkG17gHWy2SdHpiH3v6 KbcVqcUJE9X/KeH8SxXQH/0dyPKDghWm56sdYzRms/41slAj6/FHguw1sqGdenc9/DdQ t6z82K6BUiVeR39GOEMoVFXmz9kHMMIEjcOzATtgTJkQckt1zsxzmqVD9DgJRkYP7ZZj MZbuJCXh9Uf2WbSfLuGX95nq/iKmoRfIudPqIkm7fbdWoL/wrfhcFFIYMpoPa+2cI7A/ JAM5/oRu4vKmQaFia5WQWNmoUDqzkmGZSkyUpfO92FaWmNzqL6eaI4wqCPHBfZHcaxft xo6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G0DYuYbs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:47 -0700 Message-Id: <20171010005600.28735-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 10/23] exec-all: bring tb->invalid into tb->cflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" This gets rid of a hole in struct TranslationBlock. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 +-- include/exec/tb-lookup.h | 2 +- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 3 +-- 4 files changed, 5 insertions(+), 7 deletions(-) -- 2.13.6 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a9a8bb6f83..3135aaf4c9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -314,12 +314,11 @@ struct TranslationBlock { #define CF_NOCACHE 0x10000 /* To be freed after execution */ #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ +#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */ /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; - uint16_t invalid; - void *tc_ptr; /* pointer to the translated code */ uint8_t *tc_search; /* pointer to search data */ /* original tb when cflags has CF_NOCACHE */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 9d32cb0c6e..436b6d5ecf 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -35,7 +35,7 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base, tb->cs_base == *cs_base && tb->flags == *flags && tb->trace_vcpu_dstate == *cpu->trace_dstate && - !atomic_read(&tb->invalid))) { + !(atomic_read(&tb->cflags) & CF_INVALID))) { return tb; } tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f8a1d68db7..9cd809d607 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -294,7 +294,7 @@ static bool tb_cmp(const void *p, const void *d) tb->cs_base == desc->cs_base && tb->flags == desc->flags && tb->trace_vcpu_dstate == desc->trace_vcpu_dstate && - !atomic_read(&tb->invalid)) { + !(atomic_read(&tb->cflags) & CF_INVALID)) { /* check next page if needed */ if (tb->page_addr[1] == -1) { return true; @@ -412,7 +412,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, tb_lock(); acquired_tb_lock = true; } - if (!tb->invalid) { + if (!(tb->cflags & CF_INVALID)) { tb_add_jump(last_tb, tb_exit, tb); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a7c1d4e3f2..ed65d68709 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1073,7 +1073,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) assert_tb_locked(); - atomic_set(&tb->invalid, true); + atomic_set(&tb->cflags, tb->cflags | CF_INVALID); /* remove the TB from the hash list */ phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); @@ -1269,7 +1269,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags = flags; tb->cflags = cflags; tb->trace_vcpu_dstate = *cpu->trace_dstate; - tb->invalid = false; #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of From patchwork Tue Oct 10 00:55:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115310 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3166783qgn; Mon, 9 Oct 2017 17:58:40 -0700 (PDT) X-Received: by 10.200.20.6 with SMTP id k6mr15973038qtj.189.1507597120767; Mon, 09 Oct 2017 17:58:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597120; cv=none; d=google.com; s=arc-20160816; b=zRwRpvREkT6goZjIAtZcl6P3gEQmxIMjthr07fwo9DCTBUbz8aJxJCl2Gos3jxMHMo 8CctP4Xc8DJkM3mUp3XjlfRYEXNf5BcQLXfqFuUIgZ/Lwmu+hfk91z1gr685wtb9ND5S N5ZCjAsqURQW6WwNyef8w+4l6Imaj5o6umk2554KVOG/oy0pEKaugBN3Au+BQxJncqr2 BU6QwisCwTVdi4bMw8P0TE0zhr4t4U0Ru55JjQmkzFixkkW54l16DnpImeC4oikVdN6v b9CjF6BHObm30wvV77vI2ojojuLFzQQPpc8ok34C2nD5FlYhoHpcFEn4qv4zsXxP/dnR Gnzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=LAawtX8GSa0/i2pqKXJe98VeX6zP0igCbj0ZmpFAsd0=; b=yvMfURLQ8D1R6xycbfl0KWqNEtU0ZLzUGogotbuuqgQOS7bSSkztRpIJc6S4TQYiU/ KAwHEVwcb4bb0mEvfQx9xsMH95oQHU6H0l1dl0szGN+Okc16Af0cZCITcHGlrXaL9FQ+ ore3s3lFTItoiWZblLLtp3qN7i74AUJx9BwhgLXLr+tuYn1bxLkpshvhTNxrZMTVZReT 6qVIMAe06QD4CLSGZ8xoL/Lx7m93/ODrvhYmKP1/8FOqfqEmvx8fxNiCZXHMq0f02t+i +ZFbaKorYtqkNU4AaMM/Qpdu2BFjqUh7NQHxI8FtOjvDcm9KdPz1RyGuxNKPzYnQtr6H 80dQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c1NXz+LX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:48 -0700 Message-Id: <20171010005600.28735-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 11/23] translate-all: define and use DEBUG_TB_FLUSH_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" This gets rid of some ifdef checks while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) -- 2.13.6 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ed65d68709..799b027e79 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ +#ifdef DEBUG_TB_FLUSH +#define DEBUG_TB_FLUSH_GATE 1 +#else +#define DEBUG_TB_FLUSH_GATE 0 +#endif + #if !defined(CONFIG_USER_ONLY) /* TB consistency checks only implemented for usermode emulation. */ #undef DEBUG_TB_CHECK @@ -899,13 +905,13 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) goto done; } -#if defined(DEBUG_TB_FLUSH) - printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", - (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)) / - tcg_ctx.tb_ctx.nb_tbs : 0); -#endif + if (DEBUG_TB_FLUSH_GATE) { + printf("qemu: flush code_size=%td nb_tbs=%d avg_tb_size=%td\n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, + tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / + tcg_ctx.tb_ctx.nb_tbs : 0); + } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); From patchwork Tue Oct 10 00:55:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115322 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3174003qgn; Mon, 9 Oct 2017 18:07:28 -0700 (PDT) X-Received: by 10.200.38.110 with SMTP id v43mr17197865qtv.296.1507597648363; Mon, 09 Oct 2017 18:07:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597648; cv=none; d=google.com; s=arc-20160816; b=P2XuwDpSrBbD2+8OJjzz6NwFgo7vPdXEupYksmTPh8VS/ojLGfJqVMr8qbg3DrhvqM IWc3/32uwCtN8qtIrLBg77xhht2cBxKHFxUDFoW37ZwbWTSYb0fVhiNbu8ksfFz3b5RT hiuHLJPp5lll8w7iXnDe72cZCsIJIEvV7xy4kPfebfXePfuWdX30rGq/BnasnocrR7Qh KdJud5lle7FEDIHqq548M2Mh/6wHWpbUhqj066iCmiXPDdMOh0qi7bHR9JGsOwowHbcV aZ3HvKxUCE39I/YR23y73h+gwo5L9kyQln5gcLSC8Xa+PZmjB7scyVIOZdAbEIOjVgZm 6kkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=nCHgQRfd/6L6A+ZFLqYH/ozIQbUkersXx+TPVXfIV2w=; b=qkemRMLOuI3v3ICSLED2m09BQITyiGN4tZDJ6Y2pkB+fMZ2ATh8UJTpzOjeRve2S/A 2Uufc8qp+f+EP5v1hLvsAZ5Tn/R6dZXp7Ti3M7SxGcfvq8A3LSwbf8ILcmSL3U972uM+ Z59FJNrnBUE2C9MgGiLLCex2V4eRcJH2MclfjU+fcJ/CsMGdGr8ma8YgbPR7KZjGh4Np bhrAeqPOFpm5Uz1X8o8ca5hDg6j7v2KDuM5v6oeWtD+ucvWoMSIYk00JyXpzjoO19wO5 Iml9Wv8v1poe53apAco6okNu/bRxoBAYGB8XmB7Wvw24CK06btDfkKARWQhuatTlpn+a LJfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JtDbDyIJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:49 -0700 Message-Id: <20171010005600.28735-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 12/23] exec-all: introduce TB_PAGE_ADDR_FMT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" And fix the following warning when DEBUG_TB_INVALIDATE is enabled in translate-all.c: CC mipsn32-linux-user/accel/tcg/translate-all.o /data/src/qemu/accel/tcg/translate-all.c: In function ‘tb_alloc_page’: /data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘tb_page_addr_t {aka unsigned int}’ [-Werror=format=] printf("protecting code page: 0x" TARGET_FMT_lx "\n", ^ cc1: all warnings being treated as errors /data/src/qemu/rules.mak:66: recipe for target 'accel/tcg/translate-all.o' failed make[1]: *** [accel/tcg/translate-all.o] Error 1 Makefile:328: recipe for target 'subdir-mipsn32-linux-user' failed make: *** [subdir-mipsn32-linux-user] Error 2 cota@flamenco:/data/src/qemu/build ((18f3fe1...) *$)$ Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 ++ accel/tcg/translate-all.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) -- 2.13.6 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 3135aaf4c9..79f8041811 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,10 @@ type. */ #if defined(CONFIG_USER_ONLY) typedef abi_ulong tb_page_addr_t; +#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx #else typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif #include "qemu/log.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 799b027e79..90b3eed9c6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1193,8 +1193,7 @@ static inline void tb_alloc_page(TranslationBlock *tb, mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); #ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TARGET_FMT_lx "\n", - page_addr); + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); #endif } #else From patchwork Tue Oct 10 00:55:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115323 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3174075qgn; Mon, 9 Oct 2017 18:07:34 -0700 (PDT) X-Received: by 10.200.38.50 with SMTP id u47mr13972999qtu.112.1507597654010; Mon, 09 Oct 2017 18:07:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597654; cv=none; d=google.com; s=arc-20160816; b=Apgd4tc+U8AvHsmnJP5WP/YSkS0Egfruw9sNU5sb4svEJybHAnOCJb4ZNlPH7SaTbe 5rxyhNRNsNzN9h4uo+oEE/z5d5xoV/UvwtBceQAYbF8TCemmLL1+j7/rXQvQ4osF/YNl OUGekDvz+DrKq4Mok3k9SevRDvBwkYWvMXvhk0ta57+QtDhwLEeh52M9Z7tj+640zZWw lEw/bvAUyWEqGO/6A8n25RHS7SKcWZNQZJg88+iXGLGPUenwRyi2FKOqGRVOdYMYv1Aw /spkvy+gn+FkSoS+7Wdq+E/md8ceBN8qW4oKdjq0kQD4Pi5nqlquB+yUgr6hQt2YIZBd L4Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=WtXhE5x32c2lhsKUN0JsspH8di2RIEl9RhyDrTbaDsw=; b=b4y7mzJIZT3j5Hxc7Y/DnD2UXXtphNtqoBQTlBqZHF7fQVxfmc/yFUSbfIFLQcUxPU 1becTaHEkZ6G26YmL5lNG+t22BKHC5QtwXODBTjiwJFmgXtiZnoiwtnQrxtDkTiOmL8j +bY3Nra1e2WgCnEn6ZX7kihUzUgqefgoVg8FSa1tGcoWb4OFW2oRJ+SwHGkVUoCB+rkT YajD92WgtBzGpRUaUhwh8r8Wr5hgorgOudTalNg5HJtnaLP8FQcVWi5rMQQPVFEPUC68 c4+Zs9NGkykdCiMpKvxUiavXyq+2Bkqyz8mr5u8wVpyhdJ7j/SiOvbGzoc+V6LoByEYa 4XFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KGtNX2ZY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:50 -0700 Message-Id: <20171010005600.28735-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 13/23] translate-all: define and use DEBUG_TB_INVALIDATE_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" This gets rid of an ifdef check while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -- 2.13.6 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 90b3eed9c6..6b853b329c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ +#ifdef DEBUG_TB_INVALIDATE +#define DEBUG_TB_INVALIDATE_GATE 1 +#else +#define DEBUG_TB_INVALIDATE_GATE 0 +#endif + #ifdef DEBUG_TB_FLUSH #define DEBUG_TB_FLUSH_GATE 1 #else @@ -1192,9 +1198,9 @@ static inline void tb_alloc_page(TranslationBlock *tb, } mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); -#ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); -#endif + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); + } } #else /* if some code is already present, then the pages are already From patchwork Tue Oct 10 00:55:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115325 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3175509qgn; Mon, 9 Oct 2017 18:09:26 -0700 (PDT) X-Received: by 10.200.15.40 with SMTP id e37mr12109974qtk.159.1507597766232; Mon, 09 Oct 2017 18:09:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597766; cv=none; d=google.com; s=arc-20160816; b=wlSizD3i8vzQZgZNXCoDf64fyl+cXI3FBIb1qRkTrV4Fh4MHBVCZCoyAlhKqFik0wS HoleyjnGjLc9+q6TErXbw9Yic8qZqk7AFEQ3tSZyMXsBgnE3XE9ZT/bEyzINl+nO8R5D IYYe/ls2m+wKG6WqQrDPUGjlPCL267Wo4gB/s2A5K72Ct6XKLEb68qxBI//cRegP04qO 4TlAyg/v4143OlejPi9YpoUlHMzn1i+s2qgjfQxmyUJ2sVgwpfShWk4SkGW/u5X5jlsY r2SMP/0kk5QzjLXF9I4SLdxYaw0es41k4NCQsneWwcKxVgk9Ci0pWJ4pxarecvAV7UKl lEVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=BlqfHrkOPjLzLqDyXBqDW01UXizdoh9zUOpMpGA3NFk=; b=NuDHiSWA4zYeoR08Csm6YhyHX+VzSov7Ruo63Z/8o2FiRtjxN6Oe8iPffFPokFW2OZ MbUBLn3iaOMF1JB/iUxIGjxr9oV9pKneQlirUQgvzLLTb/88ZUfPVz46HFcoXA8639l9 x8M+0jQ235sPMkzDfK86t3/0ON1GmeNd1FtJ6dezwmst7I84gWl/aNeC8LO+UicpbePA KMtJ+6ybL9/CWrfSlhU5PUARTg4ZdLUk890NUsvdjKR2onfTEgmj/+EhPzotebHP/JiF 1ZfZu/wMofAUqVnmaKJmotWceFJ/y3nIPdh1M2pyZop9J16HHKHvLe8DzPKgMXrXJKfv 3Gfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fzdaXHJ7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:51 -0700 Message-Id: <20171010005600.28735-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 14/23] translate-all: define and use DEBUG_TB_CHECK_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" This prevents bit rot by ensuring the debug code is compiled when building a user-mode target. Unfortunately the helpers are user-mode-only so we cannot fully get rid of the ifdef checks. Add a comment to explain this. Suggested-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) -- 2.13.6 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b853b329c..26efad302d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -82,6 +82,12 @@ #undef DEBUG_TB_CHECK #endif +#ifdef DEBUG_TB_CHECK +#define DEBUG_TB_CHECK_GATE 1 +#else +#define DEBUG_TB_CHECK_GATE 0 +#endif + /* Access to the various translations structures need to be serialised via locks * for consistency. This is automatic for SoftMMU based system * emulation due to its single threaded nature. In user-mode emulation @@ -950,7 +956,13 @@ void tb_flush(CPUState *cpu) } } -#ifdef DEBUG_TB_CHECK +/* + * Formerly ifdef DEBUG_TB_CHECK. These debug functions are user-mode-only, + * so in order to prevent bit rot we compile them unconditionally in user-mode, + * and let the optimizer get rid of them by wrapping their user-only callers + * with if (DEBUG_TB_CHECK_GATE). + */ +#ifdef CONFIG_USER_ONLY static void do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp) @@ -994,7 +1006,7 @@ static void tb_page_check(void) qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); } -#endif +#endif /* CONFIG_USER_ONLY */ static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) { @@ -1236,8 +1248,10 @@ static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); -#ifdef DEBUG_TB_CHECK - tb_page_check(); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_page_check(); + } #endif } @@ -2223,8 +2237,10 @@ int page_unprotect(target_ulong address, uintptr_t pc) /* and since the content will be modified, we must invalidate the corresponding translated code. */ current_tb_invalidated |= tb_invalidate_phys_page(addr, pc); -#ifdef DEBUG_TB_CHECK - tb_invalidate_check(addr); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_invalidate_check(addr); + } #endif } mprotect((void *)g2h(host_start), qemu_host_page_size, From patchwork Tue Oct 10 00:55:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115327 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3176773qgn; Mon, 9 Oct 2017 18:11:08 -0700 (PDT) X-Received: by 10.55.102.215 with SMTP id a206mr11898370qkc.269.1507597868035; Mon, 09 Oct 2017 18:11:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597868; cv=none; d=google.com; s=arc-20160816; b=GiJj5UXh+E3/CwYlegT+8kT5Fim21CHkMIOfdRraKZ5ri2FfIhzw38Omqyd3CGLAl8 qHQRYHGuaplJeSjGQMtWKTBuhSRq7cIwWR7CEuVUDqhY8uefF52RnGh+8o4hv8vtmO1j J5bvyuju/8omWrHLRH7i8qubhX0Rp9W1StmjLSgvkU+ELqdK9+oDADLy5hLwTuE6aHKf lcIFQR+OWp7YjSLz7IogE3UzZUSbPctw4TXifjSq6pgt+RvQ98inNTm+ZQY8yWZ1nFbk +YIIPYY2WYqfQIgJHASFXh4vw2XWZCO69wn2SKvB60WQRRrDvZU1zs4G6CQecYWiZ2xG xYWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yvehDTJT52The5SOdJt0x6s/jRMheKd5KLpLoVOTPQ4=; b=YhOYDLrgbHz7AYGNqPMpnc0hqLolQV4ZdrS72HeprBo9Of2Q3yp7Fva2C/0NMfk+Wn GA5nNqoAsA0lw/MqZJPgnq8roNtMnH7pbrYT1enBGGJipcpA5pnbJ796dao/lkwtqRQG ofxa7c7cqjxDL1yZ/W0AZvnK9jKnD5MKlmnvxgBGo/szM9c8S1uQN/V6X1VFzetx6FAb u2mEc0MgFEJMiorYQT+8VI2jRuZ4cOrk3e11pB+BajprNSWPcfj8m/LMq6C0I7kdax62 +Eumy2HgWgmMGslvZy6kIQrUWISP2cgz57wU51Oh9TDCAW7ojJdBjhX0qkecc88Pr394 meLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fbAVAwKi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:52 -0700 Message-Id: <20171010005600.28735-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 15/23] exec-all: extract tb->tc_* into a separate struct tc_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" In preparation for adding tc.size to be able to keep track of TB's using the binary search tree implementation from glib. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++++++++++-- accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/tcg-runtime.c | 4 ++-- accel/tcg/translate-all.c | 24 ++++++++++++------------ tcg/tcg.c | 4 ++-- 5 files changed, 33 insertions(+), 25 deletions(-) -- 2.13.6 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 79f8041811..53f1835c43 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -303,6 +303,14 @@ static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif +/* + * Translation Cache-related fields of a TB. + */ +struct tb_tc { + void *ptr; /* pointer to the translated code */ + uint8_t *search; /* pointer to search data */ +}; + struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -321,8 +329,8 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; - void *tc_ptr; /* pointer to the translated code */ - uint8_t *tc_search; /* pointer to search data */ + struct tb_tc tc; + /* original tb when cflags has CF_NOCACHE */ struct TranslationBlock *orig_tb; /* first and second physical page containing code. The lower bit diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9cd809d607..363dfa208a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -143,11 +143,11 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr = itb->tc_ptr; + uint8_t *tb_ptr = itb->tc.ptr; qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %p [%d: " TARGET_FMT_lx "] %s\n", - itb->tc_ptr, cpu->cpu_index, itb->pc, + itb->tc.ptr, cpu->cpu_index, itb->pc, lookup_symbol(itb->pc)); #if defined(DEBUG_DISAS) @@ -179,7 +179,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc_ptr, last_tb->pc, + last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); if (cc->synchronize_from_tb) { cc->synchronize_from_tb(cpu, last_tb); @@ -334,7 +334,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) { if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset = tb->jmp_target_arg[n]; - uintptr_t tc_ptr = (uintptr_t)tb->tc_ptr; + uintptr_t tc_ptr = (uintptr_t)tb->tc.ptr; tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); } else { tb->jmp_target_arg[n] = addr; @@ -354,11 +354,11 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); + tb->tc.ptr, tb->pc, n, + tb_next->tc.ptr, tb_next->pc); /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); /* add in TB jmp circular list */ tb->jmp_list_next[n] = tb_next->jmp_list_first; diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d0edd944b0..54d89100d9 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -157,9 +157,9 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, pc, + tb->tc.ptr, cpu->cpu_index, pc, lookup_symbol(pc)); - return tb->tc_ptr; + return tb->tc.ptr; } void HELPER(exit_atomic)(CPUArchState *env) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 26efad302d..c5ce99d549 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -260,7 +260,7 @@ static target_long decode_sleb128(uint8_t **pp) which comes from the host pc of the end of the code implementing the insn. Each line of the table is encoded as sleb128 deltas from the previous - line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }. + line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. That is, the first column is seeded with the guest pc, the last column with the host pc, and the middle columns with zeros. */ @@ -270,7 +270,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) uint8_t *p = block; int i, j, n; - tb->tc_search = block; + tb->tc.search = block; for (i = 0, n = tb->icount; i < n; ++i) { target_ulong prev; @@ -305,9 +305,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc) { target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; - uintptr_t host_pc = (uintptr_t)tb->tc_ptr; + uintptr_t host_pc = (uintptr_t)tb->tc.ptr; CPUArchState *env = cpu->env_ptr; - uint8_t *p = tb->tc_search; + uint8_t *p = tb->tc.search; int i, j, num_insns = tb->icount; #ifdef CONFIG_PROFILER int64_t ti = profile_getclock(); @@ -858,7 +858,7 @@ void tb_free(TranslationBlock *tb) tb == tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { size_t struct_size = ROUND_UP(sizeof(*tb), qemu_icache_linesize); - tcg_ctx.code_gen_ptr = tb->tc_ptr - struct_size; + tcg_ctx.code_gen_ptr = tb->tc.ptr - struct_size; tcg_ctx.tb_ctx.nb_tbs--; } } @@ -1059,7 +1059,7 @@ static inline void tb_remove_from_jmp_list(TranslationBlock *tb, int n) another TB */ static inline void tb_reset_jump(TranslationBlock *tb, int n) { - uintptr_t addr = (uintptr_t)(tb->tc_ptr + tb->jmp_reset_offset[n]); + uintptr_t addr = (uintptr_t)(tb->tc.ptr + tb->jmp_reset_offset[n]); tb_set_jmp_target(tb, n, addr); } @@ -1288,7 +1288,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } gen_code_buf = tcg_ctx.code_gen_ptr; - tb->tc_ptr = gen_code_buf; + tb->tc.ptr = gen_code_buf; tb->pc = pc; tb->cs_base = cs_base; tb->flags = flags; @@ -1307,7 +1307,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_intermediate_code(cpu, tb); tcg_ctx.cpu = NULL; - trace_translate_block(tb, tb->pc, tb->tc_ptr); + trace_translate_block(tb, tb->pc, tb->tc.ptr); /* generate machine code */ tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID; @@ -1354,11 +1354,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_lock(); qemu_log("OUT: [size=%d]\n", gen_code_size); if (tcg_ctx.data_gen_ptr) { - size_t code_size = tcg_ctx.data_gen_ptr - tb->tc_ptr; + size_t code_size = tcg_ctx.data_gen_ptr - tb->tc.ptr; size_t data_size = gen_code_size - code_size; size_t i; - log_disas(tb->tc_ptr, code_size); + log_disas(tb->tc.ptr, code_size); for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { if (sizeof(tcg_target_ulong) == 8) { @@ -1372,7 +1372,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } } } else { - log_disas(tb->tc_ptr, gen_code_size); + log_disas(tb->tc.ptr, gen_code_size); } qemu_log("\n"); qemu_log_flush(); @@ -1699,7 +1699,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) while (m_min <= m_max) { m = (m_min + m_max) >> 1; tb = tcg_ctx.tb_ctx.tbs[m]; - v = (uintptr_t)tb->tc_ptr; + v = (uintptr_t)tb->tc.ptr; if (v == tc_ptr) { return tb; } else if (tc_ptr < v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index dff9999bc6..a874bdd41f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2836,8 +2836,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_reg_alloc_start(s); - s->code_buf = tb->tc_ptr; - s->code_ptr = tb->tc_ptr; + s->code_buf = tb->tc.ptr; + s->code_ptr = tb->tc.ptr; #ifdef TCG_TARGET_NEED_LDST_LABELS s->ldst_labels = NULL; From patchwork Tue Oct 10 00:55:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115326 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3176758qgn; Mon, 9 Oct 2017 18:11:06 -0700 (PDT) X-Received: by 10.233.221.66 with SMTP id r63mr5712802qkf.79.1507597866167; Mon, 09 Oct 2017 18:11:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597866; cv=none; d=google.com; s=arc-20160816; b=w3ljqIBsSJehQKhoqDUonVCBrIrQ7ON5N4hSUK2mcoJq7QuBrEf6rk2Wy+bBkv9bHb /xBmRlPFJJ2D2Q8RXLMRyA/59ww7aOksAfNhX5ls3SVIN1Q8Ukj7e+CW2bEkat2PuhOR ISGmUq14D54Qf/2fRiHGzlvNI8dHhYUkrw4bLM0Y4uniWmarZ19BlytyWvgw9AzOD+8Q //kpxxuOlpsBdB0AfWR8qAdZzWSxteFYH9Gxi2IbNyyX0P4qTYN4S2ZFav5ixoNgTV25 uVVhRqaT95jqI8XwwOXsCScPT6bJl/ow38/hOEQ9fbUYa/Z7YIKd4sAf1+6wfJz41PNr BVsQ== ARC-Message-Signature: i=1; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:53 -0700 Message-Id: <20171010005600.28735-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 16/23] tci: move tci_regs to tcg_qemu_tb_exec's stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Acked-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tci.c | 552 +++++++++++++++++++++++++++++++------------------------------- 1 file changed, 279 insertions(+), 273 deletions(-) -- 2.13.6 diff --git a/tcg/tci.c b/tcg/tci.c index f39bfb95c0..63f2cd54ab 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -55,93 +55,95 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, tcg_target_ulong); #endif -static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; - -static tcg_target_ulong tci_read_reg(TCGReg index) +static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) { - tci_assert(index < ARRAY_SIZE(tci_reg)); - return tci_reg[index]; + tci_assert(index < TCG_TARGET_NB_REGS); + return regs[index]; } #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGReg index) +static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) { - return (int8_t)tci_read_reg(index); + return (int8_t)tci_read_reg(regs, index); } #endif #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGReg index) +static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { - return (int16_t)tci_read_reg(index); + return (int16_t)tci_read_reg(regs, index); } #endif #if TCG_TARGET_REG_BITS == 64 -static int32_t tci_read_reg32s(TCGReg index) +static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { - return (int32_t)tci_read_reg(index); + return (int32_t)tci_read_reg(regs, index); } #endif -static uint8_t tci_read_reg8(TCGReg index) +static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) { - return (uint8_t)tci_read_reg(index); + return (uint8_t)tci_read_reg(regs, index); } -static uint16_t tci_read_reg16(TCGReg index) +static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { - return (uint16_t)tci_read_reg(index); + return (uint16_t)tci_read_reg(regs, index); } -static uint32_t tci_read_reg32(TCGReg index) +static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { - return (uint32_t)tci_read_reg(index); + return (uint32_t)tci_read_reg(regs, index); } #if TCG_TARGET_REG_BITS == 64 -static uint64_t tci_read_reg64(TCGReg index) +static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { - return tci_read_reg(index); + return tci_read_reg(regs, index); } #endif -static void tci_write_reg(TCGReg index, tcg_target_ulong value) +static void +tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { - tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < TCG_TARGET_NB_REGS); tci_assert(index != TCG_AREG0); tci_assert(index != TCG_REG_CALL_STACK); - tci_reg[index] = value; + regs[index] = value; } #if TCG_TARGET_REG_BITS == 64 -static void tci_write_reg32s(TCGReg index, int32_t value) +static void +tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif -static void tci_write_reg8(TCGReg index, uint8_t value) +static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } -static void tci_write_reg32(TCGReg index, uint32_t value) +static void +tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #if TCG_TARGET_REG_BITS == 32 -static void tci_write_reg64(uint32_t high_index, uint32_t low_index, - uint64_t value) +static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, + uint32_t low_index, uint64_t value) { - tci_write_reg(low_index, value); - tci_write_reg(high_index, value >> 32); + tci_write_reg(regs, low_index, value); + tci_write_reg(regs, high_index, value >> 32); } #elif TCG_TARGET_REG_BITS == 64 -static void tci_write_reg64(TCGReg index, uint64_t value) +static void +tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif @@ -188,94 +190,97 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) #endif /* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong tci_read_r(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - tcg_target_ulong value = tci_read_reg(**tb_ptr); + tcg_target_ulong value = tci_read_reg(regs, **tb_ptr); *tb_ptr += 1; return value; } /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint8_t value = tci_read_reg8(**tb_ptr); + uint8_t value = tci_read_reg8(regs, **tb_ptr); *tb_ptr += 1; return value; } #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int8_t value = tci_read_reg8s(**tb_ptr); + int8_t value = tci_read_reg8s(regs, **tb_ptr); *tb_ptr += 1; return value; } #endif /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint16_t value = tci_read_reg16(**tb_ptr); + uint16_t value = tci_read_reg16(regs, **tb_ptr); *tb_ptr += 1; return value; } #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int16_t value = tci_read_reg16s(**tb_ptr); + int16_t value = tci_read_reg16s(regs, **tb_ptr); *tb_ptr += 1; return value; } #endif /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint32_t value = tci_read_reg32(**tb_ptr); + uint32_t value = tci_read_reg32(regs, **tb_ptr); *tb_ptr += 1; return value; } #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint32_t low = tci_read_r32(tb_ptr); - return tci_uint64(tci_read_r32(tb_ptr), low); + uint32_t low = tci_read_r32(regs, tb_ptr); + return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int32_t value = tci_read_reg32s(**tb_ptr); + int32_t value = tci_read_reg32s(regs, **tb_ptr); *tb_ptr += 1; return value; } /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint64_t value = tci_read_reg64(**tb_ptr); + uint64_t value = tci_read_reg64(regs, **tb_ptr); *tb_ptr += 1; return value; } #endif /* Read indexed register(s) with target address from bytecode. */ -static target_ulong tci_read_ulong(uint8_t **tb_ptr) +static target_ulong +tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - target_ulong taddr = tci_read_r(tb_ptr); + target_ulong taddr = tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr += (uint64_t)tci_read_r(tb_ptr) << 32; + taddr += (uint64_t)tci_read_r(regs, tb_ptr) << 32; #endif return taddr; } /* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r = **tb_ptr; @@ -283,13 +288,13 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) if (r == TCG_CONST) { value = tci_read_i(tb_ptr); } else { - value = tci_read_reg(r); + value = tci_read_reg(regs, r); } return value; } /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_ptr) { uint32_t value; TCGReg r = **tb_ptr; @@ -297,21 +302,21 @@ static uint32_t tci_read_ri32(uint8_t **tb_ptr) if (r == TCG_CONST) { value = tci_read_i32(tb_ptr); } else { - value = tci_read_reg32(r); + value = tci_read_reg32(regs, r); } return value; } #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint32_t low = tci_read_ri32(tb_ptr); - return tci_uint64(tci_read_ri32(tb_ptr), low); + uint32_t low = tci_read_ri32(regs, tb_ptr); + return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_ptr) { uint64_t value; TCGReg r = **tb_ptr; @@ -319,7 +324,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) if (r == TCG_CONST) { value = tci_read_i64(tb_ptr); } else { - value = tci_read_reg64(r); + value = tci_read_reg64(regs, r); } return value; } @@ -465,12 +470,13 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t ret = 0; - tci_reg[TCG_AREG0] = (tcg_target_ulong)env; - tci_reg[TCG_REG_CALL_STACK] = sp_value; + regs[TCG_AREG0] = (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] = sp_value; tci_assert(tb_ptr); for (;;) { @@ -503,27 +509,27 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) switch (opc) { case INDEX_op_call: - t0 = tci_read_ri(&tb_ptr); + t0 = tci_read_ri(regs, &tb_ptr); #if TCG_TARGET_REG_BITS == 32 - tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5), - tci_read_reg(TCG_REG_R6), - tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8), - tci_read_reg(TCG_REG_R9), - tci_read_reg(TCG_REG_R10)); - tci_write_reg(TCG_REG_R0, tmp64); - tci_write_reg(TCG_REG_R1, tmp64 >> 32); + tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10)); + tci_write_reg(regs, TCG_REG_R0, tmp64); + tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5)); - tci_write_reg(TCG_REG_R0, tmp64); + tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5)); + tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; case INDEX_op_br: @@ -533,46 +539,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) continue; case INDEX_op_setcond_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); + t1 = tci_read_r32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); condition = *tb_ptr++; - tci_write_reg32(t0, tci_compare32(t1, t2, condition)); + tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: t0 = *tb_ptr++; - tmp64 = tci_read_r64(&tb_ptr); - v64 = tci_read_ri64(&tb_ptr); + tmp64 = tci_read_r64(regs, &tb_ptr); + v64 = tci_read_ri64(regs, &tb_ptr); condition = *tb_ptr++; - tci_write_reg32(t0, tci_compare64(tmp64, v64, condition)); + tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)); break; #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); + t1 = tci_read_r64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); condition = *tb_ptr++; - tci_write_reg64(t0, tci_compare64(t1, t2, condition)); + tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - tci_write_reg32(t0, t1); + t1 = tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; case INDEX_op_movi_i32: t0 = *tb_ptr++; t1 = tci_read_i32(&tb_ptr); - tci_write_reg32(t0, t1); + tci_write_reg32(regs, t0, t1); break; /* Load/store operations (32 bit). */ case INDEX_op_ld8u_i32: t0 = *tb_ptr++; - t1 = tci_read_r(&tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -583,25 +589,25 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) break; case INDEX_op_ld_i32: t0 = *tb_ptr++; - t1 = tci_read_r(&tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: - t0 = tci_read_r8(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r8(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) = t0; break; case INDEX_op_st16_i32: - t0 = tci_read_r16(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r16(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) = t0; break; case INDEX_op_st_i32: - t0 = tci_read_r32(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_assert(t1 != sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) = t0; @@ -611,46 +617,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) case INDEX_op_add_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 + t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 - t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 * t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 / t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 % t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -660,71 +666,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) #endif case INDEX_op_and_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 & t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 | t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 ^ t2); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 ^ t2); break; /* Shift/rotate operations (32 bit). */ case INDEX_op_shl_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 << (t2 & 31)); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 >> (t2 & 31)); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, rol32(t1, t2 & 31)); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 = *tb_ptr++; - t1 = tci_read_ri32(&tb_ptr); - t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ror32(t1, t2 & 31)); + t1 = tci_read_ri32(regs, &tb_ptr); + t2 = tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - t2 = tci_read_r32(&tb_ptr); + t1 = tci_read_r32(regs, &tb_ptr); + t2 = tci_read_r32(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp32 = (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); break; #endif case INDEX_op_brcond_i32: - t0 = tci_read_r32(&tb_ptr); - t1 = tci_read_ri32(&tb_ptr); + t0 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_ri32(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -737,20 +743,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) case INDEX_op_add2_i32: t0 = *tb_ptr++; t1 = *tb_ptr++; - tmp64 = tci_read_r64(&tb_ptr); - tmp64 += tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 = tci_read_r64(regs, &tb_ptr); + tmp64 += tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_sub2_i32: t0 = *tb_ptr++; t1 = *tb_ptr++; - tmp64 = tci_read_r64(&tb_ptr); - tmp64 -= tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 = tci_read_r64(regs, &tb_ptr); + tmp64 -= tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 = tci_read_r64(&tb_ptr); - v64 = tci_read_ri64(&tb_ptr); + tmp64 = tci_read_r64(regs, &tb_ptr); + v64 = tci_read_ri64(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -762,86 +768,86 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) case INDEX_op_mulu2_i32: t0 = *tb_ptr++; t1 = *tb_ptr++; - t2 = tci_read_r32(&tb_ptr); - tmp64 = tci_read_r32(&tb_ptr); - tci_write_reg64(t1, t0, t2 * tmp64); + t2 = tci_read_r32(regs, &tb_ptr); + tmp64 = tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 = *tb_ptr++; - t1 = tci_read_r8s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 = tci_read_r8s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 = *tb_ptr++; - t1 = tci_read_r16s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 = tci_read_r16s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 = *tb_ptr++; - t1 = tci_read_r8(&tb_ptr); - tci_write_reg32(t0, t1); + t1 = tci_read_r8(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 = *tb_ptr++; - t1 = tci_read_r16(&tb_ptr); - tci_write_reg32(t0, t1); + t1 = tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 = *tb_ptr++; - t1 = tci_read_r16(&tb_ptr); - tci_write_reg32(t0, bswap16(t1)); + t1 = tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - tci_write_reg32(t0, bswap32(t1)); + t1 = tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - tci_write_reg32(t0, ~t1); + t1 = tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - tci_write_reg32(t0, -t1); + t1 = tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; case INDEX_op_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); - tci_write_reg64(t0, t1); + tci_write_reg64(regs, t0, t1); break; /* Load/store operations (64 bit). */ case INDEX_op_ld8u_i64: t0 = *tb_ptr++; - t1 = tci_read_r(&tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -850,43 +856,43 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) break; case INDEX_op_ld32u_i64: t0 = *tb_ptr++; - t1 = tci_read_r(&tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 = *tb_ptr++; - t1 = tci_read_r(&tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg32s(t0, *(int32_t *)(t1 + t2)); + tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 = *tb_ptr++; - t1 = tci_read_r(&tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); - tci_write_reg64(t0, *(uint64_t *)(t1 + t2)); + tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: - t0 = tci_read_r8(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r8(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) = t0; break; case INDEX_op_st16_i64: - t0 = tci_read_r16(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r16(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) = t0; break; case INDEX_op_st32_i64: - t0 = tci_read_r32(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) = t0; break; case INDEX_op_st_i64: - t0 = tci_read_r64(&tb_ptr); - t1 = tci_read_r(&tb_ptr); + t0 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); tci_assert(t1 != sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) = t0; @@ -896,21 +902,21 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) case INDEX_op_add_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 + t2); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 - t2); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 * t2); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -927,71 +933,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) #endif case INDEX_op_and_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 & t2); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 | t2); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 ^ t2); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 ^ t2); break; /* Shift/rotate operations (64 bit). */ case INDEX_op_shl_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 << (t2 & 63)); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 >> (t2 & 63)); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, rol64(t1, t2 & 63)); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 = *tb_ptr++; - t1 = tci_read_ri64(&tb_ptr); - t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ror64(t1, t2 & 63)); + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(&tb_ptr); - t2 = tci_read_r64(&tb_ptr); + t1 = tci_read_r64(regs, &tb_ptr); + t2 = tci_read_r64(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp64 = (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); break; #endif case INDEX_op_brcond_i64: - t0 = tci_read_r64(&tb_ptr); - t1 = tci_read_ri64(&tb_ptr); + t0 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_ri64(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -1003,29 +1009,29 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 = *tb_ptr++; - t1 = tci_read_r8(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r8(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 = *tb_ptr++; - t1 = tci_read_r8s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r8s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 = *tb_ptr++; - t1 = tci_read_r16s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r16s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 = *tb_ptr++; - t1 = tci_read_r16(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1033,50 +1039,50 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) #endif case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r32s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: #endif case INDEX_op_extu_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - tci_write_reg64(t0, t1); + t1 = tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 = *tb_ptr++; - t1 = tci_read_r16(&tb_ptr); - tci_write_reg64(t0, bswap16(t1)); + t1 = tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32(&tb_ptr); - tci_write_reg64(t0, bswap32(t1)); + t1 = tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(&tb_ptr); - tci_write_reg64(t0, bswap64(t1)); + t1 = tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(&tb_ptr); - tci_write_reg64(t0, ~t1); + t1 = tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(&tb_ptr); - tci_write_reg64(t0, -t1); + t1 = tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS == 64 */ @@ -1097,7 +1103,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) continue; case INDEX_op_qemu_ld_i32: t0 = *tb_ptr++; - taddr = tci_read_ulong(&tb_ptr); + taddr = tci_read_ulong(regs, &tb_ptr); oi = tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1127,14 +1133,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp32); + tci_write_reg(regs, t0, tmp32); break; case INDEX_op_qemu_ld_i64: t0 = *tb_ptr++; if (TCG_TARGET_REG_BITS == 32) { t1 = *tb_ptr++; } - taddr = tci_read_ulong(&tb_ptr); + taddr = tci_read_ulong(regs, &tb_ptr); oi = tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1176,14 +1182,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp64); + tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS == 32) { - tci_write_reg(t1, tmp64 >> 32); + tci_write_reg(regs, t1, tmp64 >> 32); } break; case INDEX_op_qemu_st_i32: - t0 = tci_read_r(&tb_ptr); - taddr = tci_read_ulong(&tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); + taddr = tci_read_ulong(regs, &tb_ptr); oi = tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: @@ -1206,8 +1212,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) } break; case INDEX_op_qemu_st_i64: - tmp64 = tci_read_r64(&tb_ptr); - taddr = tci_read_ulong(&tb_ptr); + tmp64 = tci_read_r64(regs, &tb_ptr); + taddr = tci_read_ulong(regs, &tb_ptr); oi = tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: From patchwork Tue Oct 10 00:55:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115314 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3168983qgn; Mon, 9 Oct 2017 18:01:27 -0700 (PDT) X-Received: by 10.200.33.186 with SMTP id 55mr16986623qty.300.1507597287234; Mon, 09 Oct 2017 18:01:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597287; cv=none; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:54 -0700 Message-Id: <20171010005600.28735-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL 17/23] tcg: take .helpers out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. The hash table becomes read-only after it is filled in, so we can save space by keeping just a global pointer to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 -- tcg/tcg.c | 10 +++++----- 2 files changed, 5 insertions(+), 7 deletions(-) -- 2.13.6 diff --git a/tcg/tcg.h b/tcg/tcg.h index 25662c36d4..b2d42e3136 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,8 +656,6 @@ struct TCGContext { tcg_insn_unit *code_ptr; - GHashTable *helpers; - #ifdef CONFIG_PROFILER /* profiling info */ int64_t tb_count1; diff --git a/tcg/tcg.c b/tcg/tcg.c index a874bdd41f..ee60798438 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -318,6 +318,7 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] = { #include "exec/helper-tcg.h" }; +static GHashTable *helper_table; static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; static void process_op_defs(TCGContext *s); @@ -328,7 +329,6 @@ void tcg_context_init(TCGContext *s) TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; - GHashTable *helper_table; memset(s, 0, sizeof(*s)); s->nb_globals = 0; @@ -356,7 +356,7 @@ void tcg_context_init(TCGContext *s) /* Register helpers. */ /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - s->helpers = helper_table = g_hash_table_new(NULL, NULL); + helper_table = g_hash_table_new(NULL, NULL); for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, @@ -982,7 +982,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, unsigned sizemask, flags; TCGHelperInfo *info; - info = g_hash_table_lookup(s->helpers, (gpointer)func); + info = g_hash_table_lookup(helper_table, (gpointer)func); flags = info->flags; sizemask = info->sizemask; @@ -1211,8 +1211,8 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) { const char *ret = NULL; - if (s->helpers) { - TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val); + if (helper_table) { + TCGHelperInfo *info = g_hash_table_lookup(helper_table, (gpointer)val); if (info) { ret = info->name; } From patchwork Tue Oct 10 00:55:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115320 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3173064qgn; Mon, 9 Oct 2017 18:06:13 -0700 (PDT) X-Received: by 10.233.221.133 with SMTP id r127mr5674554qkf.205.1507597573610; Mon, 09 Oct 2017 18:06:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597573; cv=none; d=google.com; s=arc-20160816; b=E78QSajtioYVoxYTw0FoABzyHOgHbWI3zOK//25wsRvj8umFNlhMIARTaG8AMipHTC 6L9BjxctkSkicIr+xNe7XUzqZCMWRcKi/S3O3EUJntwkXvRjItUwsBJ8nuhYv3dEIXXO +rD7q2R/CQZdFER+1C418awRzFCRRshAx2ZilGYu5aNuKTAISWsb6EeIJ3Nx0YEMiV8r X75R475jHtLpLhUyrqkxvpCCNgjgb7tmL6UmDwTE6nbWYa7HP+/4K9jM5fp1bBxX/RFw AaKIAtVzFgvc5CkRDteJGwIdtaraYFjCoBpaFso8yErto578Wcf8xnTVdCJl0W8puMyh ulxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ZVhJYyvotqWfO3C5NrogLABsiBUP9yTOkLR3rrD+pnI=; b=Z5EctCbC+GoGO2O6OCM5AUz1HZ670wmbcOOAtEK+A5c1c//UA8cuVZhR4SsUlLNFRS R4grdBvuxUlw+roJyHgtszZhlf3uYeVXCo5OecnduTIjmPcwWi4/tSnBosIdeUypm+q/ 4BRBx+t6Wi71MaA3Q9aH/libzSRMp16q9/XTUirlKlzM5rbqlDUPqad4N+EQDV0ePyPZ UNpdsNnXzl+NPX2XJAKYqofK4aWVcwXOZPOQ3EeNC5aq4kEVp+WisGTVC2Y/GU/+8Qar FH1OxltVMRnt6O0IyfeHCwcK/MCgDMYqFNxXpqNw3k34gXq/+QmsBhX4HF8+K9DjHHZ7 fOYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V2rKMiNr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:55 -0700 Message-Id: <20171010005600.28735-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 18/23] tcg: allocate optimizer temps with tcg_malloc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. While at it, also allocate temps_used directly as a bitmap of the required size, instead of using a bitmap of TCG_MAX_TEMPS via TCGTempSet. Performance-wise we lose about 1.12% in a translation-heavy workload such as booting+shutting down debian-arm: Performance counter stats for 'taskset -c 0 arm-softmmu/qemu-system-arm \ -machine type=virt -nographic -smp 1 -m 4096 \ -netdev user,id=unet,hostfwd=tcp::2222-:22 \ -device virtio-net-device,netdev=unet \ -drive file=die-on-boot.qcow2,id=myblock,index=0,if=none \ -device virtio-blk-device,drive=myblock \ -kernel kernel.img -append console=ttyAMA0 root=/dev/vda1 \ -name arm,debug-threads=on -smp 1' (10 runs): exec time (s) Relative slowdown wrt original (%) --------------------------------------------------------------- original 20.213321616 0. tcg_malloc 20.441130078 1.1270214 TCGContext 20.477846517 1.3086662 g_malloc 20.780527895 2.8061013 The other two alternatives shown in the table are: - TCGContext: embed temps[TCG_MAX_TEMPS] and TCGTempSet used_temps in TCGContext. This is simple enough but it isn't faster than using tcg_malloc; moreover, it wastes memory. - g_malloc: allocate/deallocate both temps and used_temps every time tcg_optimize is executed. Suggested-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/optimize.c | 306 ++++++++++++++++++++++++++++++--------------------------- 1 file changed, 161 insertions(+), 145 deletions(-) -- 2.13.6 diff --git a/tcg/optimize.c b/tcg/optimize.c index adfc56ce62..ce422e9ff0 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -40,21 +40,18 @@ struct tcg_temp_info { tcg_target_ulong mask; }; -static struct tcg_temp_info temps[TCG_MAX_TEMPS]; -static TCGTempSet temps_used; - -static inline bool temp_is_const(TCGArg arg) +static inline bool temp_is_const(const struct tcg_temp_info *temps, TCGArg arg) { return temps[arg].is_const; } -static inline bool temp_is_copy(TCGArg arg) +static inline bool temp_is_copy(const struct tcg_temp_info *temps, TCGArg arg) { return temps[arg].next_copy != arg; } /* Reset TEMP's state, possibly removing the temp for the list of copies. */ -static void reset_temp(TCGArg temp) +static void reset_temp(struct tcg_temp_info *temps, TCGArg temp) { temps[temps[temp].next_copy].prev_copy = temps[temp].prev_copy; temps[temps[temp].prev_copy].next_copy = temps[temp].next_copy; @@ -64,21 +61,16 @@ static void reset_temp(TCGArg temp) temps[temp].mask = -1; } -/* Reset all temporaries, given that there are NB_TEMPS of them. */ -static void reset_all_temps(int nb_temps) -{ - bitmap_zero(temps_used.l, nb_temps); -} - /* Initialize and activate a temporary. */ -static void init_temp_info(TCGArg temp) +static void init_temp_info(struct tcg_temp_info *temps, + unsigned long *temps_used, TCGArg temp) { - if (!test_bit(temp, temps_used.l)) { + if (!test_bit(temp, temps_used)) { temps[temp].next_copy = temp; temps[temp].prev_copy = temp; temps[temp].is_const = false; temps[temp].mask = -1; - set_bit(temp, temps_used.l); + set_bit(temp, temps_used); } } @@ -116,7 +108,8 @@ static TCGOpcode op_to_movi(TCGOpcode op) } } -static TCGArg find_better_copy(TCGContext *s, TCGArg temp) +static TCGArg find_better_copy(TCGContext *s, const struct tcg_temp_info *temps, + TCGArg temp) { TCGArg i; @@ -145,7 +138,8 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg temp) return temp; } -static bool temps_are_copies(TCGArg arg1, TCGArg arg2) +static bool temps_are_copies(const struct tcg_temp_info *temps, TCGArg arg1, + TCGArg arg2) { TCGArg i; @@ -153,7 +147,7 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return true; } - if (!temp_is_copy(arg1) || !temp_is_copy(arg2)) { + if (!temp_is_copy(temps, arg1) || !temp_is_copy(temps, arg2)) { return false; } @@ -166,15 +160,15 @@ static bool temps_are_copies(TCGArg arg1, TCGArg arg2) return false; } -static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg val) +static void tcg_opt_gen_movi(TCGContext *s, struct tcg_temp_info *temps, + TCGOp *op, TCGArg *args, TCGArg dst, TCGArg val) { TCGOpcode new_op = op_to_movi(op->opc); tcg_target_ulong mask; op->opc = new_op; - reset_temp(dst); + reset_temp(temps, dst); temps[dst].is_const = true; temps[dst].val = val; mask = val; @@ -188,10 +182,10 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg *args, args[1] = val; } -static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args, - TCGArg dst, TCGArg src) +static void tcg_opt_gen_mov(TCGContext *s, struct tcg_temp_info *temps, + TCGOp *op, TCGArg *args, TCGArg dst, TCGArg src) { - if (temps_are_copies(dst, src)) { + if (temps_are_copies(temps, dst, src)) { tcg_op_remove(s, op); return; } @@ -201,7 +195,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg *args, op->opc = new_op; - reset_temp(dst); + reset_temp(temps, dst); mask = temps[src].mask; if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) { /* High bits of the destination are now garbage. */ @@ -463,10 +457,11 @@ static bool do_constant_folding_cond_eq(TCGCond c) /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, - TCGArg y, TCGCond c) +static TCGArg +do_constant_folding_cond(const struct tcg_temp_info *temps, TCGOpcode op, + TCGArg x, TCGArg y, TCGCond c) { - if (temp_is_const(x) && temp_is_const(y)) { + if (temp_is_const(temps, x) && temp_is_const(temps, y)) { switch (op_bits(op)) { case 32: return do_constant_folding_cond_32(temps[x].val, temps[y].val, c); @@ -475,9 +470,9 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, default: tcg_abort(); } - } else if (temps_are_copies(x, y)) { + } else if (temps_are_copies(temps, x, y)) { return do_constant_folding_cond_eq(c); - } else if (temp_is_const(y) && temps[y].val == 0) { + } else if (temp_is_const(temps, y) && temps[y].val == 0) { switch (c) { case TCG_COND_LTU: return 0; @@ -492,15 +487,17 @@ static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x, /* Return 2 if the condition can't be simplified, and the result of the condition (0 or 1) if it can */ -static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) +static TCGArg +do_constant_folding_cond2(const struct tcg_temp_info *temps, TCGArg *p1, + TCGArg *p2, TCGCond c) { TCGArg al = p1[0], ah = p1[1]; TCGArg bl = p2[0], bh = p2[1]; - if (temp_is_const(bl) && temp_is_const(bh)) { + if (temp_is_const(temps, bl) && temp_is_const(temps, bh)) { uint64_t b = ((uint64_t)temps[bh].val << 32) | (uint32_t)temps[bl].val; - if (temp_is_const(al) && temp_is_const(ah)) { + if (temp_is_const(temps, al) && temp_is_const(temps, ah)) { uint64_t a; a = ((uint64_t)temps[ah].val << 32) | (uint32_t)temps[al].val; return do_constant_folding_cond_64(a, b, c); @@ -516,18 +513,19 @@ static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c) } } } - if (temps_are_copies(al, bl) && temps_are_copies(ah, bh)) { + if (temps_are_copies(temps, al, bl) && temps_are_copies(temps, ah, bh)) { return do_constant_folding_cond_eq(c); } return 2; } -static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) +static bool swap_commutative(const struct tcg_temp_info *temps, TCGArg dest, + TCGArg *p1, TCGArg *p2) { TCGArg a1 = *p1, a2 = *p2; int sum = 0; - sum += temp_is_const(a1); - sum -= temp_is_const(a2); + sum += temp_is_const(temps, a1); + sum -= temp_is_const(temps, a2); /* Prefer the constant in second argument, and then the form op a, a, b, which is better handled on non-RISC hosts. */ @@ -539,13 +537,14 @@ static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2) return false; } -static bool swap_commutative2(TCGArg *p1, TCGArg *p2) +static bool swap_commutative2(const struct tcg_temp_info *temps, TCGArg *p1, + TCGArg *p2) { int sum = 0; - sum += temp_is_const(p1[0]); - sum += temp_is_const(p1[1]); - sum -= temp_is_const(p2[0]); - sum -= temp_is_const(p2[1]); + sum += temp_is_const(temps, p1[0]); + sum += temp_is_const(temps, p1[1]); + sum -= temp_is_const(temps, p2[0]); + sum -= temp_is_const(temps, p2[1]); if (sum > 0) { TCGArg t; t = p1[0], p1[0] = p2[0], p2[0] = t; @@ -558,6 +557,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2) /* Propagate constants and copies, fold constant expressions. */ void tcg_optimize(TCGContext *s) { + struct tcg_temp_info *temps; + unsigned long *temps_used; int oi, oi_next, nb_temps, nb_globals; TCGArg *prev_mb_args = NULL; @@ -568,7 +569,9 @@ void tcg_optimize(TCGContext *s) nb_temps = s->nb_temps; nb_globals = s->nb_globals; - reset_all_temps(nb_temps); + temps = tcg_malloc(nb_temps * sizeof(*temps)); + temps_used = tcg_malloc(BITS_TO_LONGS(nb_temps) * sizeof(*temps_used)); + bitmap_zero(temps_used, nb_temps); for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) { tcg_target_ulong mask, partmask, affected; @@ -590,21 +593,21 @@ void tcg_optimize(TCGContext *s) for (i = 0; i < nb_oargs + nb_iargs; i++) { tmp = args[i]; if (tmp != TCG_CALL_DUMMY_ARG) { - init_temp_info(tmp); + init_temp_info(temps, temps_used, tmp); } } } else { nb_oargs = def->nb_oargs; nb_iargs = def->nb_iargs; for (i = 0; i < nb_oargs + nb_iargs; i++) { - init_temp_info(args[i]); + init_temp_info(temps, temps_used, args[i]); } } /* Do copy propagation */ for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - if (temp_is_copy(args[i])) { - args[i] = find_better_copy(s, args[i]); + if (temp_is_copy(temps, args[i])) { + args[i] = find_better_copy(s, temps, args[i]); } } @@ -620,44 +623,44 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(nor): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - swap_commutative(args[0], &args[1], &args[2]); + swap_commutative(temps, args[0], &args[1], &args[2]); break; CASE_OP_32_64(brcond): - if (swap_commutative(-1, &args[0], &args[1])) { + if (swap_commutative(temps, -1, &args[0], &args[1])) { args[2] = tcg_swap_cond(args[2]); } break; CASE_OP_32_64(setcond): - if (swap_commutative(args[0], &args[1], &args[2])) { + if (swap_commutative(temps, args[0], &args[1], &args[2])) { args[3] = tcg_swap_cond(args[3]); } break; CASE_OP_32_64(movcond): - if (swap_commutative(-1, &args[1], &args[2])) { + if (swap_commutative(temps, -1, &args[1], &args[2])) { args[5] = tcg_swap_cond(args[5]); } /* For movcond, we canonicalize the "false" input reg to match the destination reg so that the tcg backend can implement a "move if true" operation. */ - if (swap_commutative(args[0], &args[4], &args[3])) { + if (swap_commutative(temps, args[0], &args[4], &args[3])) { args[5] = tcg_invert_cond(args[5]); } break; CASE_OP_32_64(add2): - swap_commutative(args[0], &args[2], &args[4]); - swap_commutative(args[1], &args[3], &args[5]); + swap_commutative(temps, args[0], &args[2], &args[4]); + swap_commutative(temps, args[1], &args[3], &args[5]); break; CASE_OP_32_64(mulu2): CASE_OP_32_64(muls2): - swap_commutative(args[0], &args[2], &args[3]); + swap_commutative(temps, args[0], &args[2], &args[3]); break; case INDEX_op_brcond2_i32: - if (swap_commutative2(&args[0], &args[2])) { + if (swap_commutative2(temps, &args[0], &args[2])) { args[4] = tcg_swap_cond(args[4]); } break; case INDEX_op_setcond2_i32: - if (swap_commutative2(&args[1], &args[3])) { + if (swap_commutative2(temps, &args[1], &args[3])) { args[5] = tcg_swap_cond(args[5]); } break; @@ -673,8 +676,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(sar): CASE_OP_32_64(rotl): CASE_OP_32_64(rotr): - if (temp_is_const(args[1]) && temps[args[1]].val == 0) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temp_is_const(temps, args[1]) && temps[args[1]].val == 0) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -683,7 +686,7 @@ void tcg_optimize(TCGContext *s) TCGOpcode neg_op; bool have_neg; - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { /* Proceed with possible constant folding. */ break; } @@ -697,9 +700,9 @@ void tcg_optimize(TCGContext *s) if (!have_neg) { break; } - if (temp_is_const(args[1]) && temps[args[1]].val == 0) { + if (temp_is_const(temps, args[1]) && temps[args[1]].val == 0) { op->opc = neg_op; - reset_temp(args[0]); + reset_temp(temps, args[0]); args[1] = args[2]; continue; } @@ -707,30 +710,30 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(xor): CASE_OP_32_64(nand): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val == -1) { + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val == -1) { i = 1; goto try_not; } break; CASE_OP_32_64(nor): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val == 0) { + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val == 0) { i = 1; goto try_not; } break; CASE_OP_32_64(andc): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val == -1) { + if (!temp_is_const(temps, args[2]) + && temp_is_const(temps, args[1]) && temps[args[1]].val == -1) { i = 2; goto try_not; } break; CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[2]) - && temp_is_const(args[1]) && temps[args[1]].val == 0) { + if (!temp_is_const(temps, args[2]) + && temp_is_const(temps, args[1]) && temps[args[1]].val == 0) { i = 2; goto try_not; } @@ -751,7 +754,7 @@ void tcg_optimize(TCGContext *s) break; } op->opc = not_op; - reset_temp(args[0]); + reset_temp(temps, args[0]); args[1] = args[i]; continue; } @@ -771,18 +774,18 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(or): CASE_OP_32_64(xor): CASE_OP_32_64(andc): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val == 0) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val == 0) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; CASE_OP_32_64(and): CASE_OP_32_64(orc): CASE_OP_32_64(eqv): - if (!temp_is_const(args[1]) - && temp_is_const(args[2]) && temps[args[2]].val == -1) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (!temp_is_const(temps, args[1]) + && temp_is_const(temps, args[2]) && temps[args[2]].val == -1) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; @@ -819,7 +822,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(and): mask = temps[args[2]].mask; - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { and_const: affected = temps[args[1]].mask & ~mask; } @@ -838,7 +841,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): /* Known-zeros does not imply known-ones. Therefore unless args[2] is constant, we can't infer anything from it. */ - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { mask = ~temps[args[2]].mask; goto and_const; } @@ -847,26 +850,26 @@ void tcg_optimize(TCGContext *s) break; case INDEX_op_sar_i32: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp = temps[args[2]].val & 31; mask = (int32_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_sar_i64: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp = temps[args[2]].val & 63; mask = (int64_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_shr_i32: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp = temps[args[2]].val & 31; mask = (uint32_t)temps[args[1]].mask >> tmp; } break; case INDEX_op_shr_i64: - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp = temps[args[2]].val & 63; mask = (uint64_t)temps[args[1]].mask >> tmp; } @@ -880,7 +883,7 @@ void tcg_optimize(TCGContext *s) break; CASE_OP_32_64(shl): - if (temp_is_const(args[2])) { + if (temp_is_const(temps, args[2])) { tmp = temps[args[2]].val & (TCG_TARGET_REG_BITS - 1); mask = temps[args[1]].mask << tmp; } @@ -976,12 +979,12 @@ void tcg_optimize(TCGContext *s) if (partmask == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_movi(s, op, args, args[0], 0); + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } if (affected == 0) { tcg_debug_assert(nb_oargs == 1); - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } @@ -991,8 +994,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(mul): CASE_OP_32_64(muluh): CASE_OP_32_64(mulsh): - if ((temp_is_const(args[2]) && temps[args[2]].val == 0)) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if ((temp_is_const(temps, args[2]) && temps[args[2]].val == 0)) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -1004,8 +1007,8 @@ void tcg_optimize(TCGContext *s) switch (opc) { CASE_OP_32_64(or): CASE_OP_32_64(and): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + if (temps_are_copies(temps, args[1], args[2])) { + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); continue; } break; @@ -1018,8 +1021,8 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(andc): CASE_OP_32_64(sub): CASE_OP_32_64(xor): - if (temps_are_copies(args[1], args[2])) { - tcg_opt_gen_movi(s, op, args, args[0], 0); + if (temps_are_copies(temps, args[1], args[2])) { + tcg_opt_gen_movi(s, temps, op, args, args[0], 0); continue; } break; @@ -1032,10 +1035,10 @@ void tcg_optimize(TCGContext *s) allocator where needed and possible. Also detect copies. */ switch (opc) { CASE_OP_32_64(mov): - tcg_opt_gen_mov(s, op, args, args[0], args[1]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[1]); break; CASE_OP_32_64(movi): - tcg_opt_gen_movi(s, op, args, args[0], args[1]); + tcg_opt_gen_movi(s, temps, op, args, args[0], args[1]); break; CASE_OP_32_64(not): @@ -1051,9 +1054,9 @@ void tcg_optimize(TCGContext *s) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp = do_constant_folding(opc, temps[args[1]].val, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; @@ -1080,66 +1083,70 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(divu): CASE_OP_32_64(rem): CASE_OP_32_64(remu): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { + if (temp_is_const(temps, args[1]) && + temp_is_const(temps, args[2])) { tmp = do_constant_folding(opc, temps[args[1]].val, temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; CASE_OP_32_64(clz): CASE_OP_32_64(ctz): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { TCGArg v = temps[args[1]].val; if (v != 0) { tmp = do_constant_folding(opc, v, 0); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); } else { - tcg_opt_gen_mov(s, op, args, args[0], args[2]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[2]); } break; } goto do_default; CASE_OP_32_64(deposit): - if (temp_is_const(args[1]) && temp_is_const(args[2])) { + if (temp_is_const(temps, args[1]) && + temp_is_const(temps, args[2])) { tmp = deposit64(temps[args[1]].val, args[3], args[4], temps[args[2]].val); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; CASE_OP_32_64(extract): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp = extract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; CASE_OP_32_64(sextract): - if (temp_is_const(args[1])) { + if (temp_is_const(temps, args[1])) { tmp = sextract64(temps[args[1]].val, args[2], args[3]); - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; CASE_OP_32_64(setcond): - tmp = do_constant_folding_cond(opc, args[1], args[2], args[3]); + tmp = do_constant_folding_cond(temps, opc, args[1], args[2], + args[3]); if (tmp != 2) { - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); break; } goto do_default; CASE_OP_32_64(brcond): - tmp = do_constant_folding_cond(opc, args[0], args[1], args[2]); + tmp = do_constant_folding_cond(temps, opc, args[0], args[1], + args[2]); if (tmp != 2) { if (tmp) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc = INDEX_op_br; args[0] = args[3]; } else { @@ -1150,12 +1157,14 @@ void tcg_optimize(TCGContext *s) goto do_default; CASE_OP_32_64(movcond): - tmp = do_constant_folding_cond(opc, args[1], args[2], args[5]); + tmp = do_constant_folding_cond(temps, opc, args[1], args[2], + args[5]); if (tmp != 2) { - tcg_opt_gen_mov(s, op, args, args[0], args[4-tmp]); + tcg_opt_gen_mov(s, temps, op, args, args[0], args[4 - tmp]); break; } - if (temp_is_const(args[3]) && temp_is_const(args[4])) { + if (temp_is_const(temps, args[3]) && + temp_is_const(temps, args[4])) { tcg_target_ulong tv = temps[args[3]].val; tcg_target_ulong fv = temps[args[4]].val; TCGCond cond = args[5]; @@ -1174,8 +1183,10 @@ void tcg_optimize(TCGContext *s) case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3]) - && temp_is_const(args[4]) && temp_is_const(args[5])) { + if (temp_is_const(temps, args[2]) && + temp_is_const(temps, args[3]) && + temp_is_const(temps, args[4]) && + temp_is_const(temps, args[5])) { uint32_t al = temps[args[2]].val; uint32_t ah = temps[args[3]].val; uint32_t bl = temps[args[4]].val; @@ -1194,8 +1205,8 @@ void tcg_optimize(TCGContext *s) rl = args[0]; rh = args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)a); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(a >> 32)); + tcg_opt_gen_movi(s, temps, op, args, rl, (int32_t)a); + tcg_opt_gen_movi(s, temps, op2, args2, rh, (int32_t)(a >> 32)); /* We've done all we need to do with the movi. Skip it. */ oi_next = op2->next; @@ -1204,7 +1215,8 @@ void tcg_optimize(TCGContext *s) goto do_default; case INDEX_op_mulu2_i32: - if (temp_is_const(args[2]) && temp_is_const(args[3])) { + if (temp_is_const(temps, args[2]) && + temp_is_const(temps, args[3])) { uint32_t a = temps[args[2]].val; uint32_t b = temps[args[3]].val; uint64_t r = (uint64_t)a * b; @@ -1214,8 +1226,8 @@ void tcg_optimize(TCGContext *s) rl = args[0]; rh = args[1]; - tcg_opt_gen_movi(s, op, args, rl, (int32_t)r); - tcg_opt_gen_movi(s, op2, args2, rh, (int32_t)(r >> 32)); + tcg_opt_gen_movi(s, temps, op, args, rl, (int32_t)r); + tcg_opt_gen_movi(s, temps, op2, args2, rh, (int32_t)(r >> 32)); /* We've done all we need to do with the movi. Skip it. */ oi_next = op2->next; @@ -1224,11 +1236,11 @@ void tcg_optimize(TCGContext *s) goto do_default; case INDEX_op_brcond2_i32: - tmp = do_constant_folding_cond2(&args[0], &args[2], args[4]); + tmp = do_constant_folding_cond2(temps, &args[0], &args[2], args[4]); if (tmp != 2) { if (tmp) { do_brcond_true: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc = INDEX_op_br; args[0] = args[5]; } else { @@ -1236,12 +1248,14 @@ void tcg_optimize(TCGContext *s) tcg_op_remove(s, op); } } else if ((args[4] == TCG_COND_LT || args[4] == TCG_COND_GE) - && temp_is_const(args[2]) && temps[args[2]].val == 0 - && temp_is_const(args[3]) && temps[args[3]].val == 0) { + && temp_is_const(temps, args[2]) + && temps[args[2]].val == 0 + && temp_is_const(temps, args[3]) + && temps[args[3]].val == 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_brcond_high: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc = INDEX_op_brcond_i32; args[0] = args[1]; args[1] = args[3]; @@ -1250,14 +1264,14 @@ void tcg_optimize(TCGContext *s) } else if (args[4] == TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_brcond_i32, args[0], args[2], TCG_COND_EQ); if (tmp == 0) { goto do_brcond_false; } else if (tmp == 1) { goto do_brcond_high; } - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_brcond_i32, args[1], args[3], TCG_COND_EQ); if (tmp == 0) { goto do_brcond_false; @@ -1265,7 +1279,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_brcond_low: - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); op->opc = INDEX_op_brcond_i32; args[1] = args[2]; args[2] = args[4]; @@ -1273,14 +1287,14 @@ void tcg_optimize(TCGContext *s) } else if (args[4] == TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_brcond_i32, args[0], args[2], TCG_COND_NE); if (tmp == 0) { goto do_brcond_high; } else if (tmp == 1) { goto do_brcond_true; } - tmp = do_constant_folding_cond(INDEX_op_brcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_brcond_i32, args[1], args[3], TCG_COND_NE); if (tmp == 0) { goto do_brcond_low; @@ -1294,17 +1308,19 @@ void tcg_optimize(TCGContext *s) break; case INDEX_op_setcond2_i32: - tmp = do_constant_folding_cond2(&args[1], &args[3], args[5]); + tmp = do_constant_folding_cond2(temps, &args[1], &args[3], args[5]); if (tmp != 2) { do_setcond_const: - tcg_opt_gen_movi(s, op, args, args[0], tmp); + tcg_opt_gen_movi(s, temps, op, args, args[0], tmp); } else if ((args[5] == TCG_COND_LT || args[5] == TCG_COND_GE) - && temp_is_const(args[3]) && temps[args[3]].val == 0 - && temp_is_const(args[4]) && temps[args[4]].val == 0) { + && temp_is_const(temps, args[3]) + && temps[args[3]].val == 0 + && temp_is_const(temps, args[4]) + && temps[args[4]].val == 0) { /* Simplify LT/GE comparisons vs zero to a single compare vs the high word of the input. */ do_setcond_high: - reset_temp(args[0]); + reset_temp(temps, args[0]); temps[args[0]].mask = 1; op->opc = INDEX_op_setcond_i32; args[1] = args[2]; @@ -1313,14 +1329,14 @@ void tcg_optimize(TCGContext *s) } else if (args[5] == TCG_COND_EQ) { /* Simplify EQ comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_setcond_i32, args[1], args[3], TCG_COND_EQ); if (tmp == 0) { goto do_setcond_const; } else if (tmp == 1) { goto do_setcond_high; } - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_setcond_i32, args[2], args[4], TCG_COND_EQ); if (tmp == 0) { goto do_setcond_high; @@ -1328,7 +1344,7 @@ void tcg_optimize(TCGContext *s) goto do_default; } do_setcond_low: - reset_temp(args[0]); + reset_temp(temps, args[0]); temps[args[0]].mask = 1; op->opc = INDEX_op_setcond_i32; args[2] = args[3]; @@ -1336,14 +1352,14 @@ void tcg_optimize(TCGContext *s) } else if (args[5] == TCG_COND_NE) { /* Simplify NE comparisons where one of the pairs can be simplified. */ - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_setcond_i32, args[1], args[3], TCG_COND_NE); if (tmp == 0) { goto do_setcond_high; } else if (tmp == 1) { goto do_setcond_const; } - tmp = do_constant_folding_cond(INDEX_op_setcond_i32, + tmp = do_constant_folding_cond(temps, INDEX_op_setcond_i32, args[2], args[4], TCG_COND_NE); if (tmp == 0) { goto do_setcond_low; @@ -1360,8 +1376,8 @@ void tcg_optimize(TCGContext *s) if (!(args[nb_oargs + nb_iargs + 1] & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) { for (i = 0; i < nb_globals; i++) { - if (test_bit(i, temps_used.l)) { - reset_temp(i); + if (test_bit(i, temps_used)) { + reset_temp(temps, i); } } } @@ -1375,11 +1391,11 @@ void tcg_optimize(TCGContext *s) block, otherwise we only trash the output args. "mask" is the non-zero bits mask for the first output arg. */ if (def->flags & TCG_OPF_BB_END) { - reset_all_temps(nb_temps); + bitmap_zero(temps_used, nb_temps); } else { do_reset_output: for (i = 0; i < nb_oargs; i++) { - reset_temp(args[i]); + reset_temp(temps, args[i]); /* Save the corresponding known-zero bits mask for the first output argument (only one supported so far). */ if (i == 0) { From patchwork Tue Oct 10 00:55:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115324 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3175473qgn; Mon, 9 Oct 2017 18:09:24 -0700 (PDT) X-Received: by 10.55.150.69 with SMTP id y66mr12118770qkd.28.1507597764035; Mon, 09 Oct 2017 18:09:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597764; cv=none; d=google.com; s=arc-20160816; b=PQy0BEr3OQPlwEZSjFEjGCA5o4s+OhwgEz4DV0+kKfQEgUYn0d0fa20E6HAd7XhEw4 e9av3lHIGySuiKR8g43dTvoUy1gFoe1BS45CTLpzP6T2ssos7m7kH2cq/ev/WBMyvVbV H3fzUCHXSx+HezhVfmAghxLgHIKRYKR8Ln6JaD0tNplYhJMdabLJfl1IyN+/K4HlBOBa jlGYqF59GremqveHAyf78bScdk/ZCJFHGl6rS4N9ru3DfvLVCSJ/CXJZY15jzl7YFtBK MW/OpL82innK7IpfLqbRjvU/8vtjQli6gpAWsiOFvHDkOn43yEeofqB3BIW9GrjfbX20 QjDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=LEPSQBFcHMdI/3CokXPsBH3v71WBctmmqRbtmcTyRnc=; b=lnJEtVzxEw4wNhHbjTulWsi8+dWEVznj1I9R89NC/MGencKtSvnthf9bYKPmjahfqQ 2srK8qfiaovF7/pFC0zy+djv6Tvdy04N93yoW27EJQMPlTpOrhUOmBO41CA4cKwuQE1R My/pMF25RWDxTiINrYGFEhP3fxGAoIrpxfgOVtWiCKiPNQSUP6bWFS4IAjnbri+iYrIi bpFrXo7KtEqSq0feg8ZqzNHUh5i38GM2qIdEgJG2Y9RyFd/5E7xyl2ah2rBC+ox0ZOtX HS7WcY9NsesThztsRLQLeQoXeOtjZorvGiZD3qI4zNwgMo+hQLBYg/Trgc9X7wH4R87B F3LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WQLCa5OO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:56 -0700 Message-Id: <20171010005600.28735-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 19/23] util: move qemu_real_host_page_size/mask to osdep.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" These only depend on the host and therefore belong in the common osdep, not in a target-dependent object. While at it, query the host during an init constructor, which guarantees the page size will be well-defined throughout the execution of the program. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 -- include/qemu/osdep.h | 6 ++++++ exec.c | 4 ---- util/pagesize.c | 18 ++++++++++++++++++ util/Makefile.objs | 1 + 5 files changed, 25 insertions(+), 6 deletions(-) create mode 100644 util/pagesize.c -- 2.13.6 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ffe43d5654..778031c3d7 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -229,8 +229,6 @@ extern int target_page_bits; /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even * when intptr_t is 32-bit and we are aligning a long long. */ -extern uintptr_t qemu_real_host_page_size; -extern intptr_t qemu_real_host_page_mask; extern uintptr_t qemu_host_page_size; extern intptr_t qemu_host_page_mask; diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 9dd318a7dd..826650c58a 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -505,6 +505,12 @@ char *qemu_get_pid_name(pid_t pid); */ pid_t qemu_fork(Error **errp); +/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even + * when intptr_t is 32-bit and we are aligning a long long. + */ +extern uintptr_t qemu_real_host_page_size; +extern intptr_t qemu_real_host_page_mask; + extern int qemu_icache_linesize; extern int qemu_dcache_linesize; diff --git a/exec.c b/exec.c index 7a80460725..6378714a2b 100644 --- a/exec.c +++ b/exec.c @@ -120,8 +120,6 @@ int use_icount; uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; -uintptr_t qemu_real_host_page_size; -intptr_t qemu_real_host_page_mask; bool set_preferred_target_page_bits(int bits) { @@ -3606,8 +3604,6 @@ void page_size_init(void) { /* NOTE: we can always suppose that qemu_host_page_size >= TARGET_PAGE_SIZE */ - qemu_real_host_page_size = getpagesize(); - qemu_real_host_page_mask = -(intptr_t)qemu_real_host_page_size; if (qemu_host_page_size == 0) { qemu_host_page_size = qemu_real_host_page_size; } diff --git a/util/pagesize.c b/util/pagesize.c new file mode 100644 index 0000000000..998632cf6e --- /dev/null +++ b/util/pagesize.c @@ -0,0 +1,18 @@ +/* + * pagesize.c - query the host about its page size + * + * Copyright (C) 2017, Emilio G. Cota + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +uintptr_t qemu_real_host_page_size; +intptr_t qemu_real_host_page_mask; + +static void __attribute__((constructor)) init_real_host_page_size(void) +{ + qemu_real_host_page_size = getpagesize(); + qemu_real_host_page_mask = -(intptr_t)qemu_real_host_page_size; +} diff --git a/util/Makefile.objs b/util/Makefile.objs index 50a55ecc75..2973b0a323 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -40,6 +40,7 @@ util-obj-y += buffer.o util-obj-y += timed-average.o util-obj-y += base64.o util-obj-y += log.o +util-obj-y += pagesize.o util-obj-y += qdist.o util-obj-y += qht.o util-obj-y += range.o From patchwork Tue Oct 10 00:55:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115328 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3177993qgn; Mon, 9 Oct 2017 18:12:48 -0700 (PDT) X-Received: by 10.237.57.98 with SMTP id l89mr6949050qte.77.1507597968295; Mon, 09 Oct 2017 18:12:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597968; cv=none; d=google.com; s=arc-20160816; b=CpCouL0a5HCPZ5+Hz7OYvkICZdmAP8yvC7qPbMqL169g/N/DKWhCUE+LIj1i1SjEtS mYhly+aALJE21d9ZwkLKA3iFiv6SgvW9ox4mAc2kUVJ852lXq60ig7EJZbabtWyLxSjx eyBgqG4qg4jI0p+mSElJZ74APwRUn0PcHAGesG7XoErAvp5Ry5sHQl4sj74nEp9TNfJf q4fyVFCBfpZ1ajigbjpR5jJTR4V5IIWj/c4ah43uZw6FJIONCcsgpYgIAcc23xs4r8LK VrYOun22tmH5d2sbR4VoyKER3+buStDMdlAeVbLCv+4+ze8SeTwB9+SI/l3g+Bx/Y6P/ c7hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7PhYXNVan+59GZGMy7Bu0CSTBdngjVIJFxpG4Ksw8+k=; b=GRXZ0K2JyGVS53me2vkIp/+7sZyca9GhaM13fF+zAi6IegQBBKLiwDV+l7vGiNY3xl WHUg0r3X64+8tHNRIfpOTA/MYZyNRuvFpxyGXZMdj2zkBt+gGhj/d8idQ3BuB2iAwg0q Ddavk1Y6McIpTQHzbwDJwkuGcFihiYB68knG9HIg+CEh9X/HJBBcsiPQNSLPza/BjApH sroMEEgv7Skb7n6aiTusJ/rfU0o7+4680TW+mfO4KGjdkPj+o42klf/jjyCdxQ8bPdo/ KyayyYwQdSDzGlNpJB/4NfM/Pf1MUzFRv9VIdAQrg39+ll6Uyk/4kypFZ+GuhO4vp45y mlaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PR3WJpfJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:57 -0700 Message-Id: <20171010005600.28735-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL 20/23] osdep: introduce qemu_mprotect_rwx/none X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 2 ++ util/osdep.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) -- 2.13.6 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 826650c58a..281782d526 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -371,6 +371,8 @@ void sigaction_invoke(struct sigaction *action, #endif int qemu_madvise(void *addr, size_t len, int advice); +int qemu_mprotect_rwx(void *addr, size_t size); +int qemu_mprotect_none(void *addr, size_t size); int qemu_open(const char *name, int flags, ...); int qemu_close(int fd); diff --git a/util/osdep.c b/util/osdep.c index a479fedc4a..0cf6d9944c 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -73,6 +73,47 @@ int qemu_madvise(void *addr, size_t len, int advice) #endif } +static int qemu_mprotect__osdep(void *addr, size_t size, int prot) +{ + g_assert(!((uintptr_t)addr & ~qemu_real_host_page_mask)); + g_assert(!(size & ~qemu_real_host_page_mask)); + +#ifdef _WIN32 + DWORD old_protect; + + if (!VirtualProtect(addr, size, prot, &old_protect)) { + error_report("%s: VirtualProtect failed with error code %d", + __func__, GetLastError()); + return -1; + } + return 0; +#else + if (mprotect(addr, size, prot)) { + error_report("%s: mprotect failed: %s", __func__, strerror(errno)); + return -1; + } + return 0; +#endif +} + +int qemu_mprotect_rwx(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_EXECUTE_READWRITE); +#else + return qemu_mprotect__osdep(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); +#endif +} + +int qemu_mprotect_none(void *addr, size_t size) +{ +#ifdef _WIN32 + return qemu_mprotect__osdep(addr, size, PAGE_NOACCESS); +#else + return qemu_mprotect__osdep(addr, size, PROT_NONE); +#endif +} + #ifndef _WIN32 static int fcntl_op_setlk = -1; From patchwork Tue Oct 10 00:55:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115318 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3169958qgn; Mon, 9 Oct 2017 18:02:32 -0700 (PDT) X-Received: by 10.55.162.198 with SMTP id l189mr12105128qke.168.1507597352508; Mon, 09 Oct 2017 18:02:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507597352; cv=none; d=google.com; s=arc-20160816; b=t64JrPs8swB/q4oLEg3CESLGZzse+68J1m6+wHqXss8nVy0Yl5PHh+9QVAtxZNOkcF qxve/kgWvI7HFcfDagwLXtyso4WKuB9FAMXpxyuoEdbncjU3deNby1xnZ5Qz5g2GiJg8 0P02vgFqXRxcsUOsbPoqHpKB1kkOHhUjMegM9MJL3ZI9u3wTco1mkju5uSZMfvPQu5xC qetQ1P1Vt4TdGepA8bQzDQe1oBmZBmCnETP5qkHVIsd0g6pqHJq6S8sKQNH7UuaAssHE djzmNE52lxc8l/i/fh9b9XeDCq0V6BhP3NH4eWk0YktypRxkbqwxgQQmAL9D6cn4/drA EVrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=z+pefpIGLM8aANgmdhXMT5MM3MztYymtG/VEnRTl2d8=; b=ft5nmwuvOoJH+KxoA9RJ2I9GjKGEzEChAGfALc2wF/VIBmsP39prGE//LTnRP1XpvW W8ykiIFM+bLTc9mS7rPiPANYnp+i1/nlOufV8BPgo6UtEK105w5+mV9RhXn1mLhtiTFT etkRhVnKi2wQLdShIonBx9Pfx0oVhPayKvRTfPKBRbpfVMTw3ZQJ/2nt8OWsMVeWgN4z awI/9d116o1KYu3HTxQ5LyZZeiE2DWxzp7f1oS1T8yfmRkqcP+KfYbwgRS0GgGvdoh4l kEYgR4pL1ycDXpvSRVhYC0LjahbESuLmDrCTceBIrbtNfts8zEzK6j1SEAy4OP4eJGSC EAuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IT/rwST3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:58 -0700 Message-Id: <20171010005600.28735-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 21/23] translate-all: use qemu_protect_rwx/none helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" The helpers require the address and size to be page-aligned, so do that before calling them. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 61 ++++++++++------------------------------------- 1 file changed, 13 insertions(+), 48 deletions(-) -- 2.13.6 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5ce99d549..d5195a0f5a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -600,63 +600,24 @@ static inline void *split_cross_256mb(void *buf1, size_t size1) static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); -# ifdef _WIN32 -static inline void do_protect(void *addr, long size, int prot) -{ - DWORD old_protect; - VirtualProtect(addr, size, prot, &old_protect); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PAGE_EXECUTE_READWRITE); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PAGE_NOACCESS); -} -# else -static inline void do_protect(void *addr, long size, int prot) -{ - uintptr_t start, end; - - start = (uintptr_t)addr; - start &= qemu_real_host_page_mask; - - end = (uintptr_t)addr + size; - end = ROUND_UP(end, qemu_real_host_page_size); - - mprotect((void *)start, end - start, prot); -} - -static inline void map_exec(void *addr, long size) -{ - do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); -} - -static inline void map_none(void *addr, long size) -{ - do_protect(addr, size, PROT_NONE); -} -# endif /* WIN32 */ - static inline void *alloc_code_gen_buffer(void) { void *buf = static_code_gen_buffer; + void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); size_t full_size, size; - /* The size of the buffer, rounded down to end on a page boundary. */ - full_size = (((uintptr_t)buf + sizeof(static_code_gen_buffer)) - & qemu_real_host_page_mask) - (uintptr_t)buf; + /* page-align the beginning and end of the buffer */ + buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); + end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); /* Reserve a guard page. */ + full_size = end - buf; size = full_size - qemu_real_host_page_size; /* Honor a command-line option limiting the size of the buffer. */ if (size > tcg_ctx.code_gen_buffer_size) { - size = (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) - & qemu_real_host_page_mask) - (uintptr_t)buf; + size = QEMU_ALIGN_DOWN(tcg_ctx.code_gen_buffer_size, + qemu_real_host_page_size); } tcg_ctx.code_gen_buffer_size = size; @@ -667,8 +628,12 @@ static inline void *alloc_code_gen_buffer(void) } #endif - map_exec(buf, size); - map_none(buf + size, qemu_real_host_page_size); + if (qemu_mprotect_rwx(buf, size)) { + abort(); + } + if (qemu_mprotect_none(buf + size, qemu_real_host_page_size)) { + abort(); + } qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); return buf; From patchwork Tue Oct 10 00:55:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115329 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3178784qgn; Mon, 9 Oct 2017 18:13:49 -0700 (PDT) X-Received: by 10.55.97.202 with SMTP id v193mr11301800qkb.165.1507598029192; Mon, 09 Oct 2017 18:13:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507598029; cv=none; d=google.com; s=arc-20160816; b=uj5C0SXW0wP58gmLxkromwYxiR6pUsr44qbmOnAZNHoOmQDPSJTPOoRYvCcPddWCr7 /BS8p8K3EcAGp2KiGhILZZ8LvSomMmZsFQZwFgafMY8JimF1qa3bZMF//kxLhbLfiZiq ZVobbtLAv6kl8zhfIiikZ7NLr+JdRPkd3E9iA1Qu8ojzB3JRCSkuxf3VHq7XiYByeWy3 I/cILQFG2fhyhYrK+KAquDL1/7w1hnB/U35OSfxdyYntaELtFhZkuxDJ3jGUCFDI/UU9 P2edNCSiQE8uRsQE1ZG6JTnhjzIronJKJIkLGc525jb4dgzAdTjuY6mm2joDgjzB0En/ FPGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Xxy9567/LyD/NAl1R9dzWOF5rk63KT8JXQlJtDyUSpQ=; b=bct6fR0EhmEzU5b2UT41ONAl5urJurZ58+OR5ESgZcCQ8zl+rwhkLcQEPudoqiaVaq 6ToJbYr7Hr1l2XVUOp0p+ryjBZoDOCg0QlC/HNn9/+x8A6syByT3kGT2zFZeIIZF1JWN NLbSb/Q58npNxxugjnhNw8JHha07DPk8RXYmjG1Bgkr6DJ73zGQJgYyJ6e9Sc0ekNu+M 5dKYlNqdquRC5izEXuNbZjCsfa361Bq/2bp0m9plelhVZ+aGY3YfSlSDH5cyT30D59f9 YS36RfjjcgbomfWua0Tnac8zQKsnAtQamn2CrDPFOAV83YGFqivqm2fUYlgkuO8t2KFQ R1Lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GWAzig0w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:55:59 -0700 Message-Id: <20171010005600.28735-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL 22/23] tcg: define TCG_HIGHWATER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Will come in handy very soon. Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.13.6 diff --git a/tcg/tcg.c b/tcg/tcg.c index ee60798438..4492e1eb3f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,6 +116,8 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, static bool tcg_out_ldst_finalize(TCGContext *s); #endif +#define TCG_HIGHWATER 1024 + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; @@ -430,7 +432,7 @@ void tcg_prologue_init(TCGContext *s) /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger than we expect the code generation for any one opcode to require. */ - s->code_gen_highwater = s->code_gen_buffer + (total_size - 1024); + s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER); tcg_register_jit(s->code_gen_buffer, total_size); From patchwork Tue Oct 10 00:56:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 115330 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp3179187qgn; Mon, 9 Oct 2017 18:14:21 -0700 (PDT) X-Received: by 10.55.17.33 with SMTP id b33mr11939542qkh.58.1507598061840; Mon, 09 Oct 2017 18:14:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507598061; cv=none; d=google.com; s=arc-20160816; b=G6LGEigg4vHlJ+u1pbj6Ji8zlvkojloiAaQApgaRTH1jSsyld5gtEd6BhKcnLl7p4o bi16Ksvy0Yk8U0nbsWUMhJg64APkewef58OkamdxRJseojyLe3rYPERr9krSQrIRXEtV 0wVIsurkJ+WReIrzv9Y2QNJi9kTkUYJhokttlSV7VLxUAXPxchmvX2qgvd2O1XcO3RzZ wHu0GDnGE0BAmwLBNY2YO2AVMUN9+tQ1X2/7Sz50GQT5/pZRaMS6MuavsHzXQU7M84sJ lrMivgJjh//b5LuLyDWFy/ORr3ckRn6B+8B5pQ68yvgVFsrIZezWswcdBN2JnET4yEWX ScUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eyzCkAldlJhlOwbAcPTVemO41jvU8FeUPJW2c1/rJgo=; b=kCqdUtUyx8jnKBPnLsqHURrbna2KuEidoamrAr+4P/QUHJ5sqM7RI2S8482beuuZgU k1wrobNflYE4VL/MHDVM3nRuYn47pwhZi2Hp3gI9pJgiFOtd3ontgyEGsMNUD/VetBIA LxEZuumzSvmU6uq6aNY3n6IGZcjgTmTNl0eFqszzG1groJWKu//FqYbwowUglO4u6T4I iRV9vj/RVnFbSJ6dSQtITMNWidXaM98N8hfjsvjlbB0ymassi694OWPeBs4bt/0VIxtX A70eNAZWWV24DB1+l8lpIR4s6yfaX3YipWcFXfML+5k/SPvVvdavCm6dkYMVrQ+qGBQ8 9jvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AsbCpM3V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id n19sm17121368pfj.52.2017.10.09.17.56.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Oct 2017 17:56:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 17:56:00 -0700 Message-Id: <20171010005600.28735-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010005600.28735-1-richard.henderson@linaro.org> References: <20171010005600.28735-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL 23/23] tcg/mips: delete commented out extern keyword. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Jiang Biao Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jiang Biao Delete commented out extern keyword on link_error(). Signed-off-by: Jiang Biao Message-Id: <1506762042-32145-1-git-send-email-jiang.biao2@zte.com.cn> Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.6 diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index e993138930..4b55ab8856 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -36,7 +36,7 @@ #else /* To assert at compile-time that these values are never used for TCG_TARGET_REG_BITS == 64. */ -/* extern */ int link_error(void); +int link_error(void); # define LO_OFF link_error() # define HI_OFF link_error() #endif