From patchwork Mon Aug 3 21:00:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 257465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48EC9C433E8 for ; Mon, 3 Aug 2020 21:01:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4DFAF22CF8 for ; Mon, 3 Aug 2020 21:01:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1596488485; bh=r6TtqHCA3jtW5jbtGF1GAwZ0vnLQNPiDh4RVvrRIEJQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=XC5SaLwq6MgVOeIUcWwq1pzKQOWakJ9v719BgSBAtOYpsB1gkaLavgUt0vAwhOqp3 H/9+x52F4tAG2yKqFJwKF0tsm+ElZG++zhKO2SzQXRtEU5cKgaGnT1/1XCEuu0NWGh MaxHUeeN3wPMYFZUB7IUlV+6eNCy0nnwBbzx03c8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729031AbgHCVBX (ORCPT ); Mon, 3 Aug 2020 17:01:23 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:34288 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbgHCVBX (ORCPT ); Mon, 3 Aug 2020 17:01:23 -0400 Received: by mail-io1-f65.google.com with SMTP id q75so31848823iod.1; Mon, 03 Aug 2020 14:01:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bKskqR1BQLcQkRJa4jVCjBb26v/8ydnan9t1CfXlQP0=; b=F3I5h+1s3UcJuJQIeVbdou8/lAyhnUMlEhtMa1/w69LqALXHoY4ZNvEqEZ8I7v1E4b 2jNorcDEgjjTASJg9DPX9XhGvMvRZK44Y7EHm00YQCDJ99YYZ3nYiKIKRMnhrRfj1cAR uZv7WY5kUeNPzuJOy3HgdGN261vglpbF6hCEd8f/R0gPmI6/7Cv7ueRiqOEgllHS75Ks J8u6RYTVWDsKnl6L6ECuQiOvJzm0qpFSZC0/IIjTrNZMPJO0uuZ3oP8hyfoFxL16n8xS 7pqLANaQt55//SdPd5NxH9pt31J4i7B6G+0hxwTZnbCNQ7qyWWtbGKMNK/oB7cPOJD1c veuQ== X-Gm-Message-State: AOAM533y/m1MgN+Lfli8vdjoQidgdVwd3BzWF9Zq0d/6fMSOkfvVC/RZ 6yAZDex/edq+AqGKKbyugQ== X-Google-Smtp-Source: ABdhPJy4qG4p8bfrwbYSt3lvEPjhQpXlxLgUy+tuEvf+7Lf39Luq/OZA9TVNwuc57X3DpMVIygnSPw== X-Received: by 2002:a05:6638:2601:: with SMTP id m1mr1810484jat.141.1596488481653; Mon, 03 Aug 2020 14:01:21 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:21 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 01/27] PCI: Allow root and child buses to have different pci_ops Date: Mon, 3 Aug 2020 15:00:50 -0600 Message-Id: <20200803210116.3132633-2-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org PCI host bridges often have different ways to access the root and child bus config spaces. The host bridge drivers have invented their own abstractions to handle this. Let's support having different root and child bus pci_ops so these per driver abstractions can be removed. Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/probe.c | 8 +++++++- include/linux/pci.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..8712e595174d 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1030,6 +1030,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) { struct pci_bus *child; + struct pci_host_bridge *host; int i; int ret; @@ -1039,11 +1040,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, return NULL; child->parent = parent; - child->ops = parent->ops; child->msi = parent->msi; child->sysdata = parent->sysdata; child->bus_flags = parent->bus_flags; + host = pci_find_host_bridge(parent); + if (host->child_ops) + child->ops = host->child_ops; + else + child->ops = parent->ops; + /* * Initialize some portions of the bus device, but don't register * it now as the parent is not properly set up yet. diff --git a/include/linux/pci.h b/include/linux/pci.h index c79d83304e52..cec789a0437e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -516,6 +516,7 @@ struct pci_host_bridge { struct device dev; struct pci_bus *bus; /* Root bus */ struct pci_ops *ops; + struct pci_ops *child_ops; void *sysdata; int busnr; struct list_head windows; /* resource_entry */ From patchwork Mon Aug 3 21:00:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247397 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539275ilo; Mon, 3 Aug 2020 14:01:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyitcvYrUUK5y1vOTHi6qhbPMXp0q7ZbM2t01xzW+nYby4nE/vH1RlanoglA7LpfAMS5+eG X-Received: by 2002:a17:906:b015:: with SMTP id v21mr7838300ejy.507.1596488489611; Mon, 03 Aug 2020 14:01:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488489; cv=none; d=google.com; s=arc-20160816; b=VbF5u7TLeSGRzhMJ29bvIP9ZN9CmVAPy2BJyy43lfRDs1pvVKNOW7B2+ZnqLpIEy+D Bz62OpzwN1qSOjAy+n9gAtM1bUKAbZt9IobqivTJMPev/+rlMThAyqHRV1DBEbV1e0Qu xfngY2rCMOrR/WV8JlQ1pQtZdn20zT35nnUrHtgrWO0V7lLYhgIVjTCUin1TXyuIvjzg GLD2UcndCmAWqhzGrhmsi4ferLa0bZOnlfve5fzgRaJ5Pt/0aE2bb8sRM7wO1wBtLkFn muyaeWSLI3rFlKzaJYQTvIu/BWKQEXdL7gae8Zc0xSWx99X0bI67jVx7OIhSTYP8GRHv XDtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=bKkfbqtFs4Kbwg3DVrwD4EpvIH0b0CJsDrYNB8t8wYc=; b=a3J8GzNGp9SB1Mf46scOTgdpzj3ICh9BU8aqyULfbJsF2T5d9EjAVdBGupc6m/OU05 WHrumxh3Bs+4qfLxVxZRW3CrwCKpbp6Pr2cXZzsl5amWKyhElsJdlwi4YutyeadYPcFL rAJEfowRg3EtTnk+eVcsxYqR7cbHRblt9VM5d8+T+7cXQf6Ol/FZ0aBs65VrHshiDGDi LKCG2D1HENooQblo0neKUbum5RzlDm+FlHdgtLvd1gNST2XIEgh05rKHY+oxrH8p96Gw CZbpKdZfyLol3YVBCtjsoI2159cTeD7nLl4Omy/t9/4Fq2pPzXApD3kZuBSo6mU2Tz+6 BRiA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.29; Mon, 03 Aug 2020 14:01:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729336AbgHCVB0 (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:26 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:32825 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbgHCVBZ (ORCPT ); Mon, 3 Aug 2020 17:01:25 -0400 Received: by mail-il1-f194.google.com with SMTP id p16so21555130ile.0; Mon, 03 Aug 2020 14:01:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bKkfbqtFs4Kbwg3DVrwD4EpvIH0b0CJsDrYNB8t8wYc=; b=K4K81kwhURZLjBoN5skJTJbRLhzsDfzeasnLbCI5VohAbnP5ZH+/SfT0Vm9Bu+p09N muOOqweLvp0EjYPJPsDSMi4w/sQIDQW11EMhUQXaXw1ZXRT66qCMDsitu9isybSc2uW6 Q/dgho82FhzK4tgYVxcy+q4Eq2yFci6fWIHFEvMcDUU8CIIarmSOK5kTffI5Knwt/hzs nlJ4TnjplXj9KsSV3MWjyTtUylkh3zr375+zzcxKuDvFl1mlTF0numuNjFDaBwOfM4jX GO2gCYSakP5dmo9iFEPd/sa1s3TtwjanXGL98hA4jqsAY3QXnUEJ55YaRxPZaWTqvzp5 gvTg== X-Gm-Message-State: AOAM532hLjx2c/TyIX1/luReVd8P2M8XEiF4ODujkPWBaIMuIMWkTpXK vB81LwUKgQBFIgIprq1YSg== X-Received: by 2002:a92:a112:: with SMTP id v18mr1292705ili.124.1596488484082; Mon, 03 Aug 2020 14:01:24 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:23 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 02/27] PCI: dwc: Use DBI accessors instead of own config accessors Date: Mon, 3 Aug 2020 15:00:51 -0600 Message-Id: <20200803210116.3132633-3-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The Designware DBI space contains the root bus bridge config space. Platforms needing custom {rd,wr}_own_conf functions are also the ones needing custom {read,write}_dbi ops functions and the access sequences are the same. Replace all dw_pcie_{rd,wr}_own_conf() calls with the DBI variants in preparation to remove dw_pcie_{rd,wr}_own_conf(). Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 55 +++++++------------ 1 file changed, 19 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0a4a5aa6fe46..6232aefbbdb4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -82,13 +82,13 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) unsigned long val; u32 status, num_ctrls; irqreturn_t ret = IRQ_NONE; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; for (i = 0; i < num_ctrls; i++) { - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + - (i * MSI_REG_CTRL_BLOCK_SIZE), - 4, &status); + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE)); if (!status) continue; @@ -148,6 +148,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d, static void dw_pci_bottom_mask(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; unsigned long flags; @@ -158,8 +159,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; pp->irq_mask[ctrl] |= BIT(bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -167,6 +167,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) static void dw_pci_bottom_unmask(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; unsigned long flags; @@ -177,8 +178,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; pp->irq_mask[ctrl] &= ~BIT(bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -186,13 +186,14 @@ static void dw_pci_bottom_unmask(struct irq_data *d) static void dw_pci_bottom_ack(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); } static struct irq_chip dw_pci_msi_bottom_irq_chip = { @@ -310,10 +311,8 @@ void dw_pcie_msi_init(struct pcie_port *pp) msi_target = (u64)pp->msi_data; /* Program the msi_data */ - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, - lower_32_bits(msi_target)); - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, - upper_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } EXPORT_SYMBOL_GPL(dw_pcie_msi_init); @@ -327,7 +326,6 @@ int dw_pcie_host_init(struct pcie_port *pp) struct pci_bus *child; struct pci_host_bridge *bridge; struct resource *cfg_res; - u32 hdr_type; int ret; raw_spin_lock_init(&pci->pp.lock); @@ -458,21 +456,6 @@ int dw_pcie_host_init(struct pcie_port *pp) goto err_free_msi; } - ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type); - if (ret != PCIBIOS_SUCCESSFUL) { - dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n", - ret); - ret = pcibios_err_to_errno(ret); - goto err_free_msi; - } - if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { - dev_err(pci->dev, - "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", - hdr_type); - ret = -EIO; - goto err_free_msi; - } - pp->root_bus_nr = pp->busn->start; bridge->dev.parent = dev; @@ -651,12 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) /* Initialize IRQ Status array */ for (ctrl = 0; ctrl < num_ctrls; ctrl++) { pp->irq_mask[ctrl] = ~0; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, pp->irq_mask[ctrl]); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); + ~0); } } @@ -698,14 +681,14 @@ void dw_pcie_setup_rc(struct pcie_port *pp) pp->io_bus_addr, pp->io_size); } - dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); /* Program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val |= PORT_LOGIC_SPEED_CHANGE; - dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); dw_pcie_dbi_ro_wr_dis(pci); } From patchwork Mon Aug 3 21:00:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247398 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539296ilo; 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[23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.31; Mon, 03 Aug 2020 14:01:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729052AbgHCVB3 (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:29 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:38423 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729344AbgHCVB1 (ORCPT ); Mon, 3 Aug 2020 17:01:27 -0400 Received: by mail-io1-f66.google.com with SMTP id l1so39991437ioh.5; Mon, 03 Aug 2020 14:01:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ijQ8ATU40Ukxf+vdFPpN/cTBNWQIy8LHFEwNkXuS7vE=; b=TtA3D50HOWjGSOYcI0fLq7MAUnDBSi++nGASm4Aoh/xGbxG+Nth6WBRpCcWzR9SZpJ zXFkOFhdk5CglhnIbRVhmHVnrTacwOWTsbwSRutc8x0VmJKmquUL+Gsix5cdpmcsFwQz k0+kaJQSrIPorGnuaRYv9orYBj9W0AYPkcJe7trNLYw/agEG2PAuWh4BjPBgOjPjVSg8 Pwsc5AphA4aWpxRoxYG36XEP47a81vesf02tunJ5SNy+qKfpGxOeW++4gDyBA4TwHmyB Eq121ULzAvJ6cWj5psaqF7VRaLKEH/0fSCEaHlmY4VaVJYSKZO/gmO4qxftZGmUIOTff TY3w== X-Gm-Message-State: AOAM532GpYjM3KbWCmeSb05lEiLzZCNVZwWkvEuYlBu6FitDnYc5T/Gp YmOiADsJm8DwexS5xjTDBQ== X-Received: by 2002:a05:6638:2482:: with SMTP id x2mr1801792jat.55.1596488486266; Mon, 03 Aug 2020 14:01:26 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:25 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 03/27] PCI: dwc: Allow overriding bridge pci_ops Date: Mon, 3 Aug 2020 15:00:52 -0600 Message-Id: <20200803210116.3132633-4-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In preparation to allow drivers to set their own root and child pci_ops instead of using the DWC specific config space ops, we need to make the pci_host_bridge pointer available and move setting the bridge->ops and bridge->child_ops pointer to before the .host_init() hook. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6232aefbbdb4..7cd8c9528d4c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -344,6 +344,8 @@ int dw_pcie_host_init(struct pcie_port *pp) if (!bridge) return -ENOMEM; + pp->bridge = bridge; + ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, &bridge->dma_ranges, NULL); if (ret) @@ -450,6 +452,10 @@ int dw_pcie_host_init(struct pcie_port *pp) } } + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_pcie_ops; + if (pp->ops->host_init) { ret = pp->ops->host_init(pp); if (ret) @@ -461,7 +467,6 @@ int dw_pcie_host_init(struct pcie_port *pp) bridge->dev.parent = dev; bridge->sysdata = pp; bridge->busnr = pp->root_bus_nr; - bridge->ops = &dw_pcie_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; @@ -667,11 +672,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_COMMAND, val); /* - * If the platform provides ->rd_other_conf, it means the platform - * uses its own address translation component rather than ATU, so - * we should not program the ATU here. + * If the platform provides its own child bus config accesses, it means + * the platform uses its own address translation component rather than + * ATU, so we should not program the ATU here. */ - if (!pp->ops->rd_other_conf) { + if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) { dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 656e00f8fbeb..bad3cddab28e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -201,6 +201,7 @@ struct pcie_port { u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; struct pci_bus *root_bus; + struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); }; From patchwork Mon Aug 3 21:00:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247399 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539318ilo; Mon, 3 Aug 2020 14:01:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2rOhf7IG5d8FIDtDXFXPsCoqBl7jX8Cb+IqzObKbm6QyyCjy+RB//2PBeIUHeuE+Fw2u9 X-Received: by 2002:a17:906:454f:: with SMTP id s15mr8243249ejq.130.1596488492558; Mon, 03 Aug 2020 14:01:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488492; cv=none; d=google.com; s=arc-20160816; b=YU6fgMjRyr4lnCj9CBcmpVb5DPUfNU/IznHUNr9Lb1QFgNgtDoE03W8PYFgF5QkZO1 pHQI1SOwFSlbsO6kTRq301gADoc41WdWwja5QpfMNLLuvu5qGsBZ09iumIRXApL0OSnx 6Z0emiTVlGkIiRuNDMrHvshjwj1v9Z2S7w4KAV8GkrB3pU2F4XUO/4735QBbvSyjHamI vK2Z4brl/Ps8UeLuidLgnSZp7xwaBSfY7599yK21gqjy7u1SQ4Z6h5zGHRI6lI5iK9Zp G+bQ+ZaUhrWySYhWQnVE9bAKtww+RIvGb9fCQGotu2lzHuBnq3bwytj7sp8P4OAcAb2k pGBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=iogw0PHdW281Zilh8Ybv/eHK0mtpVLAHgw0xblz2JaM=; b=CLFaKUXX9ehaLjGlpj4Wot55zAIxfPUDXG9g/jMxWyjMmsjtYhem0r/sFfGWUsqhtX QnCU/WiBxeI/BJnGn0fJBbOla3XQ08NJtvrv180E2pNGPPRSjHE9aPVluwFGBYe/maF8 ditHsj3xH5xUNARehtNY5yisc0UREDng/uf64sDP23R5isq4dUNOTCHWqKTuEQOQFZ8P RfGDZvUsJUZSt0q1CasViZTm6KLC05WEb5nnNcZjnPL926aS9FGfs3n49Du7ciAFNRmp H3LMggScoPoWuFn8N8W3A4+umHTWJlnZdsJj5sD2+jhrceRrgyNTQCMwbHZdy9MVexon Ucug== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.32; Mon, 03 Aug 2020 14:01:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729349AbgHCVBa (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:30 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:43651 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729040AbgHCVB3 (ORCPT ); Mon, 3 Aug 2020 17:01:29 -0400 Received: by mail-io1-f68.google.com with SMTP id k23so39948190iom.10; Mon, 03 Aug 2020 14:01:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iogw0PHdW281Zilh8Ybv/eHK0mtpVLAHgw0xblz2JaM=; b=Y+G2v9urpYl/zFtdG3UZYy7xrppuQDw4XuVOJnC+YA1KSSOiIgf3tQh6V2qHshLntD xXG3yq5Kw/+74OYr3fWMaSjmr6qZFiU+kEjL8liXnId16rLCSTW4wHsYmF6zW1eR2sNp nZBVHw0nzVPcc/lofqPmwnywFw/aYDPhIlx13HVrEQUKkbHnIHG17t4YdBXLRHLfsNT/ Ns/x3yGacAY9h22ajXgWiKkjU+nnrZ3vrbMOs+LxSkvmrT0JGz8oAwKC8cyAAXfVlWan Y168V6JPNJkR8QePx3brLcY+IdQrrm4DusWfiznfyWgaYpNDYGyUInL2eqP5gktOYj4n MEbA== X-Gm-Message-State: AOAM530Zt6IRkNcoPaDkDcVX4RCQKZPXY85uO8wvzbj3pHI6/1w17vS/ Hd/7blXodU0WArYVg8czgA== X-Received: by 2002:a6b:c504:: with SMTP id v4mr1848864iof.20.1596488488493; Mon, 03 Aug 2020 14:01:28 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:27 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 04/27] PCI: dwc: Add a default pci_ops.map_bus for root port Date: Mon, 3 Aug 2020 15:00:53 -0600 Message-Id: <20200803210116.3132633-5-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The Designware root port config space is memory mapped accesses via the DBI space by default. Add a common implementation dw_pcie_own_conf_map_bus() for platforms to use. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 11 +++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 13 insertions(+) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7cd8c9528d4c..e9d31c341881 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -615,6 +615,17 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); } +void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) +{ + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (PCI_SLOT(devfn) > 0) + return NULL; + + return pci->dbi_base + where; +} + static struct pci_ops dw_pcie_ops = { .read = dw_pcie_rd_conf, .write = dw_pcie_wr_conf, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index bad3cddab28e..dbe53e464e11 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -378,6 +378,8 @@ void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); +void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { From patchwork Mon Aug 3 21:00:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247400 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539387ilo; Mon, 3 Aug 2020 14:01:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzDKpfVezrg82u7jpkLZpSrMOxOPiZaj2RRuoC7rJyaNMEOLCirEk2TVrq+/Q/MgoNKA2ON X-Received: by 2002:a17:906:a204:: with SMTP id r4mr17817566ejy.552.1596488495185; Mon, 03 Aug 2020 14:01:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488495; cv=none; d=google.com; s=arc-20160816; b=qw1XmiDuzyNi33IrXEOvayKc/o0CxKpZ5CoRR71jeF5fTmVlw8oCD8p7Tiy8SaiWmn fKeYtG83Md/b7PzbpaY9LNZXns5IvCZZje5nyOUGtEIW1YHDqIYyhFsdWH5wT5NNjRa+ u+Na5L34/tjQiZeSirFiy8TGKp2KMUOKfHKNX3wWoiZIrUYaDvp/ZXymzZzF4KW+dx11 6nK1d8ir7/B6dOI62Ks3ab3rQsWrL5tMiG4A1n8uY/2x+pMiKzFU4i/2ji/0hr20ZoT9 6IhMbiXUh1G1x/dr45NZI7RPouXy5TnB9ETnlkwVmLpS38tTaVaCC/M6Hy+P9E7YylNE Wgxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=EQL3A7dHzz+gC5njEctrBiMEIqtA+XjXrb2o208g3Ks=; b=HLfXvVgS4D1HCUlW30SNJFIg1kr9FxEkBKw6FiAA7jq0kXkJ2ANkNnugPGhRDf34Jd ijQAekdtPNpQ2sqte7qIdyeDSkU3TxQ6w7fO7ecc2xvTQCtUoXICnW3A4rRKH/nSuPNb uaRsYwtXrC4/2K4ePqzyJN8hP8mgu8NeXYwJhiHIXKwSFsOcDPs6i1xkpVA8jPwDlJHQ 6mThTu9AG//q+Cd2QBut84ZF01bjPMj7bu9iUXz37AbtAMxSKYudEC1Utium9U8x7767 3vg4+t4VRvX5Hc2CMu6nbTSiFOAaIOKrDyI6nslyRO1gbO32v33b9PbBzum2+xFlduNg d1DA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.34; Mon, 03 Aug 2020 14:01:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729043AbgHCVBe (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:34 -0400 Received: from mail-il1-f196.google.com ([209.85.166.196]:44506 "EHLO mail-il1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbgHCVBc (ORCPT ); Mon, 3 Aug 2020 17:01:32 -0400 Received: by mail-il1-f196.google.com with SMTP id j9so28944215ilc.11; Mon, 03 Aug 2020 14:01:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EQL3A7dHzz+gC5njEctrBiMEIqtA+XjXrb2o208g3Ks=; b=F7YBgQRbZju55J1lslO3ZYYUq/hG4N8wTHAwZU2uIZn8/wbItJEPFW7cgXc/wG+XfX h0WHNqI1RTLpyW656CwcisHE7Q+Q4x8mW2n84ZwgibfSrfEBeh6zm2gmmWlakCDUtgEx avkG/p9QCgev92l5nTcWtt14O1h+Elp5VWTer/gNDWmJQlxbloZGCMUvdStxhzeqXlpS LSjbamKWn3SX7BPFb8J11Gzdtulr3dRD/Qp0FqS50o17Sqf7h5MtlxvR1BWPEFbhy8cp PyoI8WMbk9WKubwvcXdA1h7tHii6zExHwmSoD9wS9iFe7js/PGcKdtTMbtf+5I5DxpEU 1XCg== X-Gm-Message-State: AOAM533sflnPRlLher4tSnqpk1k4OBCcobnTMHudfrIOl+9Q6YddgPbV fiUxMbrLl0V74dU6/sv1wQ== X-Received: by 2002:a92:d7cb:: with SMTP id g11mr1303449ilq.89.1596488491153; Mon, 03 Aug 2020 14:01:31 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:30 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 05/27] PCI: dwc: al: Use pci_ops for child config space accessors Date: Mon, 3 Aug 2020 15:00:54 -0600 Message-Id: <20200803210116.3132633-6-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Amazon driver to use the standard pci_ops for child bus config accesses. Cc: Jonathan Chocron Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-al.c | 63 ++++++---------------------- 1 file changed, 13 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index 270868f3859a..5c5763f14485 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -222,14 +222,15 @@ static inline void al_pcie_target_bus_set(struct al_pcie *pcie, reg); } -static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie, - unsigned int busnr, - unsigned int devfn) +static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) { + struct pcie_port *pp = bus->sysdata; + struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp)); + unsigned int busnr = bus->number; struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg; unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask; unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; - struct pcie_port *pp = &pcie->pci->pp; void __iomem *pci_base_addr; pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base + @@ -245,52 +246,14 @@ static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie, target_bus_cfg->reg_mask); } - return pci_base_addr; -} - -static int al_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 *val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct al_pcie *pcie = to_al_pcie(pci); - unsigned int busnr = bus->number; - void __iomem *pci_addr; - int rc; - - pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn); - - rc = dw_pcie_read(pci_addr + where, size, val); - - dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n", - size, pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, - (pci_addr + where), *val); - - return rc; + return pci_base_addr + where; } -static int al_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct al_pcie *pcie = to_al_pcie(pci); - unsigned int busnr = bus->number; - void __iomem *pci_addr; - int rc; - - pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn); - - rc = dw_pcie_write(pci_addr + where, size, val); - - dev_dbg(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n", - size, pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, - (pci_addr + where), val); - - return rc; -} +static struct pci_ops al_child_pci_ops = { + .map_bus = al_pcie_conf_addr_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; static void al_pcie_config_prepare(struct al_pcie *pcie) { @@ -344,6 +307,8 @@ static int al_pcie_host_init(struct pcie_port *pp) struct al_pcie *pcie = to_al_pcie(pci); int rc; + pp->bridge->child_ops = &al_child_pci_ops; + rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id); if (rc) return rc; @@ -358,8 +323,6 @@ static int al_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops al_pcie_host_ops = { - .rd_other_conf = al_pcie_rd_other_conf, - .wr_other_conf = al_pcie_wr_other_conf, .host_init = al_pcie_host_init, }; From patchwork Mon Aug 3 21:00:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247402 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539440ilo; Mon, 3 Aug 2020 14:01:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzux2hHpejo70WeSeBu2lgIMDFcHApaVvLLDyG5uEd407d0aFkQLhBPvOhnC1cea1ClIm7H X-Received: by 2002:a17:906:454f:: with SMTP id s15mr8243681ejq.130.1596488498741; Mon, 03 Aug 2020 14:01:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488498; cv=none; d=google.com; s=arc-20160816; b=MGYtivV2K0OC0gj08bmSCNrc9mCsuUEgzK50+oA6hLvsjZ3U1n8TrH5WVtm1iDqr+r qh80mLhmwsUqnUU7+MIbYg46KTvmmc3GVOTuDV6VzZ2lDhOqegI3cQsZoU8DjVEg/fPV 2kKx5/dGGhFLnsIWgvK1PGUL6HX0NQqGTDaLl38tlT6/cS1HuoEGzJmVkLfEPnKYlqwX kb39+ACOAvWm3dR7TC6hywwXHrfO3mjgf9Om2lFDjtSYdw5Jo4F1P4kz5DuUwpaHxfGi Z3L1JCwZPMjQMrCSN5J+FbruwSl+XO5EZIRwXDkNnNUTZryJP00FfcmvCx7aZRDdMkVv caYQ== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.38; Mon, 03 Aug 2020 14:01:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729055AbgHCVBh (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:37 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:43661 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729365AbgHCVBg (ORCPT ); Mon, 3 Aug 2020 17:01:36 -0400 Received: by mail-io1-f66.google.com with SMTP id k23so39948561iom.10; Mon, 03 Aug 2020 14:01:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DhVIHy/Rw3yhAfrDggAhIwfl4PW3KaTrEVn3uFz3dc8=; b=mGfvjJ46N/FQjo19ot0o+xbJClOAX2J9x0YQjYvXVvPwJV8D5RmMUofnnr7uHaStkh kDQ7urSLtBiGS1DH3Ofr3wOegJqXTuppubHEkHMJyY/LQFiNYU0ay8kkB9yrvKNvvU6I xPpatg7EMzvGs/sJTPt58eQP1gyF0ltwdPkFfE9e8ARF7KD1ApyVahq9BfNFxVg3ln2b oavXhc37HD4G9Br2ORYxiQdz22laYVX2iQk/UX6Oc1uyeQXj4qstsE2/VIa26Ba09/pN 5DFxBKcscwnYNdPHzVGhPNF2WCwLQZLy1vSamdRwvkVmf57G7kBHcMGezvq8YhPtYx+l XHQA== X-Gm-Message-State: AOAM5311jcXP1s+/hOiG7CXGwpyPb5ci/TY/t4D9FuGXB2xAjPfqTwZG mlefQCtiQJd3MCWK0kxbZg== X-Received: by 2002:a5e:d519:: with SMTP id e25mr1841622iom.36.1596488495414; Mon, 03 Aug 2020 14:01:35 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:34 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 07/27] PCI: dwc: tegra: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:56 -0600 Message-Id: <20200803210116.3132633-8-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Tegra driver to use the standard pci_ops for root bus config accesses. Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-tegra194.c | 30 ++++++++++++---------- 1 file changed, 16 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 92b77f7d8354..52bb145c42d1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -568,42 +568,44 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) return IRQ_HANDLED; } -static int tegra_pcie_dw_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) +static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - /* * This is an endpoint mode specific register happen to appear even * when controller is operating in root port mode and system hangs * when it is accessed with link being in ASPM-L1 state. * So skip accessing it altogether */ - if (where == PORT_LOGIC_MSIX_DOORBELL) { + if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) { *val = 0x00000000; return PCIBIOS_SUCCESSFUL; } - return dw_pcie_read(pci->dbi_base + where, size, val); + return pci_generic_config_read(bus, devfn, where, size, val); } -static int tegra_pcie_dw_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) +static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - /* * This is an endpoint mode specific register happen to appear even * when controller is operating in root port mode and system hangs * when it is accessed with link being in ASPM-L1 state. * So skip accessing it altogether */ - if (where == PORT_LOGIC_MSIX_DOORBELL) + if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) return PCIBIOS_SUCCESSFUL; - return dw_pcie_write(pci->dbi_base + where, size, val); + return pci_generic_config_write(bus, devfn, where, size, val); } +static struct pci_ops tegra_pci_ops = { + .map_bus = dw_pcie_own_conf_map_bus, + .read = tegra_pcie_dw_rd_own_conf, + .write = tegra_pcie_dw_wr_own_conf, +}; + #if defined(CONFIG_PCIEASPM) static void disable_aspm_l11(struct tegra_pcie_dw *pcie) { @@ -970,6 +972,8 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp) struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val, tmp, offset, speed; + pp->bridge->ops = &tegra_pci_ops; + tegra_pcie_prepare_host(pp); if (dw_pcie_wait_for_link(pci)) { @@ -1057,8 +1061,6 @@ static const struct dw_pcie_ops tegra_dw_pcie_ops = { }; static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { - .rd_own_conf = tegra_pcie_dw_rd_own_conf, - .wr_own_conf = tegra_pcie_dw_wr_own_conf, .host_init = tegra_pcie_dw_host_init, .set_num_vectors = tegra_pcie_set_msi_vec_num, }; From patchwork Mon Aug 3 21:00:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247404 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539509ilo; Mon, 3 Aug 2020 14:01:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5hVKUb1dcjx+JkImuId7Lc3Urb4VUhTxMENdjfU+NgxnM4nAbyL0wqBUR5wA71xch4zZn X-Received: by 2002:aa7:d047:: with SMTP id n7mr18164181edo.78.1596488503603; Mon, 03 Aug 2020 14:01:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488503; cv=none; d=google.com; s=arc-20160816; b=ORCKbzrW9/qktgDFkYMo3Hmns0EGQVcfP90qClLkIlg/GA2mWmwR9kBj8WAvnzDLxX ruz44LbZFj6T3OTVmEVNRbQz64G6EmPQAVlwS10APziw2GZdHvlJrDfXvh3iBbUFlc5o 9fm6dL5n/fSL6jH4swvVsXyAF6I4XfSPbPwP9KArSP9rbyvVa6/xCvWzZmVc3+SOaadC VQ5CjiyM8jLaqCOjXzugkdXw+y0OY6NSUqhoGC+x2IeepF9RZrbuaZqh+TId3jWgkSqo Y6iAqepCoWXvAoJNHsd2PQSTHz5cE/63X9sgguQzquM4zshxE4AlHGPMq9wC3Hhb14rR 6Ehg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=uqMmmSdRu2mAJmxJVyfdC1UZDoCNddnAHqJmdw3g1qc=; b=SutVnk4SFxPys7bbh7t0ChOMNBR8rNRDs0pSOpx50RWehh59gfHwsQ5/vWMv3fzu7b 7gT3rkiOsg7mNHDtBksI4dfoSkUFCrinKQQ3tsANUNa7oIndvR+kG7Y/rMcqM7wLGko5 9rb/VR9uf0urlw+2pO4Qio3napuxSIKJ/CDYRKo7SYXeTDj27t/Pkf18VqnTt3s5a7e1 ZpYcn8SQePPftPog+Nf5kpTdGdEl9cXogekcP99ngc7dihRW4flYuobw1lN5Y/g0AE/T PzSLZxpRsxaXVmErX/xPCIxtbMvyexMKZG8XQ6RyOF9W/AfiotsvSQni5Vi+aExfghwU nRNQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.43; Mon, 03 Aug 2020 14:01:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729377AbgHCVBl (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:41 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:38453 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729372AbgHCVBk (ORCPT ); Mon, 3 Aug 2020 17:01:40 -0400 Received: by mail-io1-f65.google.com with SMTP id l1so39992207ioh.5; Mon, 03 Aug 2020 14:01:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uqMmmSdRu2mAJmxJVyfdC1UZDoCNddnAHqJmdw3g1qc=; b=kbh/gROR243Odr5WjQNkYijTi8E5dG08IEnI96YhEKNcfAGLtuYLyJD1JIRTiIuD0C CfFzzGHJYBQxl7NtxACRGHxHO0sOfZwFL167qVqyRcbBrSFw9zEOWgHb7TxkkWSyWk5G b8K7uRWRjjoyk2uZpkzEJUtnNr3MX7nuIplrbGhqz6mUJLZYc7DQ7XtZM68w9SrFezSr hbP5INOFlox0Rl4cvwNaBQZY0vZs177aSvGv0RKb4rHjYNNvz7CS1LZEFL1kafsRIJYK SmUUfCjyDTmSG6752X7d0p2IJnkLPj3LjBXD4mud6wmTi5yj+x/77dbQ/mTXnk8qGTc5 O9sg== X-Gm-Message-State: AOAM531wschz0usaKytMHCOCSv7M8xmzDRoMrxgVay8bT4/i59DHRriV u4TH1w3/rP2v4lnXeqcu1g== X-Received: by 2002:a5e:930b:: with SMTP id k11mr1852419iom.30.1596488499811; Mon, 03 Aug 2020 14:01:39 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:39 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 09/27] PCI: dwc: kirin: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:58 -0600 Message-Id: <20200803210116.3132633-10-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the HiSilicon Kirin driver to use the standard pci_ops for root bus config accesses. Cc: Xiaowei Song Cc: Binghui Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-kirin.c | 39 +++++++++++++------------ 1 file changed, 21 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index c19617a912bd..1680dc72b416 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -335,34 +335,37 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); } -static int kirin_pcie_rd_own_conf(struct pcie_port *pp, +static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true); - ret = dw_pcie_read(pci->dbi_base + where, size, val); - kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false); + if (PCI_SLOT(devfn)) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } - return ret; + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; } -static int kirin_pcie_wr_own_conf(struct pcie_port *pp, +static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true); - ret = dw_pcie_write(pci->dbi_base + where, size, val); - kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; - return ret; + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; } +static struct pci_ops kirin_pci_ops = { + .read = kirin_pcie_rd_own_conf, + .write = kirin_pcie_wr_own_conf, +}; + static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) { @@ -428,6 +431,8 @@ static int kirin_pcie_establish_link(struct pcie_port *pp) static int kirin_pcie_host_init(struct pcie_port *pp) { + pp->bridge->ops = &kirin_pci_ops; + kirin_pcie_establish_link(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) @@ -443,8 +448,6 @@ static const struct dw_pcie_ops kirin_dw_pcie_ops = { }; static const struct dw_pcie_host_ops kirin_pcie_host_ops = { - .rd_own_conf = kirin_pcie_rd_own_conf, - .wr_own_conf = kirin_pcie_wr_own_conf, .host_init = kirin_pcie_host_init, }; From patchwork Mon Aug 3 21:00:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247421 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1540683ilo; Mon, 3 Aug 2020 14:03:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy81DErteQQ5cljI1fnfxuM4mNW5jQwfezXaYMMNBLetja3IX/fk5NxQyb9BubFNRVqkHWh X-Received: by 2002:a17:906:3a51:: with SMTP id a17mr18386802ejf.433.1596488506475; Mon, 03 Aug 2020 14:01:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488506; cv=none; d=google.com; s=arc-20160816; b=JpfuKH8s6Bfsj3Djm1l74gd4IBA9Afj0Bg/pX0JZS7ozs+BVh7KrNKaKaMwgZTY8xc 7YbgK5EdYdCud/l1GPuv8H6CfWRF7uV1uEYGzDBbrA36xOBRzRGevkCyNpl/l2fau+1A 4wxUp13Ow7zoVQy6IbtNBRet4nA/UyDI3qt5+puAmk9NemwfTHZp+V4WZTFXO5oqZV+C BWmFhoDmbg1u6SAsIArT4LTwdRHYUjyMajM5Srb02oreDIs3fLOXhaVGHIat2zeqtZsr b/ZTtJxeo1dvpi8CG1o0CX2pbXIm+1Z4ApN9t6pxBnICKZEa11zgb7Aux95Ti7eBSqkg zkcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=w74e1Ztc1qAn6gEbliDEy8D1xkphK6dVWVgtaNcLV4w=; b=L7Y9QyM8D30vW9ELz3R7lv/lHIjqJFhhe9LERdWDFZS4x1p0nDi6LcDAX+9DB04jUG cJCVdS8QPXx03exYuLw6q3eG+xn6/wOCmXGRxWMSA+ZSf2GHl+vwJWRrVzvWdfbmb+b9 IFg7CCroQhjIbHgknVEfMCqMADqn1f75ERx3Tijfq93UC2Jdvgo6WKaIzmuFOVt0rkr4 LlpAbJGK0X+cgJQ65E4by+UrcI2a0VnJ3H+PjPo5LNbrVl+8aEvAiKFpQDwwdmz3z6yV CfWCFBjiuheQfz3LvFflSipo7CcWG8IdskQO3EIjPBWy80UFUj6ya7zqiSHm+zC0u/um +H1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lk20si8340152ejb.703.2020.08.03.14.01.46; Mon, 03 Aug 2020 14:01:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729337AbgHCVBn (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:43 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:38507 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729372AbgHCVBn (ORCPT ); Mon, 3 Aug 2020 17:01:43 -0400 Received: by mail-il1-f194.google.com with SMTP id 77so3879440ilc.5; Mon, 03 Aug 2020 14:01:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w74e1Ztc1qAn6gEbliDEy8D1xkphK6dVWVgtaNcLV4w=; b=q1kAxFAcUcChwZzscN/BtqszSs41IJB+QrwM+exX6dedGv3CStCdg/RVz2KB+JVNTd 4IzBPkm0KWUVoQ4ol9qkscOv5vrBQudfo1+NfI9m0Ie9QPrCbL1FWFvWGIoHbsrrhZ7o Ag1BMDk25H9rYpGDvjxrHwK5Q1JAiPIeymUp/zuRaZisSurn+DxHc1OdJVwfvyMS5LTj emC/ivP3X7FimUFw7DQL9RBvzs7V66EsWDpqY/6jAfE+5Gr+AjZr8iDaNI/egBBWDGJh ZpJSCfRz4Q8V8LarXXLf8Q3BIMjaaxvwFWHCAOIN0zRX4W3u+nA95bg1XdzlcJ8PsIFF FWvw== X-Gm-Message-State: AOAM531GjW4M+HLPRoK3DZq9YUI5T4TS4b27JHPhELLBJo/mJY7g9u+i nC2l1dGg0OPiwySPF6Ii8A== X-Received: by 2002:a92:1b42:: with SMTP id b63mr1415959ilb.76.1596488501865; Mon, 03 Aug 2020 14:01:41 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:41 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 10/27] PCI: dwc: exynos: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:59 -0600 Message-Id: <20200803210116.3132633-11-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Samsung Exynos driver to use the standard pci_ops for root bus config accesses. Cc: Jingoo Han Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-exynos.c | 45 ++++++++++++++----------- 1 file changed, 25 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index c5043d951e80..d5d37cffa441 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -338,32 +338,37 @@ static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, exynos_pcie_sideband_dbi_w_mode(ep, false); } -static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) +static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct exynos_pcie *ep = to_exynos_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - exynos_pcie_sideband_dbi_r_mode(ep, true); - ret = dw_pcie_read(pci->dbi_base + where, size, val); - exynos_pcie_sideband_dbi_r_mode(ep, false); - return ret; + if (PCI_SLOT(devfn)) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; } -static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) +static int exynos_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct exynos_pcie *ep = to_exynos_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - exynos_pcie_sideband_dbi_w_mode(ep, true); - ret = dw_pcie_write(pci->dbi_base + where, size, val); - exynos_pcie_sideband_dbi_w_mode(ep, false); - return ret; + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; } +static struct pci_ops exynos_pci_ops = { + .read = exynos_pcie_rd_own_conf, + .write = exynos_pcie_wr_own_conf, +}; + static int exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep = to_exynos_pcie(pci); @@ -381,6 +386,8 @@ static int exynos_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct exynos_pcie *ep = to_exynos_pcie(pci); + pp->bridge->ops = &exynos_pci_ops; + exynos_pcie_establish_link(ep); exynos_pcie_enable_interrupts(ep); @@ -388,8 +395,6 @@ static int exynos_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops exynos_pcie_host_ops = { - .rd_own_conf = exynos_pcie_rd_own_conf, - .wr_own_conf = exynos_pcie_wr_own_conf, .host_init = exynos_pcie_host_init, }; From patchwork Mon Aug 3 21:01:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 257459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7E66C4345D for ; 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Mon, 03 Aug 2020 14:01:51 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 13/27] PCI: dwc: Use generic config accessors Date: Mon, 3 Aug 2020 15:01:02 -0600 Message-Id: <20200803210116.3132633-14-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Now that all the platforms with custom config access handling define their own pci_ops, let's split the default config accessors to use different pci_ops for root and child buses. With this, we can use the generic config accessors. The child bus accesses mainly require a .map_bus() hook to reconfigure the iATU on each config space access. BTW, if there are only 2 viewports which means config space and I/O accesses are mutually exclusive because the iATU window is shared, how are accesses serialized? That seems broken... Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 120 ++++++------------ 1 file changed, 42 insertions(+), 78 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6e9f106e8e05..e9778f8ee955 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -20,24 +20,7 @@ #include "pcie-designware.h" static struct pci_ops dw_pcie_ops; - -static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) -{ - struct dw_pcie *pci; - - pci = to_dw_pcie_from_pp(pp); - return dw_pcie_read(pci->dbi_base + where, size, val); -} - -static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) -{ - struct dw_pcie *pci; - - pci = to_dw_pcie_from_pp(pp); - return dw_pcie_write(pci->dbi_base + where, size, val); -} +static struct pci_ops dw_child_pcie_ops; static void dw_msi_ack_irq(struct irq_data *d) { @@ -448,7 +431,7 @@ int dw_pcie_host_init(struct pcie_port *pp) /* Set default bus ops */ bridge->ops = &dw_pcie_ops; - bridge->child_ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; if (pp->ops->host_init) { ret = pp->ops->host_init(pp); @@ -498,14 +481,14 @@ void dw_pcie_host_deinit(struct pcie_port *pp) } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); -static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val, - bool write) +static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) { - int ret, type; + int type; u32 busdev, cfg_size; u64 cpu_addr; void __iomem *va_cfg_base; + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | @@ -526,79 +509,59 @@ static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - if (write) - ret = dw_pcie_write(va_cfg_base + where, size, *val); - else - ret = dw_pcie_read(va_cfg_base + where, size, val); - if (pci->num_viewport <= 2) - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_IO, pp->io_base, - pp->io_bus_addr, pp->io_size); - - return ret; -} - -static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) -{ - return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val, - false); + return va_cfg_base + where; } -static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 val) -{ - return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val, - true); -} - -static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, - int dev) +static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) { + int ret; + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - /* If there is no link, then there is no device */ - if (bus->number != pp->root_bus_nr) { - if (!dw_pcie_link_up(pci)) - return 0; - } + ret = pci_generic_config_read(bus, devfn, where, size, val); - /* Access only one slot on each root port */ - if (bus->number == pp->root_bus_nr && dev > 0) - return 0; + if (!ret && pci->num_viewport <= 2) + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, pp->io_base, + pp->io_bus_addr, pp->io_size); - return 1; + return ret; } -static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) +static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { + int ret; struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } + ret = pci_generic_config_write(bus, devfn, where, size, val); - if (bus->number == pp->root_bus_nr) - return dw_pcie_rd_own_conf(pp, where, size, val); + if (!ret && pci->num_viewport <= 2) + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, pp->io_base, + pp->io_bus_addr, pp->io_size); - return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); + return ret; } -static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) +static struct pci_ops dw_child_pcie_ops = { + .map_bus = dw_pcie_other_conf_map_bus, + .read = dw_pcie_rd_other_conf, + .write = dw_pcie_wr_other_conf, +}; + +void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (bus->number == pp->root_bus_nr) - return dw_pcie_wr_own_conf(pp, where, size, val); + if (PCI_SLOT(devfn) > 0) + return NULL; - return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); + return pci->dbi_base + where; } void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) @@ -613,8 +576,9 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } static struct pci_ops dw_pcie_ops = { - .read = dw_pcie_rd_conf, - .write = dw_pcie_wr_conf, + .map_bus = dw_pcie_own_conf_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, }; void dw_pcie_setup_rc(struct pcie_port *pp) @@ -673,7 +637,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * the platform uses its own address translation component rather than * ATU, so we should not program the ATU here. */ - if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) { + if (pp->bridge->child_ops == &dw_child_pcie_ops) { dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); From patchwork Mon Aug 3 21:01:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247408 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539709ilo; Mon, 3 Aug 2020 14:01:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzbTvBsngzbanlwwPc4SVIaMso0MRb+r9uioe7OX15UPbqI+juH9KdSkUjGFrh5YxOuDXb X-Received: by 2002:a17:906:998f:: with SMTP id af15mr17726797ejc.461.1596488517662; Mon, 03 Aug 2020 14:01:57 -0700 (PDT) ARC-Seal: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id i2si9818208ejp.500.2020.08.03.14.01.57; Mon, 03 Aug 2020 14:01:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729400AbgHCVB5 (ORCPT + 4 others); Mon, 3 Aug 2020 17:01:57 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:46757 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVB4 (ORCPT ); Mon, 3 Aug 2020 17:01:56 -0400 Received: by mail-io1-f68.google.com with SMTP id a5so24746443ioa.13; Mon, 03 Aug 2020 14:01:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aFafu+8WFYxvnK2ZfkQMV1ef4S4ilss7PqKLS2/JE9Q=; b=ipXeKRH+xqu0EHK9jtgf5Niv5ypGpvAs060+j9cftbVi4H/bRDhG4/dVGwvVx5JEuZ DI8dw9dThv7cLhacTBNq92rxLY3Qqzoh7rfMF94qLt0ZxFvI+9CllvwmSmmOfiyxrbey XSR3bKBJrznxUu0TYsNwB3gPWLoYuOjwEfokUuErIleQ5er6evK2ZczBC0MhtDIcydGY 0tpmW9/iqdtVlm5bhCpV4bTutf2+AyvM9vtv87nTcn9fLvkBTIoQNCSmY9hDepk/ZxV+ rm/7YMm/SApcwCfSmiEbTa5V91g1z66Tlxjjaxc0/D9V1WAEmj8TKwUtzTmMogD6gSMs ZS0w== X-Gm-Message-State: AOAM531oYEUOpJwzwHi58YBqEG0jGT3S7IVM90Y0Px592R0fgDjnsWv6 3rF5j1EwrwocnDZnjOd3cA== X-Received: by 2002:a5d:87c9:: with SMTP id q9mr1812686ios.113.1596488515619; Mon, 03 Aug 2020 14:01:55 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:55 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 14/27] PCI: Also call .add_bus() callback for root bus Date: Mon, 3 Aug 2020 15:01:03 -0600 Message-Id: <20200803210116.3132633-15-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Similar to pcibios_add_bus(), call pci_ops.add_bus() when the root bus is added. This allows host bridge drivers to do any setup requiring a bus pointer. There are currently no .add_bus() callbacks, so this is safe to do. Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/probe.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.25.1 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 8712e595174d..337a3b7766ca 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -935,6 +935,12 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge) pcibios_add_bus(bus); + if (bus->ops->add_bus) { + err = bus->ops->add_bus(bus); + if (WARN_ON(err < 0)) + dev_err(&bus->dev, "failed to add bus: %d\n", err); + } + /* Create legacy_io and legacy_mem files for this bus */ pci_create_legacy_files(bus); From patchwork Mon Aug 3 21:01:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247409 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539755ilo; Mon, 3 Aug 2020 14:02:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMM2ZAstEjp6yjA/UUA1B6WVgpx1zgScGwKxgAEXXnOZfYqDOJ4AvcRrJWSZPzK5yi+G6F X-Received: by 2002:a05:6402:3128:: with SMTP id dd8mr7472032edb.97.1596488521038; Mon, 03 Aug 2020 14:02:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488521; cv=none; d=google.com; s=arc-20160816; b=WeaJna7W0vP0Kad5fp5jlotWP4TxVvoT9ExZJGSJHl4vNcVjx8iJovDLyApH4LYzi+ xXdrPbfay4FnBV4daWvA9NHPpkbY438XgAUlmxF5IX3oo5rUAXLLAO2Bw7cSfYCSPgKU j7CgNI1+VxN47l2VPW7sYpul1kqdz5wlP2UA/CiOiIpuZpJOOmujOlJG6USWOVclVff5 MPQnnemQChsUyy0nbHEX4/1hT3jr26K3vYuPVeVq/eh3fbrFveOhm1tfEsCjVthd+ECN kFNwjJO3r3rELTxyFQLYsiNT/sVXJW1KQddG9qRuwjAZtl8X1GXX/+j/dVOgUyvyvZmK uTLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=+G09sVWmLiEk+qlmhnIPsi/B/n4JiVilLbMwDzTJ8Fc=; b=b6LXZG+UJzE2PH9vaAOAwR6YIq5vN7F1XRIpwt/1f54S/+MsLaAYIGiF8gREYkbNM4 8xR/40mBovcPIlADKR0WlqjBp6oQKMa5uYkoHXE6VFYXIbrBxAS0GW8pEI8WKLrQP2Wx pt2p1sfox/5I3j1Zhz99tPaaRIGoiVnkIGv//p3QecKmOlRKrexdIp9YQ++kJGZ/x2Qt i18ZNcKfvwxVIdax4h1fOBnnITIRh2vBJe9TAS6mcvI0D+YtlFJAoecYt+5cjATWkcDS 48FsLog7XQkX5m62A/uAl5I9SoDCXN5q8auIvKdrFCsNVpKyPMN3fKZVvUAPxOgf2Hg2 GLKg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i2si9818208ejp.500.2020.08.03.14.02.00; Mon, 03 Aug 2020 14:02:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729403AbgHCVCA (ORCPT + 4 others); Mon, 3 Aug 2020 17:02:00 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:45747 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVCA (ORCPT ); Mon, 3 Aug 2020 17:02:00 -0400 Received: by mail-io1-f66.google.com with SMTP id u126so2718395iod.12; Mon, 03 Aug 2020 14:01:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+G09sVWmLiEk+qlmhnIPsi/B/n4JiVilLbMwDzTJ8Fc=; b=PaoWVWjJPXhqL4kgjd3GLb0n3DyC2PeyL+cfvdOJEGt8nunuxRHj2H5NQ9PSdaxTnM oHEeOiK1lAtlgw6N+pXTQhsFucGqIo5dC1ab+c7oyD+IIuyk96GMq4ohyLSI+YE+E5+N EyjUO165ow6j8kEUf+ZAaGTwwzkNmIOTdmzyX9cjlibmB6iSMj1ezTVwQd5lMYN1xxA9 i57z+MDAtmdkmOyFt2MYO5+A1+AokobryHc89++mOOFuajqBZIMU7jPgoj+NEZ6sg/Ql 5b03x00Gk8/Q5MhR83hg5b/IzROudK5Y0fNuIEcdJXpmlpu0s3SA51cCp8tUyE0wWJTV q6kQ== X-Gm-Message-State: AOAM530l8j86JMGgWWVQ1mB5HyjTi6Dwzga5Z8VGxyLlZdGkB8FHfvaW 82hSUIwIq+E0JBITbt6P4g== X-Received: by 2002:a5e:c311:: with SMTP id a17mr1821353iok.12.1596488518872; Mon, 03 Aug 2020 14:01:58 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:58 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 15/27] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Date: Mon, 3 Aug 2020 15:01:04 -0600 Message-Id: <20200803210116.3132633-16-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org TI keystone is the only Designware driver using .scan_bus(). This function pointer is the only thing preventing the Designware driver from using pci_host_probe(). Let's use the pci_ops.add_bus hook instead. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index df1194d186bc..17271b21fb7d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -454,15 +454,19 @@ static struct pci_ops ks_child_pcie_ops = { }; /** - * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization + * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization * * This sets BAR0 to enable inbound access for MSI_IRQ register */ -static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) +static int ks_pcie_v3_65_add_bus(struct pci_bus *bus) { + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + if (!pci_is_root_bus(bus)) + return 0; + /* Configure and set up BAR0 */ ks_pcie_set_dbi_mode(ks_pcie); @@ -477,12 +481,15 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) * be sufficient. Use physical address to avoid any conflicts. */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); + + return 0; } static struct pci_ops ks_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, + .add_bus = ks_pcie_v3_65_add_bus, }; /** @@ -842,7 +849,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) static const struct dw_pcie_host_ops ks_pcie_host_ops = { .host_init = ks_pcie_host_init, .msi_host_init = ks_pcie_msi_host_init, - .scan_bus = ks_pcie_v3_65_scan_bus, }; static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { From patchwork Mon Aug 3 21:01:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247411 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1539825ilo; Mon, 3 Aug 2020 14:02:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKq/ANQzhy0RbGREelBNcPZ2qv7bjiGxXpz3RADoF9Y43QxoYblaAfvXz71oUhf9nEpGRO X-Received: by 2002:a17:906:9382:: with SMTP id l2mr17925402ejx.513.1596488526314; Mon, 03 Aug 2020 14:02:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488526; cv=none; d=google.com; s=arc-20160816; b=gU9QUVJxjRgQ3p9XTL5vqtGS1BM7DCKgejCYVAFxsdKfvrp9nc6NHI5ehFMVeXrYJX OisR8KEIbcHnzFd/FrOwdeTpl5TL/3MIH0+xXWrPRP1MWyjbA/XQ8Ji7kWv1kcbBLUuz ciGYoffPtMnctMKXj3JwE75zQCs0dLWgOcWSQ129ZG+1L/eMXup9vBqrFMlQDmx77taW zR2TGS7iTnD5D3K0HHD9LWWehfjr1HD3PgegXfU7jfRdzGg+Be7kzg5Jc1lI1lEpxnH3 b8hXNFtwU//Js1lMkysKqCX31rv+9bpxBDUGIaSUoWqmtsyP51CpigSCzKjQL6igwKn+ rJKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=KBszrZoR6KfV8PIUJ9TAD0pOH/WhVXS7vLHSzuibxQI=; b=x36uNz1xPPSWXzQ0qBPgGZ/nY+LG181plrdeBgXf2WPAOrIY6ckVex73Ru/26nyYQ6 U4AZ4CCWmgIC+l46I0TxlTe96rR+HaTsJTKpIGsTbIDzWa2qDfnbFxyduBzfjN4jv2op POjOIY/hNgPe27Nk9RKBFnkkSa8jlwynlEXEyUuKdvh11sq6KAKUv3LPePem7ftyhVtL jFzYS8r9xPUerbAhIwSXSpAdSFQy1p/SD41G1bxAA1R2QQZCZdvLBqiXTkIdMpfS6792 MdguiJZWk6JqPQFcuaho8jNq42TBCrpwmqUXykPkuIgh106rT+DdFmgyB+ySqVJ8dNva ZzDg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i2si9818208ejp.500.2020.08.03.14.02.06; Mon, 03 Aug 2020 14:02:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729084AbgHCVCF (ORCPT + 4 others); Mon, 3 Aug 2020 17:02:05 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:34380 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVCE (ORCPT ); Mon, 3 Aug 2020 17:02:04 -0400 Received: by mail-io1-f68.google.com with SMTP id q75so31850951iod.1; Mon, 03 Aug 2020 14:02:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KBszrZoR6KfV8PIUJ9TAD0pOH/WhVXS7vLHSzuibxQI=; b=ffSv2U+0W36NH6O2luIDvOWR8rQ5f6KQdv6yLauVEdpvgY9XDZhwMtgtSk9Qr6oui1 1Bibbh+6z+H2lu5/iPlIvTbwmYFWGJVMjaLaIDtpx3L/FO3F/+mF2bH5nQTBjmF5+s/K x5OK63at196Y6YSe5F6D/m/+gr9R9vDEHBvq+XU6kf4Fai7CCrBD5443gdy/cIPNbJEK fur2ALfcEFlhml8TR5JcWWTGftorAJPr185dHYAboKts7WHUNh2i93H+3dWCGrTkO6g9 avkQMcv7x7T/BRIgHFKfYpkaxXrFbQZoHEb9tTL34POm1+PInluifixn0xTDhl28nSwO cCzg== X-Gm-Message-State: AOAM5333mMj0LTHl4gN2XVM98/xarue34ziXkGv/LQwjIgiDho8ywhYV +JTrlIFgLBl0IFUjJ7eW9Q== X-Received: by 2002:a02:c735:: with SMTP id h21mr1877476jao.90.1596488523308; Mon, 03 Aug 2020 14:02:03 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:02 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 17/27] PCI: dwc: Remove root_bus pointer Date: Mon, 3 Aug 2020 15:01:06 -0600 Message-Id: <20200803210116.3132633-18-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The pci_host_bridge struct already has a pointer to its pci_bus, so let's convert the one user to use the bridge struct and remove the private 'root_bus' pointer. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.h | 1 - drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index dc336163104a..9528c8b1c9ab 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -459,8 +459,8 @@ EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { - pci_stop_root_bus(pp->root_bus); - pci_remove_root_bus(pp->root_bus); + pci_stop_root_bus(pp->bridge->bus); + pci_remove_root_bus(pp->bridge->bus); if (pci_msi_enabled() && !pp->ops->msi_host_init) dw_pcie_free_msi(pp); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 10d22269254a..67aac6fdca24 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -193,7 +193,6 @@ struct pcie_port { struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; - struct pci_bus *root_bus; struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 52bb145c42d1..c567c9c09ff6 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1264,9 +1264,9 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) * 5.2 Link State Power Management (Page #428). */ - list_for_each_entry(child, &pp->root_bus->children, node) { + list_for_each_entry(child, &pp->bridge->bus->children, node) { /* Bring downstream devices to D0 if they are not already in */ - if (child->parent == pp->root_bus) { + if (child->parent == pp->bridge->bus) { root_bus = child; break; } From patchwork Mon Aug 3 21:01:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 257456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28F2EC433E0 for ; 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Mon, 03 Aug 2020 14:02:07 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 19/27] PCI: dwc: Simplify config space handling Date: Mon, 3 Aug 2020 15:01:08 -0600 Message-Id: <20200803210116.3132633-20-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The config space is divided in half for type 0 and type 1 accesses, but this is pointless as there's only one iATU window which is reconfigured on each access. The only platform doing something custom is TI Keystone (surprise!). It does its own mapping of the config space to avoid spliting the config space and never actually uses va_cfg1_base as it has its own config space accessors. With the splitting removed, Keystone can use the default mapping of config space. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Gustavo Pimentel Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 8 --- .../pci/controller/dwc/pcie-designware-host.c | 63 ++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 4 -- 3 files changed, 20 insertions(+), 55 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index bdf4fe1fc822..e9028c98d6c0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -873,16 +873,8 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; - struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); - - pp->va_cfg1_base = pp->va_cfg0_base; - ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a981e9de81d7..1ff4702595b6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -308,10 +308,8 @@ int dw_pcie_host_init(struct pcie_port *pp) cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (cfg_res) { - pp->cfg0_size = resource_size(cfg_res) >> 1; - pp->cfg1_size = resource_size(cfg_res) >> 1; + pp->cfg0_size = resource_size(cfg_res); pp->cfg0_base = cfg_res->start; - pp->cfg1_base = cfg_res->start + pp->cfg0_size; } else if (!pp->va_cfg0_base) { dev_err(dev, "Missing *config* reg space\n"); } @@ -336,25 +334,22 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->io_base = pci_pio_to_address(win->res->start); break; case 0: - pp->cfg = win->res; - pp->cfg0_size = resource_size(pp->cfg) >> 1; - pp->cfg1_size = resource_size(pp->cfg) >> 1; - pp->cfg0_base = pp->cfg->start; - pp->cfg1_base = pp->cfg->start + pp->cfg0_size; + dev_err(dev, "Missing *config* reg space\n"); + pp->cfg0_size = resource_size(win->res); + pp->cfg0_base = win->res->start; + if (!pci->dbi_base) { + pci->dbi_base = devm_pci_remap_cfgspace(dev, + pp->cfg0_base, + pp->cfg0_size); + if (!pci->dbi_base) { + dev_err(dev, "Error with ioremap\n"); + return -ENOMEM; + } + } break; } } - if (!pci->dbi_base) { - pci->dbi_base = devm_pci_remap_cfgspace(dev, - pp->cfg->start, - resource_size(pp->cfg)); - if (!pci->dbi_base) { - dev_err(dev, "Error with ioremap\n"); - return -ENOMEM; - } - } - if (!pp->va_cfg0_base) { pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, pp->cfg0_base, pp->cfg0_size); @@ -364,16 +359,6 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - if (!pp->va_cfg1_base) { - pp->va_cfg1_base = devm_pci_remap_cfgspace(dev, - pp->cfg1_base, - pp->cfg1_size); - if (!pp->va_cfg1_base) { - dev_err(dev, "Error with ioremap\n"); - return -ENOMEM; - } - } - ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); if (ret) pci->num_viewport = 2; @@ -455,32 +440,24 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { int type; - u32 busdev, cfg_size; - u64 cpu_addr; - void __iomem *va_cfg_base; + u32 busdev; struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | PCIE_ATU_FUNC(PCI_FUNC(devfn)); - if (bus->parent->number == pp->root_bus_nr) { + if (bus->parent->number == pp->root_bus_nr) type = PCIE_ATU_TYPE_CFG0; - cpu_addr = pp->cfg0_base; - cfg_size = pp->cfg0_size; - va_cfg_base = pp->va_cfg0_base; - } else { + else type = PCIE_ATU_TYPE_CFG1; - cpu_addr = pp->cfg1_base; - cfg_size = pp->cfg1_size; - va_cfg_base = pp->va_cfg1_base; - } + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, - type, cpu_addr, - busdev, cfg_size); + type, pp->cfg0_size, + busdev, pp->cfg0_size); - return va_cfg_base + where; + return pp->va_cfg0_base + where; } static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 3d552ec8a850..2db6f52dfe81 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -170,13 +170,9 @@ struct pcie_port { u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size; - u64 cfg1_base; - void __iomem *va_cfg1_base; - u32 cfg1_size; resource_size_t io_base; phys_addr_t io_bus_addr; u32 io_size; - struct resource *cfg; int irq; const struct dw_pcie_host_ops *ops; int msi_irq; From patchwork Mon Aug 3 21:01:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 257455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19B2AC43458 for ; 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Mon, 03 Aug 2020 14:02:13 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Andy Gross Subject: [RFC 21/27] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Date: Mon, 3 Aug 2020 15:01:10 -0600 Message-Id: <20200803210116.3132633-22-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Move the IS_ENABLED(CONFIG_PCI_MSI) check into dw_pcie_msi_init() instead of duplicating it in all the drivers. Cc: Richard Zhu Cc: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Yue Wang Cc: Kevin Hilman Cc: Jesper Nilsson Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Xiaowei Song Cc: Binghui Wang Cc: Stanimir Varbanov Cc: Andy Gross Cc: Bjorn Andersson Cc: Kunihiko Hayashi Cc: Masahiro Yamada Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@axis.com Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-imx6.c | 4 +--- drivers/pci/controller/dwc/pci-meson.c | 8 +------- drivers/pci/controller/dwc/pcie-artpec6.c | 11 +---------- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware-plat.c | 4 +--- drivers/pci/controller/dwc/pcie-histb.c | 4 +--- drivers/pci/controller/dwc/pcie-kirin.c | 4 +--- drivers/pci/controller/dwc/pcie-qcom.c | 4 +--- drivers/pci/controller/dwc/pcie-uniphier.c | 3 +-- 9 files changed, 11 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8f08ae53f53e..7b526f4f85ce 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -847,9 +847,7 @@ static int imx6_pcie_host_init(struct pcie_port *pp) imx6_setup_phy_mpll(imx6_pcie); dw_pcie_setup_rc(pp); imx6_pcie_establish_link(imx6_pcie); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index 54ce3369d963..cbde683d107f 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -377,12 +377,6 @@ static int meson_pcie_establish_link(struct meson_pcie *mp) return dw_pcie_wait_for_link(pci); } -static void meson_pcie_enable_interrupts(struct meson_pcie *mp) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(&mp->pci.pp); -} - static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { @@ -466,7 +460,7 @@ static int meson_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - meson_pcie_enable_interrupts(mp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index 28d5a1095200..969f217c5675 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -346,15 +346,6 @@ static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie) usleep_range(100, 200); } -static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie) -{ - struct dw_pcie *pci = artpec6_pcie->pci; - struct pcie_port *pp = &pci->pp; - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); -} - static int artpec6_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -368,7 +359,7 @@ static int artpec6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); artpec6_pcie_establish_link(pci); dw_pcie_wait_for_link(pci); - artpec6_pcie_enable_interrupts(artpec6_pcie); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 1ff4702595b6..0e62bed7f6cb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -276,6 +276,9 @@ void dw_pcie_msi_init(struct pcie_port *pp) struct device *dev = pci->dev; u64 msi_target; + if (!IS_ENABLED(CONFIG_PCI_MSI)) + return; + pp->msi_page = alloc_page(GFP_KERNEL); pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE, DMA_FROM_DEVICE); diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 73646b677aff..4990cd010983 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -39,9 +39,7 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); dw_pcie_wait_for_link(pci); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index 0d93088deea3..c97c37c6314e 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -202,9 +202,7 @@ static int histb_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &histb_pci_ops; histb_pcie_establish_link(pp); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 1680dc72b416..0be17db42f56 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -434,9 +434,7 @@ static int kirin_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &kirin_pci_ops; kirin_pcie_establish_link(pp); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 138e1a2d21cc..9f1d3ba686fa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1237,9 +1237,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) } dw_pcie_setup_rc(pp); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); qcom_ep_reset_deassert(pcie); diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index a5401a0b1e58..07ba2d833941 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -322,8 +322,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } From patchwork Mon Aug 3 21:01:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247415 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1540045ilo; Mon, 3 Aug 2020 14:02:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxR7ObSiiqRqV/GrjJtK/zxZP/9bS9zrYxbi+ZCfiVuHTGymrYgXPR9H3UFnWYTTKJGFzMr X-Received: by 2002:a17:906:1455:: with SMTP id q21mr18167694ejc.139.1596488540520; Mon, 03 Aug 2020 14:02:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488540; cv=none; d=google.com; s=arc-20160816; b=kY1O9sPMUalN7Js04CO23ttlbTkQvt7wxQeY+Bnv4dKYLZE3UbQqBk0tLWhlzVjgCu qPvS5BR5UGFP229k+QYVDA9EJR+JCyxqv3s1GQhzDkGdUopFBCadrInuPoId7NJE7ZH2 dTxsKsKEZYP5QXdzWNCgGgM0eDWbxZA6w808HvnwXJYbtcx9TyHisRDh8/g/vvPhkgIk zQZ4bWSw96v1AAkGbMwWKsf3BuYe0aNCjTX6lKRNumUAz1i9mu3JQjhZuccsZQN/G1Ob blQtB6ikMMcnKCwi7b5Wv8jYtRDwuNe1wHPzuEZZtDp+opVZvfTuwAwtlJQXs59HhxOk zGrQ== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id a16si11728729ejk.194.2020.08.03.14.02.20; Mon, 03 Aug 2020 14:02:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729460AbgHCVCT (ORCPT + 4 others); Mon, 3 Aug 2020 17:02:19 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:45789 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCS (ORCPT ); Mon, 3 Aug 2020 17:02:18 -0400 Received: by mail-io1-f65.google.com with SMTP id u126so2719389iod.12; Mon, 03 Aug 2020 14:02:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yeVh4LY4Ol0sFEbqSsJcffa7f//z27paKHgfSp0xtxI=; b=PRxnPLGjDqHtLZhyyfH0d3hVBWgx6ENJDH2v8rbBdzDz8WvI2bv3DxRsayKghBvaLr et58lDEMVgpvs9peb7FXlDYGNJpHfz6VTdjV5cf3Ktqy5XhITlEQ15Cdwg/vfhg6bBWC KKN/aeiPF54OSzB9/qiQLjGrONIKjt5BupoGzFkujXOo7y4Q318vSuxKWVVaFyeRP8Ce c3rnc6e2fYknq2FcW75uu9Txm8LZ8fslt2H4nAJhP30/gVRjrAelNGdRCfJ7+AUq7vOK 3Mx5px8snzwGRqyw6/PRk+hDSC9kZ6K4N+Dj/EerPkIm5RJTx18LN40CMy+VVlIjZzLm 0SkA== X-Gm-Message-State: AOAM532dXE+PdD82jUDZ0HDBO2ET4azXc2YfWsOQAEHh8lgklpbDm26H ptF4uHxeQEbkNywjVr7ybA== X-Received: by 2002:a5e:c30f:: with SMTP id a15mr1845040iok.184.1596488537676; Mon, 03 Aug 2020 14:02:17 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:17 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 22/27] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Date: Mon, 3 Aug 2020 15:01:11 -0600 Message-Id: <20200803210116.3132633-23-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org PCIE_LINK_WIDTH_SPEED_CONTROL is already defined in pcie-designware.h, so remove it from the i.MX6 driver. Cc: Richard Zhu Cc: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-imx6.c | 2 -- 1 file changed, 2 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 7b526f4f85ce..64e694f04dce 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -116,8 +116,6 @@ struct imx6_pcie { #define PCIE_PHY_STAT (PL_OFFSET + 0x110) #define PCIE_PHY_STAT_ACK BIT(16) -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C - /* PHY registers (not memory-mapped) */ #define PCIE_PHY_ATEOVRD 0x10 #define PCIE_PHY_ATEOVRD_EN BIT(2) From patchwork Mon Aug 3 21:01:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247416 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1540122ilo; Mon, 3 Aug 2020 14:02:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtzXP9HGbmLwBhhboXEUb3OXtPoyes9/2hIqQ76TQOqHw92Cq97Kz+eAOg1c/9VKUVgu+E X-Received: by 2002:a17:906:24d0:: with SMTP id f16mr17964669ejb.325.1596488545848; Mon, 03 Aug 2020 14:02:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488545; cv=none; d=google.com; s=arc-20160816; b=xFfRQtb9rlHpm1nwlyh9chbjOrfGzytFUmQjXI86zJqdwtUy+yGhFUv/LNnwgk8PNy lWbok0bAxP9Wr8i+IGfOTpnN7EMZfSdyctS1IZ3wP3/U9fkzOlVr5lIW8OfjGoZJX8LX xASvgj6/stwA7oe5/e56h6z7M83/rT4/Ke41VvznrlakypfEcz908ZTqRTyx7s1ghA5P dTwk2OYUpJddJlX0vMmVYxrfnK6vZIvYUlhTD6e09+fhdrdHFnCTboZE76R/2YhyNKWb kJqLrh+CQLXsPk+JlnDkID8bSUUdYxIXSozR5AMVa36x4J010aErie/n+0pIoT884eyE kRKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=bEN9vVsE3mU2Nyqo3uVsRwOE6mBebuJzlr8xG6a6d4M=; b=iUx1+bjQ4OQj4S43n5OjSPRaPGzgg8YFqerMlSUjs9UMSA4Z42lKPN23yIFYWKGMB+ hIPGmjthzTddvzGaBu+Sm0xB6b/4RCJgDNSYVD5SDhN1x1gE6t4cbNEiMQXDImi3S035 ICj41w9eWA/edF2UKvpU5zQsKgzkY6PRf6NSRByyEu8xaHg3v4VZhh2Emtvllwx/XFiy lqmdG8CYw7UzAfVzXtttg/dBE6voBjLf1Cp9XDGUOwRCZYqxtQEk3PfBGJnF45ub80V+ Vp80YB5Rx/bNSMfFxnYysqm+sxGJ0aJzvstW/eIvwQhBURVVHKKnzsjAJZgKHMHdQNJX ieVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id rl26si3871175ejb.568.2020.08.03.14.02.25; Mon, 03 Aug 2020 14:02:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729466AbgHCVCY (ORCPT + 4 others); Mon, 3 Aug 2020 17:02:24 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:33153 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729103AbgHCVCW (ORCPT ); Mon, 3 Aug 2020 17:02:22 -0400 Received: by mail-io1-f65.google.com with SMTP id g14so2509436iom.0; Mon, 03 Aug 2020 14:02:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bEN9vVsE3mU2Nyqo3uVsRwOE6mBebuJzlr8xG6a6d4M=; b=gvlZ85rNLI4mgSE7YxG4Q0KiemuST2J48lyVHCiY+PD/HkVNhJJeVF9iNU9j+8IQmA m7RZlm8jqvU/xvqtd9qXD3jCxIEGFPXJ215cUFJZfmk7q85O+SWGeLcYhRozUKOQB20E 3lypsIO/PIMIq6wFTTqsMH8smaBVIeAccdeOcp1p34QjkYuYMDjxMW/QhzyQ/aFpV+zs BcIdQWmrsFL08Tj8HKJ5T9IntAeb0VAgtM72j92rAc0ek4lZBlfUIR4zVOJT0xudrgrI ggu+PN1ng44B7cXiAICRF/sdUdyK8LwW5IllpxmaZ/yMl3XwfymoyW80U2tB3qWjQViJ 6Fow== X-Gm-Message-State: AOAM532rDbMpmjaGbpD+D13MkBENq9zkSYqmBgywDILaw+rD5kp1SKuA HVVY1x77VoWi1WEwiT7ong== X-Received: by 2002:a02:a584:: with SMTP id b4mr1758886jam.68.1596488541762; Mon, 03 Aug 2020 14:02:21 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:21 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 23/27] PCI: dwc/meson: Drop unnecessary RC config space initialization Date: Mon, 3 Aug 2020 15:01:12 -0600 Message-Id: <20200803210116.3132633-24-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The common Designware init already initializes the RC PCI_COMMAND, BAR0 and BAR1 registers. The only difference here is the common code sets SERR. If clearing SERR is what's desired, then the Meson driver should do that instead. Cc: Yue Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Kevin Hilman Cc: linux-pci@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-meson.c | 20 -------------------- 1 file changed, 20 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index cbde683d107f..d1cfc65f0a69 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -34,15 +34,6 @@ #define NUM_OF_LANES_X1 BIT(8) #define DIRECT_SPEED_CHANGE BIT(17) -#define TYPE1_HDR_OFFSET 0x0 -#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) -#define PCI_IO_EN BIT(0) -#define PCI_MEM_SPACE_EN BIT(1) -#define PCI_BUS_MASTER_EN BIT(2) - -#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) -#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) - #define PCIE_CAP_OFFSET 0x70 #define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) #define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) @@ -303,9 +294,6 @@ static void meson_pcie_init_dw(struct meson_pcie *mp) val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE; meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); - - meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0); - meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1); } static int meson_size_to_payload(struct meson_pcie *mp, int size) @@ -353,13 +341,6 @@ static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); } -static inline void meson_enable_memory_space(struct meson_pcie *mp) -{ - /* Set the RC Bus Master, Memory Space and I/O Space enables */ - meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN, - PCIE_STATUS_COMMAND); -} - static int meson_pcie_establish_link(struct meson_pcie *mp) { struct dw_pcie *pci = &mp->pci; @@ -370,7 +351,6 @@ static int meson_pcie_establish_link(struct meson_pcie *mp) meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); dw_pcie_setup_rc(pp); - meson_enable_memory_space(mp); meson_pcie_assert_reset(mp); From patchwork Mon Aug 3 21:01:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247418 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1540238ilo; Mon, 3 Aug 2020 14:02:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHF5cvp7COP5EsL1X5gsFPf67QznBNDgRDUg2Ox7JvLzEQdpsEEbRKVAP3gYsN9Cejs8jg X-Received: by 2002:a17:906:1402:: with SMTP id p2mr17846881ejc.126.1596488553015; Mon, 03 Aug 2020 14:02:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488553; cv=none; d=google.com; s=arc-20160816; b=a4jf34Lydj4uOFcAIYgnR49oh4AJhTaeP/O/l/MqXpLa2O0WdseFrrYqjpJRDyzHke jIDsocdySIcMxK3g1y9ylzTXh5CqHSkYimc5rEws1VJkJj/NGDWFwGxSnMy7rd+tHT/+ bAm38FlNVjT7AarmyAaj9zYK4vgX10QRC4N/IYQ+cEO/vbmDArOmNY5F2PAaar38xjeH 6brziqhHf3oHX17LhoUbutP3QK79q3SxhWmYz3Vo5Mjl6LJtu1EaCh/Dg/g+2FdYw15y FXjLKXC9UTxVWa96pK2fgJx7uwlyo0iTlUPE2meJ2EIb26uoqOLiQw2jJ4aWVeEpqe/N IZoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=VwFTr4t0lrmNy8f4Fgv3/l49uahHgczW7Wdy7hSwZ1w=; b=RLoSHXyHo/3SV41DLnt9hPaMrwBvn76aZ1eWuaPmP++E6jVuelHlRKlt6Gg+nNlh3A OkA37Z+xvWs1H+fKVYoKG4xTMEbl/SKBo3cWCF3gT/hAUFgw74iaUz0d9+YxqiSG/zFa Y8u9m2Bbrn3sqbUFVEEJHvgEUqboKYifAtwXq5uy+erIIFTIr2Sb5jDGdbBIR/r93hjd gEw/SccPXQ4fsZ+/m1GLaZiz/hqpVXz0L/j0DJ/ixvGNwSyfcNWEb7TjqlSsaHZUpE6J Oshb7r8z4G0bKa91KZ6PNFNpq/xjeOqQuGYDxZj1y/UttBWgipGH4fXhKp9Cm79PdDbm Epaw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id rl26si3871175ejb.568.2020.08.03.14.02.32; Mon, 03 Aug 2020 14:02:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729094AbgHCVCb (ORCPT + 4 others); Mon, 3 Aug 2020 17:02:31 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:40326 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCa (ORCPT ); Mon, 3 Aug 2020 17:02:30 -0400 Received: by mail-io1-f68.google.com with SMTP id l17so40001373iok.7; Mon, 03 Aug 2020 14:02:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VwFTr4t0lrmNy8f4Fgv3/l49uahHgczW7Wdy7hSwZ1w=; b=LORzLGQCc25xfattQ/r/eucxR1jhevA1boxWsnpFezxp4FAJH8zXFAS55YebAQxt49 h7OtBc4Rk3Es3JBBHnKpfKL+HGl0MiW0fDRZpCCLs1kEM/T4tdr3CviNX8FNvuWwplVw 0syBl5MkVIX8PJVjRD4ejJo7rxJ87n2tlAj8De73inJKZZvIgOFpabtSSa/btmXiVOwW 5cfjhryp9Sa5+CUY6Mee1jqIK5Ip5g8WdUvaf+UcHMhBXSvFHaoVklyZfwFpN6DfeF05 tK452SW3+4DSxiIqaGUViYGYCv0m8+KMtJcLbNJiFLOZvNX/X2f4tZyAAwxG7w8V2TUI 4x0A== X-Gm-Message-State: AOAM530dT9iH43Gsh1KoPGuU1LF4DdqnW7pOPVXRL5Iw+uEISKFI9hbG 4lWsoCqdtNi1jAa2AUaeeQ== X-Received: by 2002:a5d:9b96:: with SMTP id r22mr1878334iom.66.1596488549634; Mon, 03 Aug 2020 14:02:29 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:29 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Andy Gross Subject: [RFC 25/27] PCI: dwc/qcom: Use common PCI register definitions Date: Mon, 3 Aug 2020 15:01:14 -0600 Message-Id: <20200803210116.3132633-26-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The QCom driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Cc: Stanimir Varbanov Cc: Andy Gross Cc: Bjorn Andersson Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++---------------- 1 file changed, 10 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9f1d3ba686fa..dba5f7d7f727 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -39,11 +39,6 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PCIE20_COMMAND_STATUS 0x04 -#define CMD_BME_VAL 0x4 -#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 -#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 - #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C #define PCIE20_PARF_DBI_BASE_ADDR 0x168 @@ -65,10 +60,6 @@ #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c #define CFG_BRIDGE_SB_INIT BIT(0) -#define PCIE20_CAP 0x70 -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC) -#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) -#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F #define PCIE20_PARF_Q2A_FLUSH 0x1AC @@ -974,6 +965,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int i, ret; u32 val; @@ -1047,16 +1039,16 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) pcie->parf + PCIE20_PARF_SYS_CTRL); writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); - writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); + writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); + writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); - val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; - writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPMS; + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); - writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + - PCIE20_DEVICE_CONTROL2_STATUS2); + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + + PCI_EXP_DEVCTL2); return 0; @@ -1209,7 +1201,8 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_link_up(struct dw_pcie *pci) { - u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); return !!(val & PCI_EXP_LNKSTA_DLLLA); } From patchwork Mon Aug 3 21:01:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 247420 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp1540342ilo; Mon, 3 Aug 2020 14:02:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3OHkMteoDs+7G8hYwEDMJT0iwUsRGDVEl0z+mW8V+7Z1e/dnZXiF9jitN5zNKzcg1oZmX X-Received: by 2002:a05:6402:1a26:: with SMTP id be6mr17274437edb.162.1596488558516; Mon, 03 Aug 2020 14:02:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596488558; cv=none; d=google.com; s=arc-20160816; b=FImKqirLsxRBgJPAsUWrPltacGcUEsCqjtD1exiW6UkyDz4Y5wdBTOt6wpBiar+af4 mPCr0U4HIMFDUUZCSk2WD5vun7cYuhOIvBiOGQxFb6IyI4/MDMtC8CKgFm2LApKkOGDC NbyQeUe3y2fazoVgudTF0Ifnxn9o7nS+STeJn6JLYff6XXPKlzQI1o7iE8xRwJ7Ujpcr /gPfxQKaETsN1hHCXHVFGoAGjLD3I0jdjs/AZegB2kEFY5ldRWVhnxiCg+yr+N3suLMJ iyVzDrrM943R8+dsyRLMY6jhTRqUfkkz8L6Q2DKzwE5ju68oQXeIa2oeqDTgR6+3sJUI xS2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=5V63dl5D15U/c4aTTJinxu1IGbYXot5HyJAyQBAcQN8=; b=b1HrAl2Lh/c8gKNq07U1RVZJXN9ayPY4nCN66iYm+zlaZuKXKd8QweO01MQ+obg5Mf /ivwhcycH+e/+jC5SfUkWmHtthmb/a9rwzgHoZfuSKNfo0OPIn5mPOtFd45Os6jQAWs/ seCvSW5Q09QWGeg6QEdG4TlfK3XWVOkHdi5jSN8hDRLip72jKeTqCVVwMU10HSmaOERM dEMkDpLLPOfAH09Jtr5RnhSJDA5ps0UBd4vdFhgrKxNnL3BtdqQNcAXwVVbVy4FJi7k7 5vzdznW0mvrhYe0k90o+7baNcvSXupdctfQaMxMroDfruLYIYap5ms7On+Dv8mGxINsA c6GQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id rl26si3871175ejb.568.2020.08.03.14.02.38; Mon, 03 Aug 2020 14:02:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729104AbgHCVCh (ORCPT + 4 others); Mon, 3 Aug 2020 17:02:37 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:43788 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCg (ORCPT ); Mon, 3 Aug 2020 17:02:36 -0400 Received: by mail-io1-f65.google.com with SMTP id k23so39951531iom.10; Mon, 03 Aug 2020 14:02:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5V63dl5D15U/c4aTTJinxu1IGbYXot5HyJAyQBAcQN8=; b=lf+K0Ql0HCqhJcyF4kai/etIqiUZ5bNVUJd1+XspolRaUPLVLF6HBHldF/eAGa4TuT pxPeu7ETiPIkjyXkvnU3ZWVZdmXznDyHHSy93nOnTCrIYV2cy9EMWm8FCWdKvKRFDDSj bj95yG17VJ9ktftMRMUw+bhcIOpKW/KbyJqppiMFA8wpr8TkW8D7ozmuY1evdMp484Jq kVog3G7VEvBV+dIiF+cuEHt5FunipPMYC9l+3Pxo4oDYhz+7klGu1zcZ0tydwv08girF uOf7Z2qnsEIfEYSqg6hT/M9BaaVd62Lkk2tTBr6so+m8bb3+CqlPIlE3dQM1Fo1ZD7y+ pxAQ== X-Gm-Message-State: AOAM533M199Z9L1ErQJW2xeBpdskJyMIwQUIg32k+YS0Kxx2VA2t/H6O 86r7O0LE3m2qQzGF9QN+6A== X-Received: by 2002:a6b:c504:: with SMTP id v4mr1853953iof.20.1596488554927; Mon, 03 Aug 2020 14:02:34 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:34 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions Date: Mon, 3 Aug 2020 15:01:16 -0600 Message-Id: <20200803210116.3132633-28-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The Tegra driver has its own defines for common Designware Port Logic registers. Convert it to use the standard register definitions. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-pci@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware.h | 6 +++ drivers/pci/controller/dwc/pcie-tegra194.c | 56 ++++++++------------ 2 files changed, 28 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b18a9a5f48d2..3bd322db69a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -32,7 +32,13 @@ /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_AFR 0x70C #define PORT_AFR_N_FTS_MASK GENMASK(15, 8) +#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n) #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) +#define PORT_AFR_ENTER_ASPM BIT(30) +#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 +#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) +#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 +#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_DLL_LINK_EN BIT(5) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index c567c9c09ff6..ad295c854853 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -183,19 +183,7 @@ #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 #define EVENT_COUNTER_GROUP_5 0x5 -#define PORT_LOGIC_ACK_F_ASPM_CTRL 0x70C -#define ENTER_ASPM BIT(30) -#define L0S_ENTRANCE_LAT_SHIFT 24 -#define L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) -#define L1_ENTRANCE_LAT_SHIFT 27 -#define L1_ENTRANCE_LAT_MASK GENMASK(29, 27) -#define N_FTS_SHIFT 8 -#define N_FTS_MASK GENMASK(7, 0) #define N_FTS_VAL 52 - -#define PORT_LOGIC_GEN2_CTRL 0x80C -#define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17) -#define FTS_MASK GENMASK(7, 0) #define FTS_VAL 52 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828 @@ -401,9 +389,9 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; appl_writel(pcie, val, APPL_CAR_RESET_OVRD); - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); - val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val |= PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); } } @@ -694,11 +682,11 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); /* Program L0s and L1 entrance latencies */ - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); - val &= ~L0S_ENTRANCE_LAT_MASK; - val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT); - val |= ENTER_ASPM; - dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; + val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); + val |= PORT_AFR_ENTER_ASPM; + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); } static int init_debugfs(struct tegra_pcie_dw *pcie) @@ -895,15 +883,15 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); /* Configure FTS */ - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); - val &= ~(N_FTS_MASK << N_FTS_SHIFT); - val |= N_FTS_VAL << N_FTS_SHIFT; - dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~PORT_AFR_N_FTS_MASK; + val |= PORT_AFR_N_FTS(N_FTS_VAL); + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); - val &= ~FTS_MASK; + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_N_FTS_MASK; val |= FTS_VAL; - dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); /* Enable as 0xFFFF0001 response for CRS */ val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); @@ -1820,15 +1808,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); /* Configure N_FTS & FTS */ - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); - val &= ~(N_FTS_MASK << N_FTS_SHIFT); - val |= N_FTS_VAL << N_FTS_SHIFT; - dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~PORT_AFR_N_FTS_MASK; + val |= PORT_AFR_N_FTS(FTS_VAL); + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); - val &= ~FTS_MASK; + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_N_FTS_MASK; val |= FTS_VAL; - dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); /* Configure Max Speed from DT */ if (pcie->max_speed && pcie->max_speed != -EINVAL) {