From patchwork Fri Aug 7 10:25:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 247551 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp2312729ilo; Fri, 7 Aug 2020 03:25:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3MmmPS/SBtjuMbFvBdCGCMr7zUMmHwRwmeUffS2HoSlYsQTcOrqkYKmH/d7/kJHYlFHqa X-Received: by 2002:a17:906:1f8e:: with SMTP id t14mr8746582ejr.336.1596795952491; Fri, 07 Aug 2020 03:25:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596795952; cv=none; d=google.com; s=arc-20160816; b=J0R1JemPL5cez46CepCqB2Hy3FUZLuQ3AFVcB/WtvCUkTZ3AVKBwj3M6DKVmuR5QhU 7yzvlKBXPWTjK6LSo6WItywEs/yMT7Kbygj/9RZqpiYZJruosleg2vz9csqgcafOoaEt QEprMbRre+JFnrOFBjvEObDcGAIWv3CTrHUWvuOE2lR2Yh0CAI/fCXSymIewDu3VGrgL PSfhhsGhK5+mcmKKy8CaUZz4hYPdXPWkZVv++L8d6TRc1pQfjN9MZmRds1p5kivLYfjJ SGE3FWjIRxenUldAebMDTKFRFMWX7BjmcksA8TeWGH6hQ6Jz4NixcHzYhyAteHgkx6fx Ghgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Tx9tjHFfZ920uEvJ+N3RWMCOvuuZtYdQQ/bhHTpcOwo=; b=liXeC2pbu+jc5Eb0AVc0G0zb8FgDAdLWyrG7UlfNs/RMctcvwSfCBcNqIV9FWvNdNa 8uqKF2IxQmonjpS4VTrDLX5IjWb8Hgat4nH5KM8J1xgYveqpM4QjKFSn9x0Pgs5n27Dk JQlvlo7BK8nQzAmYlIh+TaUEOPH0rjWl2u0ESmQbTIxMKt0yq7CXeU04Q8ZGTQiHnRjQ HjQflzExxjy9HaBT3+gp4PGY3dHI/5R0uG27TL3iCyE47Ishtk54Ld8PJQ8L2nyDazyp 19wU52WCg2gFr5sH0HEWJ0v7cwM4EB22fFb+IyDr2IaDiSB8Wev3qcXV2H8pT8/23Ao9 fX+g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e17si5733132edc.382.2020.08.07.03.25.52; Fri, 07 Aug 2020 03:25:52 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728194AbgHGKZc (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:32 -0400 Received: from mx.socionext.com ([202.248.49.38]:31570 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726940AbgHGKZa (ORCPT ); Fri, 7 Aug 2020 06:25:30 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:28 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 04FBB180BB5; Fri, 7 Aug 2020 19:25:29 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:29 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id A7F441A0507; Fri, 7 Aug 2020 19:25:28 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 1/6] PCI: portdrv: Add pcie_port_service_get_irq() function Date: Fri, 7 Aug 2020 19:25:17 +0900 Message-Id: <1596795922-705-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pcie_port_service_get_irq() that returns the virtual IRQ number for specified portdrv service. Cc: Lorenzo Pieralisi Signed-off-by: Kunihiko Hayashi --- drivers/pci/pcie/portdrv.h | 1 + drivers/pci/pcie/portdrv_core.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) -- 2.7.4 diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index af7cf23..e256456 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -150,4 +150,5 @@ static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ struct device *pcie_port_find_device(struct pci_dev *dev, u32 service); +int pcie_port_service_get_irq(struct pci_dev *dev, u32 service); #endif /* _PORTDRV_H_ */ diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 50a9522..f92daf8 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -480,6 +480,22 @@ struct device *pcie_port_find_device(struct pci_dev *dev, } EXPORT_SYMBOL_GPL(pcie_port_find_device); +/* + * pcie_port_service_get_irq - get irq of the service + * @dev: PCI Express port the service is associated with + * @service: For the service to find + * + * Get irq number associated with given service on a pci_dev + */ +int pcie_port_service_get_irq(struct pci_dev *dev, u32 service) +{ + struct pcie_device *pciedev; + + pciedev = to_pcie_device(pcie_port_find_device(dev, service)); + + return pciedev->irq; +} + /** * pcie_port_device_remove - unregister PCI Express port service devices * @dev: PCI Express port the service devices to unregister are associated with From patchwork Fri Aug 7 10:25:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 247552 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp2312737ilo; Fri, 7 Aug 2020 03:25:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyKT9JUJWxs0f/12rbRuOF7bgZCuFAtr94i8wbRXf7kVRtaSIY8/jISFrgoqFzIz9hmBmEB X-Received: by 2002:a17:906:5902:: with SMTP id h2mr9080241ejq.423.1596795952818; Fri, 07 Aug 2020 03:25:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596795952; cv=none; d=google.com; s=arc-20160816; b=wwEZvYeoX9wv8FutQB8c0t73GY6oLxjI1S7Xz3tjUlaN4h7hcRdiXn7IDgJ15w7Pqu CBoE0xm0L2N6Pfl0rzIOVRwwKuCpjzT1r55QcQI2fmH46h1by0UWAvBMQ+6ly93uGHeJ Q1uHZ/o6MLVBS4F7+1usdEll5b+tosc2FfGcHjbAmYboEldOddC8Dd4ewB437nJuYaT1 ieCZOMLrk6QgB7KCFqnr6V462DCKHc6Nk0KSzn7S97LS29Q1yALHtzj2MS1j1gc3ZCNI DIJtxWthN0YOB5PQkD/SNInFjj5JFtS84K9/hhyQmDA3mlIpzcUMiAnhHC1BsFXxZ+45 wyyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=jMZ9Np59mwhB1Am+VWBP836eeb5+NFJxhLBg98/mYBo=; b=rRPBINKbOOeCVz9GNB+YZrGnadT6K+cF6VfXWHxSCE8YWbOfGruhWPlr7NdWMySy3r M6C18A7uEj08vb8ZgfiwwT3RDaNeGju4QblUsA/3TKGRmnQq55cb1OJMVLU1RFsN88PA 8iYes9U+JN96x1A7+ZtKnCt/qhl8cUT+EZmhOIFfmzKY8g2q6WGRYgjqEfZCv+OHiyhe odjtcyYFlREgUUVacWJnQ7WDDeOwJQmNurPXURrvoK44SVNliplWibZkt2x4v7PqLX7t tMyvc/cjhCjWTGt8lPxjraDWbmIhWlm37YCs9JtAYC12SzMLjK+hqtyaT1MwDWnHqc5Q JTXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e17si5733132edc.382.2020.08.07.03.25.52; Fri, 07 Aug 2020 03:25:52 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728292AbgHGKZv (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:51 -0400 Received: from mx.socionext.com ([202.248.49.38]:31578 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726619AbgHGKZc (ORCPT ); Fri, 7 Aug 2020 06:25:32 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:30 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 8D29A180BB5; Fri, 7 Aug 2020 19:25:30 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:30 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 2A0681A050B; Fri, 7 Aug 2020 19:25:30 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 2/6] PCI: dwc: Add msi_host_isr() callback Date: Fri, 7 Aug 2020 19:25:18 +0900 Message-Id: <1596795922-705-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds msi_host_isr() callback function support to describe SoC-dependent service triggered by MSI. For example, when AER interrupt is triggered by MSI, the callback function reads SoC-dependent registers and detects that the interrupt is from AER, and invoke AER interrupts related to MSI. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Signed-off-by: Kunihiko Hayashi Acked-by: Gustavo Pimentel --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) -- 2.7.4 Acked-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9dafecb..7948bf1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -83,6 +83,9 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) u32 status, num_ctrls; irqreturn_t ret = IRQ_NONE; + if (pp->ops->msi_host_isr) + pp->ops->msi_host_isr(pp); + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; for (i = 0; i < num_ctrls; i++) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index f911760..401cbd9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -170,6 +170,7 @@ struct dw_pcie_host_ops { void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); + void (*msi_host_isr)(struct pcie_port *pp); }; struct pcie_port { From patchwork Fri Aug 7 10:25:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 247547 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp2312583ilo; Fri, 7 Aug 2020 03:25:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwLugy0hS+u+khRDh8RYiBmnIAO7mOuGawSxypvMcgc7I+Kyf5yjyghdgwiWW91DvQkRMqO X-Received: by 2002:a17:906:138b:: with SMTP id f11mr8383509ejc.310.1596795936088; Fri, 07 Aug 2020 03:25:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596795936; cv=none; d=google.com; s=arc-20160816; b=S9tJD4kcnu9EqNM6zEJNBRTZvQd+MBxJrBtz46GNBSJ79hR7YhmaIE0ai37g4WHvZn HGMxF3ANPfyTbf4d1mgEV/Ox/3XQ6wmel0tkaa4ucpMqbvS2r1q8FrjyRXZzTzGhKnOp CydiKo8sCRsDNxwvfQwjj/EDqS8/oh/OXJHxJDliyaFYMRvMo13r5g6lzYsSOPzWsVrJ u1zDAdYm/5w1wC1ZVpXIsIzonvUCns4hEiigugpT3nfijdCp5yZ+t2lNk5Hs7krKEKkP o/gWjv85YMhoQwtonzodR+4fn6qszIdDIWebrMQjnetafsctIz54yT8ewEP+chu6oNSn G/iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=VPTkoL55kMJ/zzw3y9dPn6mzxmUlrhx7IBQkOdPSTgU=; b=FPyIf3fF8Suuo+ygVXyZRd9esF97ETZ7ZSA+H9HG2wNvNpWlS65OO1dKPUdmXkPop6 5d06fKgDMECMDOdLko1VxUhpXKPLZa+kBoyvD2GI8rtY1C9WkE96KyPnVmBJx6FZtpJB VWvlxVysFKCbj2mcNxsaarmJmYiG3WgQO73atrAQ7uqsZnxh590uaKXJdqhAxaAZfUfv NdXz2s27T/LCuVrTcekWvqvtRhAH4mEzUeArXgzCqU56ny4I8m4M0+YJ17jjJoJi9BpI xaGf2YtMQ3wK6lbH/8+K5nThduMHyTqBYQpUkFIYAKsbXr2jX2k4ukRDRiGuUeMKXDGM etEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v8si6015436edl.307.2020.08.07.03.25.35; Fri, 07 Aug 2020 03:25:36 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728260AbgHGKZe (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:34 -0400 Received: from mx.socionext.com ([202.248.49.38]:31586 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728216AbgHGKZe (ORCPT ); Fri, 7 Aug 2020 06:25:34 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:31 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 1156260060; Fri, 7 Aug 2020 19:25:32 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:31 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 7AE2F1A0507; Fri, 7 Aug 2020 19:25:31 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 3/6] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Date: Fri, 7 Aug 2020 19:25:19 +0900 Message-Id: <1596795922-705-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds misc interrupt handler to detect and invoke PME/AER event. In UniPhier PCIe controller, PME/AER signals are assigned to the same signal as MSI by the internal logic. These signals should be detected by the internal register, however, DWC MSI handler can't handle these signals. DWC MSI handler calls .msi_host_isr() callback function, that detects PME/AER signals with the internal register and invokes the interrupt with PME/AER vIRQ numbers. These vIRQ numbers is obtained from portdrv in uniphier_add_pcie_port() function. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 77 +++++++++++++++++++++++++----- 1 file changed, 66 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 3a7f403..55a7166 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -21,6 +21,7 @@ #include #include "pcie-designware.h" +#include "../../pcie/portdrv.h" #define PCL_PINCTRL0 0x002c #define PCL_PERST_PLDN_REGEN BIT(12) @@ -44,7 +45,9 @@ #define PCL_SYS_AUX_PWR_DET BIT(8) #define PCL_RCV_INT 0x8108 +#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25) #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) +#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9) #define PCL_CFG_BW_MGT_STATUS BIT(4) #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) @@ -68,6 +71,8 @@ struct uniphier_pcie_priv { struct reset_control *rst; struct phy *phy; struct irq_domain *legacy_irq_domain; + int aer_irq; + int pme_irq; }; #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) @@ -167,7 +172,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci) static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) { - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); + u32 val; + + val = PCL_RCV_INT_ALL_ENABLE; + if (pci_msi_enabled()) + val |= PCL_RCV_INT_ALL_INT_MASK; + else + val |= PCL_RCV_INT_ALL_MSI_MASK; + + writel(val, priv->base + PCL_RCV_INT); writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); } @@ -231,28 +244,52 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = { .map = uniphier_pcie_intx_map, }; -static void uniphier_pcie_irq_handler(struct irq_desc *desc) +static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi) { - struct pcie_port *pp = irq_desc_get_handler_data(desc); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long reg; - u32 val, bit, virq; + u32 val; - /* INT for debug */ val = readl(priv->base + PCL_RCV_INT); if (val & PCL_CFG_BW_MGT_STATUS) dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); + if (val & PCL_CFG_LINK_AUTO_BW_STATUS) dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); - if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) - dev_dbg(pci->dev, "Root Error\n"); - if (val & PCL_CFG_PME_MSI_STATUS) - dev_dbg(pci->dev, "PME Interrupt\n"); + + if (is_msi) { + if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) { + dev_dbg(pci->dev, "Root Error Status\n"); + if (priv->aer_irq) + generic_handle_irq(priv->aer_irq); + } + + if (val & PCL_CFG_PME_MSI_STATUS) { + dev_dbg(pci->dev, "PME Interrupt\n"); + if (priv->pme_irq) + generic_handle_irq(priv->pme_irq); + } + } writel(val, priv->base + PCL_RCV_INT); +} + +static void uniphier_pcie_msi_host_isr(struct pcie_port *pp) +{ + uniphier_pcie_misc_isr(pp, true); +} + +static void uniphier_pcie_irq_handler(struct irq_desc *desc) +{ + struct pcie_port *pp = irq_desc_get_handler_data(desc); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long reg; + u32 val, bit, virq; + + uniphier_pcie_misc_isr(pp, false); /* INTx */ chained_irq_enter(chip, desc); @@ -330,6 +367,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { .host_init = uniphier_pcie_host_init, + .msi_host_isr = uniphier_pcie_msi_host_isr, }; static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, @@ -338,6 +376,7 @@ static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, struct dw_pcie *pci = &priv->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; + struct pci_dev *pcidev; int ret; pp->ops = &uniphier_pcie_host_ops; @@ -354,6 +393,22 @@ static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, return ret; } + /* irq for PME */ + list_for_each_entry(pcidev, &pp->root_bus->devices, bus_list) { + priv->pme_irq = + pcie_port_service_get_irq(pcidev, PCIE_PORT_SERVICE_PME); + if (priv->pme_irq) + break; + } + + /* irq for AER */ + list_for_each_entry(pcidev, &pp->root_bus->devices, bus_list) { + priv->aer_irq = + pcie_port_service_get_irq(pcidev, PCIE_PORT_SERVICE_AER); + if (priv->aer_irq) + break; + } + return 0; } From patchwork Fri Aug 7 10:25:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 247550 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp2312715ilo; Fri, 7 Aug 2020 03:25:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZAvyCE4irpl2jjqTSIqZugkRaJO0BHWnv5W7OHJBEq1AvO/Z89SneMfV+b3sBx1n57tLc X-Received: by 2002:a50:ee92:: with SMTP id f18mr8221143edr.80.1596795951108; Fri, 07 Aug 2020 03:25:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596795951; cv=none; d=google.com; s=arc-20160816; b=C0MdnosL4KwqNklGUc+zESKjmSLKeyTQc5+3GG8l7jJbafWtttz9iO78ujKapJl3l8 +AZqr0ovRNkt4lRbXuMYAXJAEZFQ9mSDf+Yud850oRTibzduWFtTTI2fcG/svtySlIga AkbwffaExfbWwIOXU5FrfHjpv8i7D4t62znttHPa8Emt+gn4p5CAbPcxdORO7OR/jykB 3xV2BvnVNlJzNBSh9DQ6LpiiMU+UZ6AVJMhPMsenzaBiU0hlo4jtwV0kdW0GT8IusfU5 KjHy3V13vAuhzcnA1cHZ0OjfgPI2WmkCjbPTNefX2bUNwmbXYu0To1DEFxYJXlN88JY5 wDjA== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id e17si5733132edc.382.2020.08.07.03.25.50; Fri, 07 Aug 2020 03:25:51 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728274AbgHGKZe (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:34 -0400 Received: from mx.socionext.com ([202.248.49.38]:31578 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728226AbgHGKZe (ORCPT ); Fri, 7 Aug 2020 06:25:34 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:33 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 19388180BB5; Fri, 7 Aug 2020 19:25:33 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:33 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 933471A0507; Fri, 7 Aug 2020 19:25:32 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 4/6] dt-bindings: PCI: uniphier: Add iATU register description Date: Fri, 7 Aug 2020 19:25:20 +0900 Message-Id: <1596795922-705-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including From patchwork Fri Aug 7 10:25:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 247548 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp2312594ilo; Fri, 7 Aug 2020 03:25:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyAEJ8wXcWVX3tQcKBtq2vfPjZuvgyrk0YhP1VRMbs/2/ujcn+QcnN6JYoGFEOaDRp0dg7 X-Received: by 2002:a17:906:15d8:: with SMTP id l24mr8298230ejd.297.1596795937115; Fri, 07 Aug 2020 03:25:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596795937; cv=none; d=google.com; s=arc-20160816; b=pDPQXDUgiPpU9ggYNALCXEBVhUzlDIp0XtPzXtB1d2sMt5HgK33mTETf6E/JIIkKHp bte0L/7IH1eRgNrmw1r3uJBSpqJtapYBrUjyIfv9ebeWQ1myuXmwxIrOTGIg0BtKdz4M bfewY1WP06kgj8LQkL+dFd21htUspaErxsKcLSibZHeSZzCvoO3VCYOZCzZqwfakbhxp J0GVbX4rW+JjFnAAJcmi29PmT/w6+ADSJP+mUKSBHOuPp2j3Y+18SYArzTXQj9Evw9PX jTnNlTN2leYq0h8AStN6wi3tS8Rc8dD7ScJPQo2qubiLzLFPeL/sMEtBBgLz4X/1BFqg zb9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=mYgbU4Elt7Tg4MMG4gs4JOly2yQ0NgzfUVYTD/ADX9c=; b=srErEvNTO51sAx41nBKbP1MLvLNTFquMW/l83XEMkZkwfmw15SuFWjrJpYbm0aH+uf u2dTY3tq820BCsBT7FL3eORwkqR8vB4CFy9LXVUxmvrjrDbwFS8bYGQqSNjZztIwcniS OGXzBkAm2xaUcbfTNTgCL36urfVyILTvkh99o25QJxx6O4GWBEAWafgPWCIE40AdTGTZ vBimlJxLp20flkXRiO1vkhOCLkxHKOR8dvtKxAI7UYmDDPhO2uyRdzGRZYf03oBNnPow +vs9Xu+23W7zEt1UrtBbFu0HbGeBOOsc8nm3wMMCl0WCU4zpjO9FYD5DA5HPvtvSCfpO o+UQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v8si6015436edl.307.2020.08.07.03.25.36; Fri, 07 Aug 2020 03:25:37 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728294AbgHGKZg (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:36 -0400 Received: from mx.socionext.com ([202.248.49.38]:31578 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727037AbgHGKZf (ORCPT ); Fri, 7 Aug 2020 06:25:35 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:34 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id A9134180BB5; Fri, 7 Aug 2020 19:25:34 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:34 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 11D2C1A0507; Fri, 7 Aug 2020 19:25:34 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 5/6] PCI: uniphier: Add iATU register support Date: Fri, 7 Aug 2020 19:25:21 +0900 Message-Id: <1596795922-705-6-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property. In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 55a7166..93ef608 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -471,6 +471,11 @@ static int uniphier_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->pci.dbi_base)) return PTR_ERR(priv->pci.dbi_base); + priv->pci.atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(priv->pci.atu_base)) + priv->pci.atu_base = NULL; + priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); From patchwork Fri Aug 7 10:25:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 247549 Delivered-To: patch@linaro.org Received: by 2002:a92:cc90:0:0:0:0:0 with SMTP id x16csp2312676ilo; Fri, 7 Aug 2020 03:25:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymIdjFKytXg+1YIf0/ibhDLd3sM4UbVDD1SNQQPjIdqxrMcvIaPyz7yOvNYcLcnlOTvIUL X-Received: by 2002:a05:6402:1591:: with SMTP id c17mr8057419edv.111.1596795945265; Fri, 07 Aug 2020 03:25:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1596795945; cv=none; d=google.com; s=arc-20160816; b=WDiJ/3N87fjuBFO6FZtfOa+RYFt4R083AuJmKfFR5hn+0fRepoHEfQaxOPpBzW3S0X w9n5gNNFQijKbpHxuq4mdnO2xROIIwCzCmP3ecgNp3X9ph2vK/xqIoC8X7mLj2wuHkCo z0terGKT56qJX3+tkKHIO8DV+EXPH9Gi5W2gpMlpsRKrIk+EBqyFKglbYkIDJUdvLG5d 74jiYc6jJIMhtNTAsW/vGP8Q7HBE1IWrMP+QF1I4GC7WL1NLRdX7csifo+0ufFT3RsN5 ykdIb17URpSgAatRxKXhLg0jMMkJ7mQKi0ik0UUDxMBkrJ2RgTzwsdNXf12yz5uIqiKo Ny5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=+2Ec5nXE5woyOr+PT30xk9G1oL45h7/1HbB536dKeZs=; b=YrrhRV/blm9KOuRt7Bto1y3OXjNblft5q/+a8VyjFJ7bJlrNbT5XpyYXtg6J7UpOAj ENYHVlia4vdQTVVvmJGk+ZsKo+mQWYoCkilXY3IgSQ8Jpe5jxo2qempfpivtr42K57AV YNqf5c3ZCiY4YoBZkJIYXsjJgoYswG3J/WzD0HlGkN/cBeU6ddzJtAtDI8il40PdGo+1 0x7WEseD/Y8pya0+uiUXTvSV04Cm4jF9NCO+96OcmG1vEmvLVBgtV00BmcD+1wgxY/Ar pUXMUDF9b75xMdDYmQdHzO/zMmLf/igl2+6M4LvLKcrnWPlXVUkkDRGygYVGNOqa9GOg PSzg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u18si4950721ejr.700.2020.08.07.03.25.45; Fri, 07 Aug 2020 03:25:45 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727037AbgHGKZn (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:43 -0400 Received: from mx.socionext.com ([202.248.49.38]:31600 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728292AbgHGKZh (ORCPT ); Fri, 7 Aug 2020 06:25:37 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:35 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id A65EF180BB5; Fri, 7 Aug 2020 19:25:35 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:35 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 28C4C1A0507; Fri, 7 Aug 2020 19:25:35 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 6/6] PCI: uniphier: Add error message when failed to get phy Date: Fri, 7 Aug 2020 19:25:22 +0900 Message-Id: <1596795922-705-7-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Even if phy driver doesn't probe, the error message can't be distinguished from other errors. This displays error message caused by the phy driver explicitly. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 93ef608..7c8721e 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -489,8 +489,12 @@ static int uniphier_pcie_probe(struct platform_device *pdev) return PTR_ERR(priv->rst); priv->phy = devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(priv->phy)) - return PTR_ERR(priv->phy); + if (IS_ERR(priv->phy)) { + ret = PTR_ERR(priv->phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get phy (%d)\n", ret); + return ret; + } platform_set_drvdata(pdev, priv);