From patchwork Wed Sep 9 14:42:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 250351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71532C43461 for ; Wed, 9 Sep 2020 16:44:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2401621941 for ; Wed, 9 Sep 2020 16:44:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RBf9ImIk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730868AbgIIQoW (ORCPT ); Wed, 9 Sep 2020 12:44:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730984AbgIIQMs (ORCPT ); Wed, 9 Sep 2020 12:12:48 -0400 Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64920C0612A0 for ; Wed, 9 Sep 2020 07:43:02 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id a15so3920407ljk.2 for ; Wed, 09 Sep 2020 07:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fbds+t1ZnFoCEkxj1/mr3T/pqQY9+u5UlZ3GW4t2en8=; b=RBf9ImIktNqjjf5ULDVjein3dUP72WGKbx2K4R3px5gjd66lkRDZ7e+cm216qNwpD2 NR1adn/mhVy5KRWZTXd6hgxEHWg2crI7A960lb1OuSOMJzYmyMIrNOPnhoLsq7PhsMA0 Au4GhwaA8Frwo6+2s3+EutWFXO80ToppvOUcHIZcp8X7H67n6WBvsQjm8nIh4X0UcdQ5 u1cdP2hOIIRoL7v01N5dwEoTTxL+d3pBn5U069iUBIzdRZTKDhiAVKv/cK0m6e8bEgu0 /j30Ri36tgig3c9rq4PtNANF3r9SeN6ZokikcG7Zr/41LHWdjYqjtoWF5oQg++f6ZF19 JkBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fbds+t1ZnFoCEkxj1/mr3T/pqQY9+u5UlZ3GW4t2en8=; b=pPCmW9N4XlIjGQFQ02/3lTgMtDSEsMEGKGoPWFQR2HjhFf16uW1pOGWz0Ir+2jVFJT NImCqaT7XoxY4wEyGGKOm2OCTY13YRLaK6QaQybGVvDa4sFBWHBP/OuL4SpkCwibOS7O llBq+ZF9m3WuviIYBRKVDr2Yc3jnAxhye/uhowjkBFIv34LZIPNkedsW2MW38letcB2o /y+Zs58YBhI+AZFyBCVdzjpMskwNd/Bu+lOvl3aj+CiQZdet72AOyXakQHGsI2KWlaKc KxK0s1//s1ouTDvPLLRMDVma/qKbwKf4uCwGlSIVMtkRP7o0pz/2f9MH5jMA/Y8ogywE Xlbw== X-Gm-Message-State: AOAM530lw1nJwlvYWPPFzCzN7MAmzLRlWFCF/dvjvDAwREPFngMQdbsR RfSg7s6JlLeyZ8UTYtuUhXi+yQ== X-Google-Smtp-Source: ABdhPJz5kb+Of6IhjilhV2MUlOJG0rCvdvpOh34KeNE6rObp9QcKkuLMCHewb8SEcOtQ3aBSy9hybw== X-Received: by 2002:a2e:920f:: with SMTP id k15mr2147380ljg.353.1599662578123; Wed, 09 Sep 2020 07:42:58 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:42:57 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 01/10] iio: adc: qcom-spmi-adc5: fix driver name Date: Wed, 9 Sep 2020 17:42:39 +0300 Message-Id: <20200909144248.54327-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove superfluous '.c' from qcom-spmi-adc5 device driver name. Fixes: e13d757279 ("iio: adc: Add QCOM SPMI PMIC5 ADC driver") Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam --- drivers/iio/adc/qcom-spmi-adc5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index b4b73c9920b4..c10aa28be70a 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -982,7 +982,7 @@ static int adc5_probe(struct platform_device *pdev) static struct platform_driver adc5_driver = { .driver = { - .name = "qcom-spmi-adc5.c", + .name = "qcom-spmi-adc5", .of_match_table = adc5_match_table, }, .probe = adc5_probe, From patchwork Wed Sep 9 14:42:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88CB3C43461 for ; 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Wed, 09 Sep 2020 07:43:00 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:42:59 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 02/10] dt-bindings: thermal: qcom: add adc-thermal monitor bindings Date: Wed, 9 Sep 2020 17:42:40 +0300 Message-Id: <20200909144248.54327-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add bindings for thermal monitor, part of Qualcomm PMIC5 chips. It is a close counterpart of VADC part of those PMICs. Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml new file mode 100644 index 000000000000..b3818357808b --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC-TM +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + const: qcom,spmi-adc-tm5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of samples to be used for measurement. + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + default: 1 + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + enum: + - 250 + - 420 + - 840 + default: 840 + +patternProperties: + "^([-a-z0-9]*)@[0-9]+$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + description: Specify the sensor channel. + maxItems: 1 + + io-channels: + description: + From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor + + qcom,adc-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Corresponding ADC channel ID. + + qcom,ratiometric: + $ref: /schemas/types.yaml#/definitions/flag + description: + Channel calibration type. + If this property is specified VADC will use the VDD reference + (1.875V) and GND for channel calibration. If property is not found, + channel will be calibrated with 0V and 1.25V reference channels, + also known as absolute calibration. + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Time between AMUX getting configured and the ADC starting conversion. + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Used for scaling the channel input signal before the + signal is fed to VADC. See qcom,spi-vadc specification for the list + of possible values. + minItems: 2 + maxItems: 2 + + required: + - reg + - qcom,adc-channel + + additionalProperties: + false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + pm8150b_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + /* Other propreties are omitted */ + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; +... From patchwork Wed Sep 9 14:42:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 250348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3B2EC43461 for ; Wed, 9 Sep 2020 16:49:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C9EC21919 for ; Wed, 9 Sep 2020 16:49:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OqjBqEAW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730921AbgIIQtD (ORCPT ); Wed, 9 Sep 2020 12:49:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730909AbgIIQHR (ORCPT ); Wed, 9 Sep 2020 12:07:17 -0400 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F067C0612A7 for ; Wed, 9 Sep 2020 07:43:07 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id y4so3870259ljk.8 for ; Wed, 09 Sep 2020 07:43:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wcVYXgQ5pttw1IKCDgQFlSKYdGXdwjbBjMlIEbUjqiQ=; b=OqjBqEAWPDnfTgGoQjNBjYeKg4K9GLkX+Bw8XJ40eGAnEnptk7yRupxf6JWaCD3JmN 5RsG/GLVMzpJiJHXxHhGdf2uNA8I5Ti9uw3PbTjKXGjl7tXt/Lh+00q2uqsGRLua4bpz c0xwDeKX8dqKrNq1y6poqRfUh+qMciJUiOGJ1aEbPxjGGqtUdA1xchxaDu0XrEBPxg2t 2EtWKUuNJThIs44LYt4kbj5pee+7qcsqeQorMdD1UcHjN5e7IFGFQAW4kqhOXP47C5sS sq40F/txN46g5H8AVsWXBkPwPDLuurGMmnKh5rU/9dl2kro650tFs24zR8g1lE8OeIOt cn7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wcVYXgQ5pttw1IKCDgQFlSKYdGXdwjbBjMlIEbUjqiQ=; b=WLyXuIrDaPoeV/CL8m6pZpYlRY6txloiyVREZ+nVzyFBkgT2h/g0exWIgyk3hG69tx vmVX8gHv1lCU0hxiCK+b85n9FaZfLRdgEiqxL8OU4Tn/7uy5rQMvzRLFgbF+mZ3FClFy hgTeY2eyBAWOjUKyvALcoPfJT+HYsSk1twJEdDjM5tow1o6GLCbcJfbK0eMonKzM4M/n YnKozWTGoFTUUDl3OOSWG9YuNfN4q2WLAGS31EiUtF6Odka4VPhYTMV2F03SnuI3Eki4 PLUjYpP+gLOhATKvU2gw4MqrO50Z89oWrDE1m2yGy2G3bK0ojgEcoQUVWdl3gWMarU7r NEew== X-Gm-Message-State: AOAM532fMuQNx6tYGBKVjmM/E97QTQ7XgaugdTqKB7sdBUYQwvCBHV4q ASyQw/+UsAWBcxZcPaJzuOcEMw== X-Google-Smtp-Source: ABdhPJyWwfksQxPk2Tnm2ER0m9k37Twox0OGJe88A6KO3gv3HM/BUcjQ+SFEmloMY+FO5ietjnqs7A== X-Received: by 2002:a2e:6c08:: with SMTP id h8mr2031092ljc.66.1599662584166; Wed, 09 Sep 2020 07:43:04 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:43:03 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Craig Tatlor Subject: [PATCH v3 03/10] fixp-arith: add a linear interpolation function Date: Wed, 9 Sep 2020 17:42:41 +0300 Message-Id: <20200909144248.54327-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Craig Tatlor Adds a function to interpolate against two points, this is carried arount as a helper function by tons of drivers. Signed-off-by: Craig Tatlor Signed-off-by: Dmitry Baryshkov --- include/linux/fixp-arith.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/fixp-arith.h b/include/linux/fixp-arith.h index 8396013785ef..281cb4f83dbe 100644 --- a/include/linux/fixp-arith.h +++ b/include/linux/fixp-arith.h @@ -141,4 +141,23 @@ static inline s32 fixp_sin32_rad(u32 radians, u32 twopi) #define fixp_cos32_rad(rad, twopi) \ fixp_sin32_rad(rad + twopi / 4, twopi) +/** + * fixp_linear_interpolate() - interpolates a value from two known points + * + * @x0: x value of point 0 + * @y0: y value of point 0 + * @x1: x value of point 1 + * @y1: y value of point 1 + * @x: the linear interpolant + */ +static inline int fixp_linear_interpolate(int x0, int y0, int x1, int y1, int x) +{ + if (y0 == y1 || x == x0) + return y0; + if (x1 == x0 || x == x1) + return y1; + + return y0 + ((y1 - y0) * (x - x0) / (x1 - x0)); +} + #endif From patchwork Wed Sep 9 14:42:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 249518 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ecf:0:0:0:0 with SMTP id i15csp1134ilk; Wed, 9 Sep 2020 09:47:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzWE2aefgGX3FEOEfcbLwSUuDm/djgcK6Br1MCmZJlIgU8i6uoYi8SK5uhoFoiAc02MxDhy X-Received: by 2002:a17:906:f43:: with SMTP id h3mr4420463ejj.338.1599670049768; Wed, 09 Sep 2020 09:47:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599670049; cv=none; d=google.com; s=arc-20160816; b=KhY3X83uaXHMkC6uo9p4tm/NUTDhcFJmAZeFLi1jB0QIngWrtDz5uxyox52sYHngyz 5xuNzGaKJlLW2eKritcGCyyHe0+i0j3KWaOoLIAWa6aUi8istcy4ErTt1yDbHa2ZTPU4 wOdPht2ErIk5aXAabPNkmZe3a341XHdS3EVLzIY2Co+gZRLJzDBcgzI/zy9/y8Rb/+Jx Y/Xi6r5Xrw1R+QaJCorVLHzzVezzQQYtyMJ/JuaI9otMCDQ4zlVtTXyK3DRZz3u+Elaf 4mWbkpoloKVBURCK39fBU2hsCX+UWdxxhAEpW6s7Oi/+tZc0vUi4YgTFFSePb+0z0D25 Jq5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JBF3uLUf/ZUhgh6mGdQvvNaF8GSfsySai+h7lBFUhRU=; b=a7fqJ6+JySNAsNuApF1StnWKcryR+6sFbHgM9znkHRif79bt8bcr0034J5u98DckNp uJXqgA99q/Kfs8gHdl8DmGUNsQxdoyPjgGWIunt7XjzCiL3J9RJrgxie68yX8bFqGuJK hbzquMNmuNuGC4Vg1Hmu7koFOWxjZNvNRgYAB0vgRHQXLWge7iaAs0I/HUOekRm/HVtS tCN+LRh8+ffs0tuMq9Q4pBImImgGG5XLYViAQmiPcZx35Fdpwqi0WyaGK/HHJ+u8PEG5 0hJGYzHMZFJNwZKPGUFm95MGi+6QBroO/p1tQuTX3Y1dolLSDOLrBOW/L8RrzHQWN6gQ yUVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jMn879aj; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Move them to qcom-vadc-common driver. Signed-off-by: Dmitry Baryshkov Reviewed-by: Jonathan Cameron --- drivers/iio/adc/qcom-spmi-adc5.c | 75 +++--------------------------- drivers/iio/adc/qcom-vadc-common.c | 68 ++++++++++++++++++++++++++- drivers/iio/adc/qcom-vadc-common.h | 10 +++- 3 files changed, 82 insertions(+), 71 deletions(-) -- 2.28.0 diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index c10aa28be70a..c2da8f068b87 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -154,18 +154,6 @@ struct adc5_chip { const struct adc5_data *data; }; -static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { - {.num = 1, .den = 1}, - {.num = 1, .den = 3}, - {.num = 1, .den = 4}, - {.num = 1, .den = 6}, - {.num = 1, .den = 20}, - {.num = 1, .den = 8}, - {.num = 10, .den = 81}, - {.num = 1, .den = 10}, - {.num = 1, .den = 16} -}; - static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) { return regmap_bulk_read(adc->regmap, adc->base + offset, data, len); @@ -181,55 +169,6 @@ static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val) return regmap_update_bits(adc->regmap, adc->base + offset, mask, val); } -static int adc5_prescaling_from_dt(u32 num, u32 den) -{ - unsigned int pre; - - for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) - if (adc5_prescale_ratios[pre].num == num && - adc5_prescale_ratios[pre].den == den) - break; - - if (pre == ARRAY_SIZE(adc5_prescale_ratios)) - return -EINVAL; - - return pre; -} - -static int adc5_hw_settle_time_from_dt(u32 value, - const unsigned int *hw_settle) -{ - unsigned int i; - - for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) { - if (value == hw_settle[i]) - return i; - } - - return -EINVAL; -} - -static int adc5_avg_samples_from_dt(u32 value) -{ - if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX) - return -EINVAL; - - return __ffs(value); -} - -static int adc5_decimation_from_dt(u32 value, - const unsigned int *decimation) -{ - unsigned int i; - - for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) { - if (value == decimation[i]) - return i; - } - - return -EINVAL; -} - static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data) { int ret; @@ -511,7 +450,7 @@ static int adc_read_raw_common(struct iio_dev *indio_dev, return ret; ret = qcom_adc5_hw_scale(prop->scale_fn_type, - &adc5_prescale_ratios[prop->prescale], + prop->prescale, adc->data, adc_code_volt, val); if (ret) @@ -717,7 +656,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32(node, "qcom,decimation", &value); if (!ret) { - ret = adc5_decimation_from_dt(value, data->decimation); + ret = qcom_adc5_decimation_from_dt(value, data->decimation); if (ret < 0) { dev_err(dev, "%02x invalid decimation %d\n", chan, value); @@ -730,7 +669,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); if (!ret) { - ret = adc5_prescaling_from_dt(varr[0], varr[1]); + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); if (ret < 0) { dev_err(dev, "%02x invalid pre-scaling <%d %d>\n", chan, varr[0], varr[1]); @@ -759,11 +698,9 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) || adc->data->info == &adc7_info) - ret = adc5_hw_settle_time_from_dt(value, - data->hw_settle_2); + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2); else - ret = adc5_hw_settle_time_from_dt(value, - data->hw_settle_1); + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); if (ret < 0) { dev_err(dev, "%02x invalid hw-settle-time %d us\n", @@ -777,7 +714,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32(node, "qcom,avg-samples", &value); if (!ret) { - ret = adc5_avg_samples_from_dt(value); + ret = qcom_adc5_avg_samples_from_dt(value); if (ret < 0) { dev_err(dev, "%02x invalid avg-samples %d\n", chan, value); diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index 5113aaa6ba67..d11f3343ad52 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -278,6 +278,18 @@ static const struct vadc_map_pt adcmap7_100k[] = { { 2420, 130048 } }; +static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { + {.num = 1, .den = 1}, + {.num = 1, .den = 3}, + {.num = 1, .den = 4}, + {.num = 1, .den = 6}, + {.num = 1, .den = 20}, + {.num = 1, .den = 8}, + {.num = 10, .den = 81}, + {.num = 1, .den = 10}, + {.num = 1, .den = 16} +}; + static int qcom_vadc_scale_hw_calib_volt( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -647,10 +659,12 @@ int qcom_vadc_scale(enum vadc_scale_fn_type scaletype, EXPORT_SYMBOL(qcom_vadc_scale); int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - const struct vadc_prescale_ratio *prescale, + unsigned int prescale_ratio, const struct adc5_data *data, u16 adc_code, int *result) { + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + if (!(scaletype >= SCALE_HW_CALIB_DEFAULT && scaletype < SCALE_HW_CALIB_INVALID)) { pr_err("Invalid scale type %d\n", scaletype); @@ -662,6 +676,58 @@ int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, } EXPORT_SYMBOL(qcom_adc5_hw_scale); +int qcom_adc5_prescaling_from_dt(u32 num, u32 den) +{ + unsigned int pre; + + for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) + if (adc5_prescale_ratios[pre].num == num && + adc5_prescale_ratios[pre].den == den) + break; + + if (pre == ARRAY_SIZE(adc5_prescale_ratios)) + return -EINVAL; + + return pre; +} +EXPORT_SYMBOL(qcom_adc5_prescaling_from_dt); + +int qcom_adc5_hw_settle_time_from_dt(u32 value, + const unsigned int *hw_settle) +{ + unsigned int i; + + for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) { + if (value == hw_settle[i]) + return i; + } + + return -EINVAL; +} +EXPORT_SYMBOL(qcom_adc5_hw_settle_time_from_dt); + +int qcom_adc5_avg_samples_from_dt(u32 value) +{ + if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX) + return -EINVAL; + + return __ffs(value); +} +EXPORT_SYMBOL(qcom_adc5_avg_samples_from_dt); + +int qcom_adc5_decimation_from_dt(u32 value, const unsigned int *decimation) +{ + unsigned int i; + + for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) { + if (value == decimation[i]) + return i; + } + + return -EINVAL; +} +EXPORT_SYMBOL(qcom_adc5_decimation_from_dt); + int qcom_vadc_decimation_from_dt(u32 value) { if (!is_power_of_2(value) || value < VADC_DECIMATION_MIN || diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h index 17b2fc4d8bf2..7e5f6428e311 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/drivers/iio/adc/qcom-vadc-common.h @@ -168,10 +168,18 @@ struct qcom_adc5_scale_type { }; int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - const struct vadc_prescale_ratio *prescale, + unsigned int prescale_ratio, const struct adc5_data *data, u16 adc_code, int *result_mdec); +int qcom_adc5_prescaling_from_dt(u32 num, u32 den); + +int qcom_adc5_hw_settle_time_from_dt(u32 value, const unsigned int *hw_settle); + +int qcom_adc5_avg_samples_from_dt(u32 value); + +int qcom_adc5_decimation_from_dt(u32 value, const unsigned int *decimation); + int qcom_vadc_decimation_from_dt(u32 value); #endif /* QCOM_VADC_COMMON_H */ From patchwork Wed Sep 9 14:42:43 2020 Content-Type: text/plain; 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Wed, 09 Sep 2020 07:43:11 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam , Jonathan Cameron Subject: [PATCH v3 05/10] iio: adc: qcom-vadc-common: use fixp_linear_interpolate Date: Wed, 9 Sep 2020 17:42:43 +0300 Message-Id: <20200909144248.54327-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use new function fixp_linear_interpolate() instead of hand-coding the linear interpolation. Signed-off-by: Dmitry Baryshkov Reviewed-by: Jonathan Cameron --- drivers/iio/adc/qcom-vadc-common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index d11f3343ad52..40d77b3af1bb 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -368,10 +369,9 @@ static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts, } else { /* result is between search_index and search_index-1 */ /* interpolate linearly */ - *output = (((s32)((pts[i].y - pts[i - 1].y) * - (input - pts[i - 1].x)) / - (pts[i].x - pts[i - 1].x)) + - pts[i - 1].y); + *output = fixp_linear_interpolate(pts[i - 1].x, pts[i - 1].y, + pts[i].x, pts[i].y, + input); } return 0; From patchwork Wed Sep 9 14:42:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A53EDC43461 for ; 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Wed, 09 Sep 2020 07:43:16 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:43:16 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 06/10] iio: adc: qcom-spmi-adc5: use of_device_get_match_data Date: Wed, 9 Sep 2020 17:42:44 +0300 Message-Id: <20200909144248.54327-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use of_device_get_match_data() instead of hand-coding it manually. Signed-off-by: Dmitry Baryshkov --- drivers/iio/adc/qcom-spmi-adc5.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index c2da8f068b87..ae27ed7a26ff 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -807,8 +808,6 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) struct adc5_channel_prop prop, *chan_props; struct device_node *child; unsigned int index = 0; - const struct of_device_id *id; - const struct adc5_data *data; int ret; adc->nchannels = of_get_available_child_count(node); @@ -827,24 +826,21 @@ static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) chan_props = adc->chan_props; iio_chan = adc->iio_chans; - id = of_match_node(adc5_match_table, node); - if (id) - data = id->data; - else - data = &adc5_data_pmic; - adc->data = data; + adc->data = of_device_get_match_data(adc->dev); + if (!adc->data) + adc->data = &adc5_data_pmic; for_each_available_child_of_node(node, child) { - ret = adc5_get_dt_channel_data(adc, &prop, child, data); + ret = adc5_get_dt_channel_data(adc, &prop, child, adc->data); if (ret) { of_node_put(child); return ret; } prop.scale_fn_type = - data->adc_chans[prop.channel].scale_fn_type; + adc->data->adc_chans[prop.channel].scale_fn_type; *chan_props = prop; - adc_chan = &data->adc_chans[prop.channel]; + adc_chan = &adc->data->adc_chans[prop.channel]; iio_chan->channel = prop.channel; iio_chan->datasheet_name = prop.datasheet_name; From patchwork Wed Sep 9 14:42:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 292956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3977C433E2 for ; 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Wed, 09 Sep 2020 07:43:20 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:43:20 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 07/10] iio: provide of_iio_channel_get_by_name() and devm_ version it Date: Wed, 9 Sep 2020 17:42:45 +0300 Message-Id: <20200909144248.54327-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There might be cases when the IIO channel is attached to the device subnode instead of being attached to the main device node. Allow drivers to query IIO channels by using device tree nodes. Signed-off-by: Dmitry Baryshkov --- drivers/iio/inkern.c | 33 +++++++++++++++++++++++++-------- include/linux/iio/consumer.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c index ede99e0d5371..3083f886d3da 100644 --- a/drivers/iio/inkern.c +++ b/drivers/iio/inkern.c @@ -180,8 +180,8 @@ static struct iio_channel *of_iio_channel_get(struct device_node *np, int index) return ERR_PTR(err); } -static struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, - const char *name) +struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, + const char *name) { struct iio_channel *chan = NULL; @@ -261,12 +261,6 @@ static struct iio_channel *of_iio_channel_get_all(struct device *dev) #else /* CONFIG_OF */ -static inline struct iio_channel * -of_iio_channel_get_by_name(struct device_node *np, const char *name) -{ - return NULL; -} - static inline struct iio_channel *of_iio_channel_get_all(struct device *dev) { return NULL; @@ -382,6 +376,29 @@ struct iio_channel *devm_iio_channel_get(struct device *dev, } EXPORT_SYMBOL_GPL(devm_iio_channel_get); +struct iio_channel *devm_of_iio_channel_get_by_name(struct device *dev, + struct device_node *np, + const char *channel_name) +{ + struct iio_channel **ptr, *channel; + + ptr = devres_alloc(devm_iio_channel_free, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + channel = of_iio_channel_get_by_name(np, channel_name); + if (IS_ERR(channel)) { + devres_free(ptr); + return channel; + } + + *ptr = channel; + devres_add(dev, ptr); + + return channel; +} +EXPORT_SYMBOL_GPL(devm_of_iio_channel_get_by_name); + struct iio_channel *iio_channel_get_all(struct device *dev) { const char *name; diff --git a/include/linux/iio/consumer.h b/include/linux/iio/consumer.h index c4118dcb8e05..0a90ba8fa1bb 100644 --- a/include/linux/iio/consumer.h +++ b/include/linux/iio/consumer.h @@ -13,6 +13,7 @@ struct iio_dev; struct iio_chan_spec; struct device; +struct device_node; /** * struct iio_channel - everything needed for a consumer to use a channel @@ -97,6 +98,41 @@ void iio_channel_release_all(struct iio_channel *chan); */ struct iio_channel *devm_iio_channel_get_all(struct device *dev); +/** + * of_iio_channel_get_by_name() - get description of all that is needed to access channel. + * @np: Pointer to consumer device tree node + * @consumer_channel: Unique name to identify the channel on the consumer + * side. This typically describes the channels use within + * the consumer. E.g. 'battery_voltage' + */ +#ifdef CONFIG_OF +struct iio_channel *of_iio_channel_get_by_name(struct device_node *np, const char *name); +#else +static inline struct iio_channel * +of_iio_channel_get_by_name(struct device_node *np, const char *name) +{ + return NULL; +} +#endif + +/** + * devm_of_iio_channel_get_by_name() - Resource managed version of of_iio_channel_get_by_name(). + * @dev: Pointer to consumer device. + * @np: Pointer to consumer device tree node + * @consumer_channel: Unique name to identify the channel on the consumer + * side. This typically describes the channels use within + * the consumer. E.g. 'battery_voltage' + * + * Returns a pointer to negative errno if it is not able to get the iio channel + * otherwise returns valid pointer for iio channel. + * + * The allocated iio channel is automatically released when the device is + * unbound. + */ +struct iio_channel *devm_of_iio_channel_get_by_name(struct device *dev, + struct device_node *np, + const char *consumer_channel); + struct iio_cb_buffer; /** * iio_channel_get_all_cb() - register callback for triggered capture From patchwork Wed Sep 9 14:42:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 250349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A9A5C43461 for ; Wed, 9 Sep 2020 16:48:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE5F72166E for ; Wed, 9 Sep 2020 16:48:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="IsTbhuF4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730845AbgIIQsi (ORCPT ); Wed, 9 Sep 2020 12:48:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730669AbgIIQHj (ORCPT ); Wed, 9 Sep 2020 12:07:39 -0400 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CE67C06125E for ; Wed, 9 Sep 2020 07:43:31 -0700 (PDT) Received: by mail-lj1-x241.google.com with SMTP id k25so3929479ljk.0 for ; Wed, 09 Sep 2020 07:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2WYwiUUMQN2z6vI1vg6yF2aZvbBYRrMTt45AOG5GRDs=; b=IsTbhuF4KrZbBNX9qa2Nl2NarKEBPn29YNiZt3CZcqkI7D5ISfdZGBbIePQWyDuVOq mkjtF0zt/PHTMXtlVThyKH+sNDq6r59tZW6iYi3kjr1LGFimL2tjRhUn/9D79WunZ1K1 /vqMy4kCBclPJq5W4W3jW9i57rxWaxGp2x0Ra4IzCw0jhFtl8VScJK8isMQSrggFpQKl iL95h3noZoEP0g50Uw+vV2AUWHEnn2rAd0NL3AUEGIuXx/y91UL5ZFhMocdxtupjLGDW H/Xhf8ZmioapvYM27sdsh1RAIbn5FC2zKljH4ZiFq7Nf6dIl/Y8jEV0cW/HwD5OSfdym Wf6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2WYwiUUMQN2z6vI1vg6yF2aZvbBYRrMTt45AOG5GRDs=; b=iSJL2bFLG1w/GXjGqp3KNjWoIplB9qrTfOS61kTTWxkOnsXEUrQyZHEiYfI8vELQBO J+pKQlVL6Y2gGDPc5SZuTrnPasbPWXCbFlwbZ2T6HiN5ub3Cc219oKRZViMhUD7wDQIc vHbzSdlG11qCHINYojWjCD6Ibxu6GUCrmIw+S9TzBDc4FR+KspISmTpBPhBOkbGybbmc GyPzLFcr578J28rYcc7jxa6oYwBpTzcatXhUeVHXxJoDnuEDUncoxYUKajYSRtNvWNrx 8ZopU+vdLwed4Zq6JTdXCrxbzfNBWl2JmlhfZ63g+lp4KG5sYTnBsHLM2d//DHpQNFms oeUg== X-Gm-Message-State: AOAM531x3fcv/2SsA8T33nCwzYDzh2tDJG6ul0OrSPJh71IT4A9NW3kC ltOmgkqURepUztjeZjvi6E5yJw== X-Google-Smtp-Source: ABdhPJyRVltfyFHdNehRqI01mp1oEosjXuO6TESaL+nwiYUC3nu94x1TulROOFIOQr/hdsrKw2wnSg== X-Received: by 2002:a2e:b610:: with SMTP id r16mr2216338ljn.226.1599662607965; Wed, 09 Sep 2020 07:43:27 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:43:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 08/10] thermal: qcom: add support for adc-tm5 PMIC thermal monitor Date: Wed, 9 Sep 2020 17:42:46 +0300 Message-Id: <20200909144248.54327-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Thermal Monitoring part of PMIC5. This part is closely coupled with ADC, using it's channels directly. ADC-TM support generating interrupts on ADC value crossing low or high voltage bounds, which is used to support thermal trip points. Signed-off-by: Dmitry Baryshkov Reviewed-by: Jonathan Cameron --- drivers/iio/adc/qcom-vadc-common.c | 74 ++- drivers/iio/adc/qcom-vadc-common.h | 3 + drivers/thermal/qcom/Kconfig | 11 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 567 +++++++++++++++++++++++ 5 files changed, 650 insertions(+), 6 deletions(-) create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5.c diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index 40d77b3af1bb..fbdf501954ed 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -377,6 +377,42 @@ static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts, return 0; } +static s32 qcom_vadc_map_temp_voltage(const struct vadc_map_pt *pts, + u32 tablesize, int input) +{ + bool descending = 1; + u32 i = 0; + + /* Check if table is descending or ascending */ + if (tablesize > 1) { + if (pts[0].y < pts[1].y) + descending = 0; + } + + while (i < tablesize) { + if (descending && pts[i].y < input) { + /* table entry is less than measured*/ + /* value and table is descending, stop */ + break; + } else if ((!descending) && pts[i].y > input) { + /* table entry is greater than measured*/ + /*value and table is ascending, stop */ + break; + } + i++; + } + + if (i == 0) + return pts[0].x; + if (i == tablesize) + return pts[tablesize - 1].x; + + /* result is between search_index and search_index-1 */ + /* interpolate linearly */ + return fixp_linear_interpolate(pts[i - 1].y, pts[i - 1].x, + pts[i].y, pts[i].x, input); +} + static void qcom_vadc_scale_calib(const struct vadc_linear_graph *calib_graph, u16 adc_code, bool absolute, @@ -474,10 +510,23 @@ static int qcom_vadc_scale_chg_temp(const struct vadc_linear_graph *calib_graph, return 0; } +static u16 qcom_vadc_scale_voltage_code(int voltage, + const struct vadc_prescale_ratio *prescale, + const u32 full_scale_code_volt, + unsigned int factor) +{ + s64 volt = voltage, adc_vdd_ref_mv = 1875; + + volt *= prescale->num * factor * full_scale_code_volt; + volt = div64_s64(volt, (s64)prescale->den * adc_vdd_ref_mv * 1000); + + return volt; +} + static int qcom_vadc_scale_code_voltage_factor(u16 adc_code, - const struct vadc_prescale_ratio *prescale, - const struct adc5_data *data, - unsigned int factor) + const struct vadc_prescale_ratio *prescale, + const struct adc5_data *data, + unsigned int factor) { s64 voltage, temp, adc_vdd_ref_mv = 1875; @@ -658,10 +707,23 @@ int qcom_vadc_scale(enum vadc_scale_fn_type scaletype, } EXPORT_SYMBOL(qcom_vadc_scale); +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp) +{ + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + s32 voltage; + + voltage = qcom_vadc_map_temp_voltage(adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + temp); + return qcom_vadc_scale_voltage_code(voltage, prescale, full_scale_code_volt, 1000); +} +EXPORT_SYMBOL(qcom_adc_tm5_temp_volt_scale); + int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - unsigned int prescale_ratio, - const struct adc5_data *data, - u16 adc_code, int *result) + unsigned int prescale_ratio, + const struct adc5_data *data, + u16 adc_code, int *result) { const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h index 7e5f6428e311..9af41201ad77 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/drivers/iio/adc/qcom-vadc-common.h @@ -172,6 +172,9 @@ int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, const struct adc5_data *data, u16 adc_code, int *result_mdec); +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp); + int qcom_adc5_prescaling_from_dt(u32 num, u32 den); int qcom_adc5_hw_settle_time_from_dt(u32 value, const unsigned int *hw_settle); diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index aa9c1d80fae4..8d5ac2df26dc 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -10,6 +10,17 @@ config QCOM_TSENS Also able to set threshold temperature for both hot and cold and update when a threshold is reached. +config QCOM_SPMI_ADC_TM5 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5" + depends on OF && SPMI && IIO + select REGMAP_SPMI + select QCOM_VADC_COMMON + help + This enables the thermal driver for the ADC thermal monitoring + device. It shows up as a thermal zone with multiple trip points. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index ec86eef7f6a6..252ea7d9da0b 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c new file mode 100644 index 000000000000..82eda6e011ab --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../iio/adc/qcom-vadc-common.h" + +#define ADC5_MAX_CHANNEL 0xc0 +#define ADC_TM5_NUM_CHANNELS 8 + +#define ADC_TM5_STATUS_LOW 0x0a + +#define ADC_TM5_STATUS_HIGH 0x0b + +#define ADC_TM5_NUM_BTM 0x0f + +#define ADC_TM5_ADC_DIG_PARAM 0x42 + +#define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1) +#define ADC_TM5_FAST_AVG_EN BIT(7) + +#define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2) +#define ADC_TM5_TIMER1 3 /* 3.9ms */ + +#define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3) +#define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0 +#define ADC_TM5_TIMER2 10 /* 1 second */ +#define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf +#define ADC_TM5_TIMER3 4 /* 4 second */ + +#define ADC_TM5_M_CHAN_BASE 0x60 + +#define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0) +#define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1) +#define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2) +#define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3) +#define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4) +#define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5) +#define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6) +#define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf +#define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30 +#define ADC_TM5_M_CTL_CAL_VAL 0x40 +#define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7) +#define ADC_TM5_M_MEAS_EN BIT(7) +#define ADC_TM5_M_HIGH_THR_INT_EN BIT(1) +#define ADC_TM5_M_LOW_THR_INT_EN BIT(0) + +enum adc5_timer_select { + ADC5_TIMER_SEL_1 = 0, + ADC5_TIMER_SEL_2, + ADC5_TIMER_SEL_3, + ADC5_TIMER_SEL_NONE, +}; + +struct adc_tm5_data { + const u32 full_scale_code_volt; + unsigned int *decimation; + unsigned int *hw_settle; +}; + +enum adc_tm5_cal_method { + ADC_TM5_NO_CAL = 0, + ADC_TM5_RATIOMETRIC_CAL, + ADC_TM5_ABSOLUTE_CAL +}; + +struct adc_tm5_chip; + +struct adc_tm5_channel { + unsigned int channel; + unsigned int adc_channel; + enum adc_tm5_cal_method cal_method; + unsigned int prescale; + unsigned int hw_settle_time; + struct iio_channel *iio; + struct adc_tm5_chip *chip; + struct thermal_zone_device *tzd; +}; + +/** + * struct adc_tm5_chip - ADC Thermal Monitoring properties + * @nchannels: amount of channels defined/allocated + * @decimation: sampling rate supported for the channel. + * @avg_samples: ability to provide single result from the ADC + * that is an average of multiple measurements. + * @base: base address of TM registers. + */ +struct adc_tm5_chip { + struct regmap *regmap; + struct device *dev; + const struct adc_tm5_data *data; + struct adc_tm5_channel *channels; + unsigned int nchannels; + unsigned int decimation; + unsigned int avg_samples; + u16 base; +}; + +static const struct adc_tm5_data adc_tm5_data_pmic = { + .full_scale_code_volt = 0x70e4, + .decimation = (unsigned int []) {250, 420, 840}, + .hw_settle = (unsigned int []) {15, 100, 200, 300, 400, 500, 600, 700, + 1, 2, 4, 8, 16, 32, 64, 128}, +}; + +static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) +{ + return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); +} + +static irqreturn_t adc_tm5_isr(int irq, void *data) +{ + struct adc_tm5_chip *chip = data; + u8 status_low, status_high, ctl; + int ret = 0, i = 0; + + ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, 1); + if (ret) { + dev_err(chip->dev, "read status low failed with %d\n", ret); + return IRQ_HANDLED; + } + + ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, 1); + if (ret) { + dev_err(chip->dev, "read status high failed with %d\n", ret); + return IRQ_HANDLED; + } + + for (i = 0; i < chip->nchannels; i++) { + bool upper_set = false, lower_set = false; + unsigned int ch = chip->channels[i].channel; + + if (!chip->channels[i].tzd) { + dev_err_once(chip->dev, "thermal device not found\n"); + continue; + } + + ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, 1); + + if (ret) { + dev_err(chip->dev, "ctl read failed with %d\n", ret); + continue; + } + + lower_set = (status_low & BIT(ch)) && + (ctl & ADC_TM5_M_MEAS_EN) && + (ctl & ADC_TM5_M_LOW_THR_INT_EN); + + upper_set = (status_high & BIT(ch)) && + (ctl & ADC_TM5_M_MEAS_EN) && + (ctl & ADC_TM5_M_HIGH_THR_INT_EN); + + if (upper_set || lower_set) + thermal_zone_device_update(chip->channels[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + return IRQ_HANDLED; +} + +static int adc_tm5_get_temp(void *data, int *temp) +{ + struct adc_tm5_channel *channel = data; + int ret, milli_celsius; + + if (!channel || !channel->iio) + return -EINVAL; + + ret = iio_read_channel_processed(channel->iio, &milli_celsius); + if (ret < 0) + return ret; + + *temp = milli_celsius; + + return 0; +} + +static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) +{ + struct adc_tm5_chip *chip = channel->chip; + unsigned int reg = ADC_TM5_M_EN(channel->channel); + + return adc_tm5_reg_update(chip, reg, + ADC_TM5_M_MEAS_EN | ADC_TM5_M_HIGH_THR_INT_EN | ADC_TM5_M_LOW_THR_INT_EN, + 0); +} + +static int adc_tm5_configure(struct adc_tm5_channel *channel, int low_temp, int high_temp) +{ + struct adc_tm5_chip *chip = channel->chip; + u8 buf[8]; + u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel); + int ret = 0; + + ret = adc_tm5_read(chip, reg, buf, 8); + if (ret) { + dev_err(chip->dev, "block read failed with %d\n", ret); + return ret; + } + + /* Update ADC channel select */ + buf[0] = channel->adc_channel; + + /* Warm temperature corresponds to low voltage threshold */ + if (high_temp != INT_MAX) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, high_temp); + + buf[1] = adc_code & 0xff; + buf[2] = adc_code >> 8; + buf[7] |= ADC_TM5_M_LOW_THR_INT_EN; + } + + /* Cool temperature corresponds to high voltage threshold */ + if (low_temp != -INT_MAX) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, low_temp); + + buf[3] = adc_code & 0xff; + buf[4] = adc_code >> 8; + buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN; + } + + /* Update timer select */ + buf[5] = ADC5_TIMER_SEL_2; + + /* Set calibration select, hw_settle delay */ + buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK; + buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time); + buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK; + buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method); + + buf[7] |= ADC_TM5_M_MEAS_EN; + + ret = adc_tm5_write(chip, reg, buf, 8); + if (ret) + dev_err(chip->dev, "buf write failed\n"); + + return ret; +} + +static int adc_tm5_set_trips(void *data, int low_temp, int high_temp) +{ + struct adc_tm5_channel *channel = data; + struct adc_tm5_chip *chip; + int ret; + + if (!channel) + return -EINVAL; + + chip = channel->chip; + dev_dbg(chip->dev, "%d:low_temp(mdegC):%d, high_temp(mdegC):%d\n", + channel->channel, low_temp, high_temp); + + if (high_temp == INT_MAX && low_temp <= -INT_MAX) + ret = adc_tm5_disable_channel(channel); + else + ret = adc_tm5_configure(channel, low_temp, high_temp); + + return ret; +} + +static struct thermal_zone_of_device_ops adc_tm5_ops = { + .get_temp = adc_tm5_get_temp, + .set_trips = adc_tm5_set_trips, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) +{ + unsigned int i; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc_tm->nchannels; i++) { + adc_tm->channels[i].chip = adc_tm; + + tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, + adc_tm->channels[i].channel, + &adc_tm->channels[i], + &adc_tm5_ops); + if (IS_ERR(tzd)) { + dev_err(adc_tm->dev, "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), adc_tm->channels[i].channel); + continue; + } + adc_tm->channels[i].tzd = tzd; + } + + return 0; +} + +static int adc_tm5_init(struct adc_tm5_chip *chip) +{ + u8 buf[4], channels_available; + int ret; + unsigned int i; + + ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, &channels_available, 1); + if (ret) { + dev_err(chip->dev, "read failed for BTM channels\n"); + return ret; + } + + ret = adc_tm5_read(chip, ADC_TM5_ADC_DIG_PARAM, buf, 4); + if (ret) { + dev_err(chip->dev, "block read failed with %d\n", ret); + return ret; + } + + /* Select decimation */ + buf[0] = chip->decimation; + + /* Select number of samples in fast average mode */ + buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; + + /* Select timer1 */ + buf[2] = ADC_TM5_TIMER1; + + /* Select timer2 and timer3 */ + buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) | + FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3); + + ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, 4); + if (ret) + dev_err(chip->dev, "block write failed with %d\n", ret); + + for (i = 0; i < chip->nchannels; i++) { + if (chip->channels[i].channel >= channels_available) { + dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); + return -EINVAL; + } + } + + return ret; +} + +static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, + struct adc_tm5_channel *channel, + struct device_node *node) +{ + const char *name = node->name; + u32 chan, value, varr[2]; + int ret; + struct device *dev = adc_tm->dev; + + ret = of_property_read_u32(node, "reg", &chan); + if (ret) { + dev_err(dev, "invalid channel number %s\n", name); + return ret; + } + + if (chan >= ADC_TM5_NUM_CHANNELS) { + dev_err(dev, "%s invalid channel number %d\n", name, chan); + return -EINVAL; + } + + /* the channel has DT description */ + channel->channel = chan; + + ret = of_property_read_u32(node, "qcom,adc-channel", &chan); + if (ret) { + dev_err(dev, "invalid channel number %s\n", name); + return ret; + } + if (chan >= ADC5_MAX_CHANNEL) { + dev_err(dev, "%s invalid ADC channel number %d\n", name, chan); + return ret; + } + channel->adc_channel = chan; + + channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL); + if (IS_ERR(channel->iio)) { + ret = PTR_ERR(channel->iio); + channel->iio = NULL; + dev_err(dev, "error getting channel %s: %d\n", name, ret); + return ret; + } + + ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) { + dev_err(dev, "%02x invalid pre-scaling <%d %d>\n", + chan, varr[0], varr[1]); + return ret; + } + channel->prescale = ret; + } else { + /* 1:1 prescale is index 0 */ + channel->prescale = 0; + } + + ret = of_property_read_u32(node, "qcom,hw-settle-time", &value); + if (!ret) { + ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); + if (ret < 0) { + dev_err(dev, "%02x invalid hw-settle-time %d us\n", + chan, value); + return ret; + } + channel->hw_settle_time = ret; + } else { + channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; + } + + if (of_property_read_bool(node, "qcom,ratiometric")) + channel->cal_method = ADC_TM5_RATIOMETRIC_CAL; + else + channel->cal_method = ADC_TM5_ABSOLUTE_CAL; + + return 0; +} + +static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) +{ + struct adc_tm5_channel *channels; + struct device_node *child; + unsigned int index = 0; + u32 value; + int ret; + struct device *dev = adc_tm->dev; + + adc_tm->nchannels = of_get_available_child_count(node); + if (!adc_tm->nchannels) + return -EINVAL; + + adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, + sizeof(*adc_tm->channels), GFP_KERNEL); + if (!adc_tm->channels) + return -ENOMEM; + + channels = adc_tm->channels; + + adc_tm->data = of_device_get_match_data(dev); + if (!adc_tm->data) + adc_tm->data = &adc_tm5_data_pmic; + + ret = of_property_read_u32(node, "qcom,decimation", &value); + if (!ret) { + ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); + if (ret < 0) { + dev_err(dev, "invalid decimation %d\n", value); + return ret; + } + adc_tm->decimation = ret; + } else { + adc_tm->decimation = ADC5_DECIMATION_DEFAULT; + } + + ret = of_property_read_u32(node, "qcom,avg-samples", &value); + if (!ret) { + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) { + dev_err(dev, "invalid avg-samples %d\n", value); + return ret; + } + adc_tm->avg_samples = ret; + } else { + adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; + } + + for_each_available_child_of_node(node, child) { + ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); + if (ret) { + of_node_put(child); + return ret; + } + + channels++; + index++; + } + + return 0; +} + +static int adc_tm5_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct adc_tm5_chip *adc_tm; + struct regmap *regmap; + int ret, irq; + u32 reg; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + ret = of_property_read_u32(node, "reg", ®); + if (ret) + return ret; + + adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); + if (!adc_tm) + return -ENOMEM; + + adc_tm->regmap = regmap; + adc_tm->dev = dev; + adc_tm->base = reg; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "get_irq failed: %d\n", irq); + return irq; + } + + ret = adc_tm5_get_dt_data(adc_tm, node); + if (ret) { + dev_err(dev, "get dt data failed: %d\n", ret); + return ret; + } + + ret = adc_tm5_init(adc_tm); + if (ret) { + dev_err(dev, "adc-tm init failed\n"); + return ret; + } + + ret = adc_tm5_register_tzd(adc_tm); + if (ret) { + dev_err(dev, "tzd register failed\n"); + return ret; + } + + return devm_request_irq(dev, irq, adc_tm5_isr, 0, + "pm-adc-tm5", adc_tm); +} + +static const struct of_device_id adc_tm5_match_table[] = { + { + .compatible = "qcom,spmi-adc-tm5", + .data = &adc_tm5_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc_tm5_match_table); + +static struct platform_driver adc_tm5_driver = { + .driver = { + .name = "qcom-spmi-adc-tm5", + .of_match_table = adc_tm5_match_table, + }, + .probe = adc_tm5_probe, +}; +module_platform_driver(adc_tm5_driver); + +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Sep 9 14:42:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 250346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AC2DC433E2 for ; Wed, 9 Sep 2020 17:21:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C3BD2087C for ; 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Wed, 09 Sep 2020 07:43:30 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:43:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 09/10] arm64: dts: qcom: pm8150x: add definitions for adc-tm5 part Date: Wed, 9 Sep 2020 17:42:47 +0300 Message-Id: <20200909144248.54327-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define adc-tm5 thermal monitoring part. Individual channes and thermal zones are to be configured in per-device dts files. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm8150b.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm8150l.dtsi | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 1b6406927509..b1b518c6a2c9 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -97,6 +97,16 @@ die-temp@6 { }; }; + pm8150_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index e112e8876db6..8e2f3250c914 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -95,6 +95,16 @@ chg-temp@9 { }; }; + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150b_gpios: gpio@c000 { compatible = "qcom,pm8150b-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 62139538b7d9..9f214ceec2b7 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -89,6 +89,16 @@ die-temp@6 { }; }; + pm8150l_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150l_gpios: gpio@c000 { compatible = "qcom,pm8150l-gpio"; reg = <0xc000>; From patchwork Wed Sep 9 14:42:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 250347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29153C433E2 for ; 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Wed, 09 Sep 2020 07:43:33 -0700 (PDT) Received: from eriador.lan ([188.162.64.155]) by smtp.gmail.com with ESMTPSA id t12sm621665lfk.26.2020.09.09.07.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 07:43:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 10/10] arm64: dts: sm8250-mtp: add thermal zones using pmic's adc-tm5 Date: Wed, 9 Sep 2020 17:42:48 +0300 Message-Id: <20200909144248.54327-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> References: <20200909144248.54327-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Port thermal zones definitions from msm-4.19 tree. Enable and add channel configuration to PMIC's ADC-TM definitions. Declare thermal zones and respective trip points. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 212 ++++++++++++++++++++++++ 1 file changed, 212 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 6894f8490dae..d524cc5a0816 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -24,6 +24,104 @@ chosen { stdout-path = "serial0:115200n8"; }; + thermal-zones { + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -358,6 +456,120 @@ &cdsp { firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm1@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc { + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc { + camera-flash-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-msm-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm2@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-therm@1 { + reg = <1>; + io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm1@2 { + reg = <2>; + io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc_tm { + status = "okay"; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + status = "okay"; + + camera-flash-therm@0 { + reg = <0>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm2@2 { + reg = <2>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + &qupv3_id_1 { status = "okay"; };