From patchwork Fri Sep 11 08:07:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Camel Guo X-Patchwork-Id: 291760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB7CCC433E2 for ; Fri, 11 Sep 2020 08:09:06 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3625208FE for ; Fri, 11 Sep 2020 08:09:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="ZmGqyRQU"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=axis.com header.i=@axis.com header.b="TMbNTQfP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3625208FE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=axis.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 235961658; Fri, 11 Sep 2020 10:08:14 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 235961658 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1599811744; bh=C5m3RosdUvw/L8jpqQPJR6i8hfS4Qd3wM9VnYLKpAjQ=; h=From:To:Subject:Date:Cc:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From; b=ZmGqyRQUvU5w565dikWwplgHpcF98OVEu6n5uZOg7GgsrvGswEer40JkpyZzg6mOY DpueWKABxWgR6CiN7+SOV027UDa30Rj8YvbNs/UM2wLGVQ3jT3IqEoZd1jUFADqbBJ S5y5QU+oUWEA9g4slqd/RQ/p6C3E7nBCXdVivHOs= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id A0AF8F80240; Fri, 11 Sep 2020 10:08:13 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id C3283F80240; Fri, 11 Sep 2020 10:08:10 +0200 (CEST) Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id CB66DF80115 for ; Fri, 11 Sep 2020 10:08:03 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz CB66DF80115 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=axis.com header.i=@axis.com header.b="TMbNTQfP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; l=2770; q=dns/txt; s=axis-central1; t=1599811684; x=1631347684; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cPa4cUMFiotpZ68Fm/qKTiIofFwHyG7dO+acVYumhHg=; b=TMbNTQfPV3HcwVwEfOLVVtdj3X4q0Ip7QoKH5fcduBYr4gK+i0irCMEt s8vPwTny3dhkCk7iDGdD0yXcgwGkpk+9RSuWDi9OsMySwlPDAaXpcUfKK jGcD8XbzeCj0uGfewINj3dTwoSlryDBzwz7lORw3py/bddD/WLiomZf1H EZFz3sC2/Z4ou9vr3kDwoToOfHsT0H3RlF3shz8Mm4FRSr26ExbVXB66b TzXFO7mzd+LXbs8KfRe8ktVeIAt+MXI7FI5rX2+VCa52juabvfFpt89Km EB2Gl8LLEheWL55H9K2lW75HpoW5EZW0TjnxN1ZNVb5+iRIvakM9KUklB w==; IronPort-SDR: 3tkqyX7XKLPM/R6pI8Xcz34ofl09t0Fwhm+XpilNpZqxb+Pa6otPLkk4027QJuX553TRbIioiQ z+y5l2YxCN97cn+I1nhuY/7QwdyDkP4UpLAwN/h5hZ5vCefBBq4EYjMDbIVbAAvAF2Klk5Ngra /lWUI20C163PB9adsex6cX+505NFBlMuPQTGpoELj5eg7kTw7lhh6jZq4QUXFyR9sLqlQdnQOy ctmei6aGyoYN+R6Yf65C4GKTMY7uHk4BxRB+KsPUOX6QjSaApUMesrk9WiG76y8obKquwrvAIX n9g= X-IronPort-AV: E=Sophos;i="5.76,414,1592863200"; d="scan'208";a="12818358" From: Camel Guo To: , , , Subject: [PATCH v2 1/3] dt-bindings: tlv320adcx140: Add GPIO config and drive config Date: Fri, 11 Sep 2020 10:07:51 +0200 Message-ID: <20200911080753.30342-1-camel.guo@axis.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, kernel@axis.com, linux-kernel@vger.kernel.org, Camel Guo X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Camel Guo Add properties for configuring the General Purpose Input Outputs (GPIO). There are 2 settings for GPIO, configuration and the output drive type. Signed-off-by: Camel Guo --- .../bindings/sound/tlv320adcx140.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml b/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml index f578f17f3e04..7b0b4554da59 100644 --- a/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml +++ b/Documentation/devicetree/bindings/sound/tlv320adcx140.yaml @@ -134,6 +134,49 @@ patternProperties: 4d - Drive weak low and active high 5d - Drive Hi-Z and active high + ti,gpio-config: + description: | + Defines the configuration and output driver for the general purpose + input and output pin (GPIO1). Its value is a pair, the first value is for + the configuration type and the second value is for the output drive + type. The array is defined as + + configuration for the GPIO pin can be one of the following: + 0 - disabled + 1 - GPIO1 is configured as a general-purpose output (GPO) + 2 - (default) GPIO1 is configured as a device interrupt output (IRQ) + 3 - GPIO1 is configured as a secondary ASI output (SDOUT2) + 4 - GPIO1 is configured as a PDM clock output (PDMCLK) + 8 - GPIO1 is configured as an input to control when MICBIAS turns on or + off (MICBIAS_EN) + 9 - GPIO1 is configured as a general-purpose input (GPI) + 10 - GPIO1 is configured as a master clock input (MCLK) + 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN) + 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2 + (PDMDIN1) + 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4 + (PDMDIN2) + 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6 + (PDMDIN3) + 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8 + (PDMDIN4) + + output drive type for the GPIO pin can be one of the following: + 0 - Hi-Z output + 1 - Drive active low and active high + 2 - (default) Drive active low and weak high + 3 - Drive active low and Hi-Z + 4 - Drive weak low and active high + 5 - Drive Hi-Z and active high + + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 2 + maxItems: 2 + items: + maximum: 15 + default: [2, 2] + required: - compatible - reg @@ -150,6 +193,7 @@ examples: ti,mic-bias-source = <6>; ti,pdm-edge-select = <0 1 0 1>; ti,gpi-config = <4 5 6 7>; + ti,gpio-config = <10 2>; ti,gpo-config-1 = <0 0>; ti,gpo-config-2 = <0 0>; reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; From patchwork Fri Sep 11 08:07:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Camel Guo X-Patchwork-Id: 251069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD345C433E2 for ; Fri, 11 Sep 2020 08:10:00 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 874FE20659 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=axis.com; l=2561; q=dns/txt; s=axis-central1; t=1599811689; x=1631347689; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GWBdvjMgI+JP9kgF51iEb5ue97etB2/mb8U6CHpN/hI=; b=n4BdKmCWWk1jk/sNZk3r+1at4o7MseCCN0RK9IHaN9I7qPlshDzf5+jy /FaQmd9hLO33CKKzfzZE8OxJfYOxS/j/S3fWSPxgVTXVWdegINvfxH8cA ALMYJB000J3C6Wr0/eqSnf/0+2iVTLUEueps5wsnyoGbMkrEeiEdzXWSl hxf4ecO9nYugjqRSybBYkbJyux1p12t4CWW7wno+974kDFcz64RiQoi3w MOiOnKLTuKAC5NFmopJaS9WJ5s4FN9JivGcqPWTFEoFbhtD/0WJYs70LW Wd+1uz1KIRk99jQ6Q0EpHO2O0DLfLiV9GixfuCOOH7LR9fhe8KeO+HllS w==; IronPort-SDR: BnKEjPvVZxmSMPmALemYWoYMsfP1TELibKrRlQoks6qxAV//kiy6uMQ0GTli5SCk6uimuC/xtS qCm3LqGWCS1mvMbzSh1Y2aT28dhxqmxZGc/bL6ZJ5bk+4HgXB9NX+1x4vcP7nPcWSrrkFOYJT3 /LlKjgAsNG39TEEP4d6JfvZx7/4t/9DvpYzMD0kikQIoB+6Dh9CkWj0dppvsTbdJvvq5t8k7Eo xJueWhdyMF06BPehVvBON+jekPq6UdtqWOUFDBJXXzR9dh/5X0eOfslW827MoML4YkPbgSIufg bsk= X-IronPort-AV: E=Sophos;i="5.76,414,1592863200"; d="scan'208";a="12818398" From: Camel Guo To: , , , Subject: [PATCH v2 2/3] ASoC: tlv320adcx140: Add support for configuring GPIO pin Date: Fri, 11 Sep 2020 10:07:52 +0200 Message-ID: <20200911080753.30342-2-camel.guo@axis.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200911080753.30342-1-camel.guo@axis.com> References: <20200911080753.30342-1-camel.guo@axis.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, kernel@axis.com, linux-kernel@vger.kernel.org, Camel Guo X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Camel Guo Add support to configure the GPIO pin to the specific configuration. The GPIO pin can be configured as GPO, IRQ, SDOUT2, PDMCLK, MICBASE_EN, GPI, MCLK, SDIN, PDMDIN1, PDMDIN2, PDMDIN3 or PDMDIN4 and the output drive can be configured with various configuration. Signed-off-by: Camel Guo --- sound/soc/codecs/tlv320adcx140.c | 44 ++++++++++++++++++++++++++++++++ sound/soc/codecs/tlv320adcx140.h | 4 +++ 2 files changed, 48 insertions(+) diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx140.c index f33ee604ee78..97f16fbba441 100644 --- a/sound/soc/codecs/tlv320adcx140.c +++ b/sound/soc/codecs/tlv320adcx140.c @@ -837,6 +837,46 @@ static int adcx140_configure_gpo(struct adcx140_priv *adcx140) } +static int adcx140_configure_gpio(struct adcx140_priv *adcx140) +{ + int gpio_count = 0; + u32 gpio_outputs[2]; + u32 gpio_output_val = 0; + int ret; + + gpio_count = device_property_count_u32(adcx140->dev, + "ti,gpio-config"); + if (gpio_count == 0) + return 0; + + if (gpio_count != 2) + return -EINVAL; + + ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config", + gpio_outputs, gpio_count); + if (ret) + return ret; + + if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) { + dev_err(adcx140->dev, "GPIO config out of range\n"); + return -EINVAL; + } + + if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) { + dev_err(adcx140->dev, "GPIO drive out of range\n"); + return -EINVAL; + } + + gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT + | gpio_outputs[1]; + + ret = regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val); + if (ret) + return ret; + + return 0; +} + static int adcx140_codec_probe(struct snd_soc_component *component) { struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); @@ -934,6 +974,10 @@ static int adcx140_codec_probe(struct snd_soc_component *component) return ret; } + ret = adcx140_configure_gpio(adcx140); + if (ret) + return ret; + ret = adcx140_configure_gpo(adcx140); if (ret) goto out; diff --git a/sound/soc/codecs/tlv320adcx140.h b/sound/soc/codecs/tlv320adcx140.h index eedbc1d7221f..96f067e65e2a 100644 --- a/sound/soc/codecs/tlv320adcx140.h +++ b/sound/soc/codecs/tlv320adcx140.h @@ -145,4 +145,8 @@ #define ADCX140_GPO_CFG_MAX 4 #define ADCX140_GPO_DRV_MAX 5 +#define ADCX140_GPIO_SHIFT 4 +#define ADCX140_GPIO_CFG_MAX 15 +#define ADCX140_GPIO_DRV_MAX 5 + #endif /* _TLV320ADCX140_ */ From patchwork Fri Sep 11 08:07:53 2020 Content-Type: text/plain; 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t=1599811692; x=1631347692; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eO+zTlfW52CayMzwiMc5LkDQ62LE8ZAr9cOy6EuS3R8=; b=PgwEQbpRoDyP33l0gHssNl6N2uC8rK3tQjrMfRjY/DXyOJ5I1RGd3Qrj e709I/+VT4TXXNxFT5FyW65BZDhOh6xogTn7bbDVdv41W65D5Hr5tx5zO JcdCbbpmnM0YW9knKNZwyf6nmRFB9M2iiE7+t2QcnP2viaMR5UwAt/QDG 5eeGQ7Vh0kMiy4552J0jdNscOzRfpfdswAfV9kamBhT9mc4WXilIOJUBY fxXPOrj6wUjuXqSL7KDNT02HqlY2mlYmUj5VYuD0jKn3Ef7upNk8mbfwu PYSQPDKSDdRuywYQ34xefLXRZ9+BhWpfFf1lGrPEHDzq+TMhtPSL8VC+m A==; IronPort-SDR: c5MZVV8Z0QXbTjZzPNPTzZ9iQdkR1ZZQ1NZus8kUuW3rRy8FxVoNVQFf0n4qxRiWrP7Ggf/3SC hYuCM6nxPiLlN6l8Dl8vArS8w9tPX2zDaMHyiWIBH4SolCaO+BeI2Ned9kp589UO4K2Qzxcwi7 huxj/DKWJpvNqYwMH2s8t9Lx9Mw5xdNiL3W7qxNEGD17ilqflsFoaykR/yCkFttVx++85anpr6 vUC5m+g/CMvthZufMVrlnk4xW+EF4AlMWrQOo96lq6S2y2a28vNjZ+IF3MMAOWzofhVCDgxsd/ MLg= X-IronPort-AV: E=Sophos;i="5.76,414,1592863200"; d="scan'208";a="12818407" From: Camel Guo To: , , , Subject: [PATCH v2 3/3] ASoC: tlv320adcx140: Add proper support for master mode Date: Fri, 11 Sep 2020 10:07:53 +0200 Message-ID: <20200911080753.30342-3-camel.guo@axis.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200911080753.30342-1-camel.guo@axis.com> References: <20200911080753.30342-1-camel.guo@axis.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, kernel@axis.com, linux-kernel@vger.kernel.org, Camel Guo X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Camel Guo Add setup of bclk-to-ws ratio and sample rate when in master mode, as well as MCLK input pin setup. Signed-off-by: Camel Guo --- v2: - Move GPIO setting into devicetree - Move master config register setting into a new function sound/soc/codecs/tlv320adcx140.c | 139 ++++++++++++++++++++++++++++++- sound/soc/codecs/tlv320adcx140.h | 27 ++++++ 2 files changed, 162 insertions(+), 4 deletions(-) diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx140.c index 97f16fbba441..685f5fd8b537 100644 --- a/sound/soc/codecs/tlv320adcx140.c +++ b/sound/soc/codecs/tlv320adcx140.c @@ -35,6 +35,7 @@ struct adcx140_priv { unsigned int dai_fmt; unsigned int tdm_delay; unsigned int slot_width; + bool master; }; static const char * const gpo_config_names[] = { @@ -651,11 +652,136 @@ static int adcx140_reset(struct adcx140_priv *adcx140) return ret; } +static int adcx140_fs_bclk_ratio(unsigned int bclk_ratio) +{ + switch (bclk_ratio) { + case 16: + return ADCX140_RATIO_16; + case 24: + return ADCX140_RATIO_24; + case 32: + return ADCX140_RATIO_32; + case 48: + return ADCX140_RATIO_48; + case 64: + return ADCX140_RATIO_64; + case 96: + return ADCX140_RATIO_96; + case 128: + return ADCX140_RATIO_128; + case 192: + return ADCX140_RATIO_192; + case 256: + return ADCX140_RATIO_256; + case 384: + return ADCX140_RATIO_384; + case 512: + return ADCX140_RATIO_512; + case 1024: + return ADCX140_RATIO_1024; + case 2048: + return ADCX140_RATIO_2048; + default: + break; + } + return -EINVAL; +} + +static int adcx140_fs_rate(unsigned int rate) +{ + switch (rate) { + case 7350: + case 8000: + return ADCX140_8_OR_7_35KHZ; + case 14700: + case 16000: + return ADCX140_16_OR_14_7KHZ; + case 22050: + case 24000: + return ADCX140_24_OR_22_05KHZ; + case 29400: + case 32000: + return ADCX140_32_OR_29_4KHZ; + case 44100: + case 48000: + return ADCX140_48_OR_44_1KHZ; + case 88200: + case 96000: + return ADCX140_96_OR_88_2KHZ; + case 176400: + case 192000: + return ADCX140_192_OR_176_4KHZ; + case 352800: + case 384000: + return ADCX140_384_OR_352_8KHZ; + case 705600: + case 768000: + return ADCX140_768_OR_705_6KHZ; + default: + break; + } + return -EINVAL; +} + +static int adcx140_setup_master_config(struct snd_soc_component *component, + struct snd_pcm_hw_params *params) +{ + int ret = 0; + struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); + + if (adcx140->master) { + u8 mst_cfg1 = 0; + u8 mst_cfg0 = 0; + unsigned int bclk_ratio; + + mst_cfg0 = ADCX140_BCLK_FSYNC_MASTER; + if (params_rate(params) % 1000) + mst_cfg0 |= ADCX140_FSYNCINV_BIT; /* 44.1 kHz et al */ + + ret = adcx140_fs_rate(params_rate(params)); + if (ret < 0) { + dev_err(adcx140->dev, "%s: Unsupported rate %d\n", + __func__, params_rate(params)); + return ret; + } + mst_cfg1 |= ret; + + /* In slave mode when using automatic clock configuration, + * the codec figures out the BCLK to FSYNC ratio itself. But + * here in master mode, we need to tell it. + */ + + bclk_ratio = snd_soc_params_to_frame_size(params); + ret = adcx140_fs_bclk_ratio(bclk_ratio); + if (ret < 0) { + dev_err(adcx140->dev, "%s: Unsupported bclk_ratio %d\n", + __func__, bclk_ratio); + return ret; + } + mst_cfg1 |= ret; + + snd_soc_component_update_bits(component, ADCX140_MST_CFG1, + ADCX140_FS_RATE_MSK | + ADCX140_RATIO_MSK, + mst_cfg1); + + snd_soc_component_update_bits(component, ADCX140_MST_CFG0, + ADCX140_FSYNCINV_BIT | + ADCX140_BCLK_FSYNC_MASTER, + mst_cfg0); + + } + + return ret; +} + + static int adcx140_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_component *component = dai->component; + int ret = 0; u8 data = 0; switch (params_width(params)) { @@ -677,6 +803,13 @@ static int adcx140_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + ret = adcx140_setup_master_config(component, params); + if (ret < 0) { + dev_err(component->dev, "%s: Failed to set up master config\n", + __func__); + return ret; + } + snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, ADCX140_WORD_LEN_MSK, data); @@ -689,16 +822,16 @@ static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai, struct snd_soc_component *component = codec_dai->component; struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); u8 iface_reg1 = 0; - u8 iface_reg2 = 0; int offset = 0; int width = adcx140->slot_width; /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: - iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER; + adcx140->master = true; break; case SND_SOC_DAIFMT_CBS_CFS: + adcx140->master = false; break; case SND_SOC_DAIFMT_CBS_CFM: case SND_SOC_DAIFMT_CBM_CFS: @@ -751,8 +884,6 @@ static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai, ADCX140_BCLKINV_BIT | ADCX140_ASI_FORMAT_MSK, iface_reg1); - snd_soc_component_update_bits(component, ADCX140_MST_CFG0, - ADCX140_BCLK_FSYNC_MASTER, iface_reg2); /* Configure data offset */ snd_soc_component_update_bits(component, ADCX140_ASI_CFG1, diff --git a/sound/soc/codecs/tlv320adcx140.h b/sound/soc/codecs/tlv320adcx140.h index 96f067e65e2a..1fbb7fa3c73d 100644 --- a/sound/soc/codecs/tlv320adcx140.h +++ b/sound/soc/codecs/tlv320adcx140.h @@ -149,4 +149,31 @@ #define ADCX140_GPIO_CFG_MAX 15 #define ADCX140_GPIO_DRV_MAX 5 +/* MST_CFG1 */ +#define ADCX140_8_OR_7_35KHZ (0 << 4) +#define ADCX140_16_OR_14_7KHZ (1 << 4) +#define ADCX140_24_OR_22_05KHZ (2 << 4) +#define ADCX140_32_OR_29_4KHZ (3 << 4) +#define ADCX140_48_OR_44_1KHZ (4 << 4) +#define ADCX140_96_OR_88_2KHZ (5 << 4) +#define ADCX140_192_OR_176_4KHZ (6 << 4) +#define ADCX140_384_OR_352_8KHZ (7 << 4) +#define ADCX140_768_OR_705_6KHZ (8 << 4) +#define ADCX140_FS_RATE_MSK GENMASK(7, 4) + +#define ADCX140_RATIO_16 0 +#define ADCX140_RATIO_24 1 +#define ADCX140_RATIO_32 2 +#define ADCX140_RATIO_48 3 +#define ADCX140_RATIO_64 4 +#define ADCX140_RATIO_96 5 +#define ADCX140_RATIO_128 6 +#define ADCX140_RATIO_192 7 +#define ADCX140_RATIO_256 8 +#define ADCX140_RATIO_384 9 +#define ADCX140_RATIO_512 10 +#define ADCX140_RATIO_1024 11 +#define ADCX140_RATIO_2048 12 +#define ADCX140_RATIO_MSK GENMASK(3, 0) + #endif /* _TLV320ADCX140_ */