From patchwork Fri Oct 13 12:50:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 115767 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp688355edb; Fri, 13 Oct 2017 05:51:49 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDF/x6gSMpjhMW84EHTpw4p1nmfo5K55iGaRcRPNWmD55cAUunByZ3tMLJXH2BkCNYsOnjT X-Received: by 10.98.237.20 with SMTP id u20mr243125pfh.237.1507899109546; Fri, 13 Oct 2017 05:51:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507899109; cv=none; d=google.com; s=arc-20160816; b=uPeDahXJrWaD14sfgHFHjrdWICDt7M1k7JyMZwhVWLzTvsIHNvYLvhs/lHEbmxAUwU EfCCfHx7AgwZY0kbsLUg/2UhxXMqxUikcL8S9MawQ3wS6HLoyrziVOy8xYI1aKuYVWYJ 8KWNVw7bg/0nTRYzIo94Sfm5NA4nF9Ld8OM1uhYfVAQWwQGKe4wlL+AZ98x9JL2sdZMX E7dZpwaTUO6mMx+X8ZThbNoVAtzkTXL8t6h81M4lp/jzPPmG6DJbmmoWh4KsbGRnTSp3 ZOR/nvfvfh8fCv0MgqQJccsrz+4CRrFaFZoIYSobWCzdrj3H1y52ZpEK+0+N8yjwG0/C g85Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter:arc-authentication-results; bh=4MqdXmZOUKHJ0ZKefrIhgymxYlZyJ+yGH9G0v8hyEO8=; b=jLF577W0o4QfwV2ecBdcchq5rSf2eLmYlrYknilrHWXGCUIfvVFA6g+4yqCYyD7KsC /84FIkHuHRMXtsKBbxT+1F34J4rZNggEGgzGcFVAX0DRkOGzJQsdcWwnGFw8X5KEP/U4 wk6lrIjIqQCb4Ii+A5tOIOQN2mfMXpWgB3otWrU5cKoBJMSAWQQaf/7pdRTeVcQWWGXy NDFkeGH438MOc+UrW1SS6PZl8hpwkQUgsczz5EN2Yo5BmPKhBNLyrpzyiQHgSarvwrDp RFJ5WRRqDkT97kM77cQZ9zjOvBGpq0p/U8teyzRfDMg3S5pja7ivONtbxgjJeOBWKMAn MGFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=wbo0u6n1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12si599647pln.482.2017.10.13.05.51.49; Fri, 13 Oct 2017 05:51:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=wbo0u6n1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758560AbdJMMvr (ORCPT + 27 others); Fri, 13 Oct 2017 08:51:47 -0400 Received: from conuserg-08.nifty.com ([210.131.2.75]:25718 "EHLO conuserg-08.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758544AbdJMMvp (ORCPT ); Fri, 13 Oct 2017 08:51:45 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-08.nifty.com with ESMTP id v9DCp7FU016824; Fri, 13 Oct 2017 21:51:07 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com v9DCp7FU016824 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1507899067; bh=4MqdXmZOUKHJ0ZKefrIhgymxYlZyJ+yGH9G0v8hyEO8=; h=From:To:Cc:Subject:Date:From; b=wbo0u6n1uDtwtI59aIabeqwXhFlm8TSc/NjSxkWc2rrpxQUrYB3SdDQ/iU8id3kOx lShaq4EuYtEehnJR/Fr5BH2Njgj0IQyTyF3mpeYq8Cf/Im0JocGNa0/gGZAYXbQvuR 6jP+zGSe/vn+2e+FyM+hiKXw2RcxPV1OtrP29JfiPk7rjqhwkAUMBc+T5zAi6Px4ia mDfBviMZt1HBWU1bCK3268P10mRUeJhUvJUBEBENmCEmR70cuprdbAG9C4bcZ6U12f EqtPQuRuhbeQngnGOb7fu9Nn5LmWXeb5Jff5KThiXLW1j8UtAoURtt73BqwlTJf87S ZC4xJfp2qRfRw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mmc@vger.kernel.org Cc: Piotr Sroka , Masahiro Yamada , linux-kernel@vger.kernel.org, Adrian Hunter , Ulf Hansson Subject: [PATCH] mmc: sdhci-cadence: use bitfield access macros for cleanup Date: Fri, 13 Oct 2017 21:50:31 +0900 Message-Id: <1507899031-1245-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Accessing register fields generally need mask and shift part. Defining them separately, like SDHCI_CDNS_HRS06_TUNE_{SHIFT,MASK}, is tedious. Register fields can be always defined by GENMASK (or, BIT if it it a single bit). They are nicely handled by FIELD_* macros. Signed-off-by: Masahiro Yamada --- drivers/mmc/host/sdhci-cadence.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 56529c3..0f589e2 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,15 +28,14 @@ #define SDHCI_CDNS_HRS04_ACK BIT(26) #define SDHCI_CDNS_HRS04_RD BIT(25) #define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16 -#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 -#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 +#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16) +#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8) +#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0) #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */ #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15) -#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8 -#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f -#define SDHCI_CDNS_HRS06_MODE_MASK 0x7 +#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8) +#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0) #define SDHCI_CDNS_HRS06_MODE_SD 0x0 #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2 #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3 @@ -105,8 +105,8 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u32 tmp; int ret; - tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | - (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); + tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | + FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); writel(tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; @@ -189,8 +189,8 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) /* The speed mode for eMMC is selected by HRS06 register */ tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); - tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK; - tmp |= mode; + tmp &= ~SDHCI_CDNS_HRS06_MODE; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } @@ -199,7 +199,7 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) u32 tmp; tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); - return tmp & SDHCI_CDNS_HRS06_MODE_MASK; + return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp); } static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, @@ -254,12 +254,12 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06; u32 tmp; - if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK)) + if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) return -EINVAL; tmp = readl(reg); - tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT); - tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT; + tmp &= ~SDHCI_CDNS_HRS06_TUNE; + tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); tmp |= SDHCI_CDNS_HRS06_TUNE_UP; writel(tmp, reg);