From patchwork Wed Oct 18 11:31:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 116265 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5952388qgn; Wed, 18 Oct 2017 04:32:25 -0700 (PDT) X-Google-Smtp-Source: ABhQp+STKY6WWtluTUJ0ViWDcK5n3SLdyCddlnGhmlqAkw+cNTYA6Jl57URE01+0XE+IZ4gQU+cG X-Received: by 10.28.173.131 with SMTP id w125mr6710551wme.126.1508326344967; Wed, 18 Oct 2017 04:32:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508326344; cv=none; d=google.com; s=arc-20160816; b=maY4tYHi3XOWUODb0NWZ2j5j5tWDLp0pd+Xwfy5cI4YRV6fXmLWMTCk75UvfiBq/PZ 4Z9rCdzCTzw2m0GlvHIH6x1RLcwzoief5QQAORHo0DV6ORSbLmL4G1qsO7KfFD+C4tk5 uDpP2wGzPpMPpzskfK4eNNKP9c6oQorEM1wBoGeGimjPrPUKjLbOByL6SJQZiOdRN+JT p8igm1IQjSc8WHCQzgVZlX4Q+GBkzSdCPZ5/682EuPKKxBfofruzomZF9wv6qwP9AzWa zJZeV4f8SXOjuepivyVMVUZFAV909r/hurWnmRYm8wOGjDP5g4iqrSAq57zlazE6Uha/ ZfVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:date:message-id:in-reply-to:to:from :dkim-signature:delivered-to:arc-authentication-results; bh=BhX3lftGJeRs0j6EHTBpRoXuy01KmqOrqtLQTS9bxLM=; b=B9oQzuvhaoq9zMkh7ZWm6RvA6cfO1odK4tHeAy+y1dNQjr9hzeIqyW9ikJlzMsP/MV ntHiL/3trN2bihNAd3qhGmWb2Mp1eQTh+y5YB6Rps99M6TC1BDNaWxLu+wJPuUJRfTmZ 5Yal3RZeb7ZXHtcwn03dFcpn3eZ5C4lbAyP6D674EdebOqKkTfVBIeH2Zw/GSPJ2LGel VtWxc13agXICkm+DW3h17jyaK5niMLHZBxoDUxu3zC3ZV7Mso4IXkJQBM7JsDK5UVcZr 4MJ9pwgpQkiXJh25v9ly18XQZb64e8tCLpc+lEtWeqbPZw75E7rQ4jYrSIEjFitihuCi OB+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=wq8FduGe; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id m22si234546wrf.135.2017.10.18.04.32.23; Wed, 18 Oct 2017 04:32:24 -0700 (PDT) Received-SPF: pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) client-ip=77.48.224.243; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=wq8FduGe; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 7CEE5267449; Wed, 18 Oct 2017 13:31:34 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id B85BA267495; Wed, 18 Oct 2017 13:31:33 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, SPF_PASS autolearn=disabled version=3.4.0 Received: from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk [172.104.155.198]) by alsa0.perex.cz (Postfix) with ESMTP id DAFAF26746C for ; Wed, 18 Oct 2017 13:31:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=sxGeupz+TfE8Bq+QGA9gw+gctJJ14tQApPVaYnQqq0k=; b=wq8FduGeMYpL d5YfkQnGWHgWwFWJfhJABXHPujR5hZuELy1oeLBIpqTFuZ36kfXnepHi4i6fbu2LTcIL5OhuQQB+m D74M1Kycq9SYdpFLx/zFsxBX46cOjMHCxhm6SoPDjEeQgAN3c+YQdxOF4JWCypbwyVPXZBBu8uqK+ mnrjQ=; Received: from debutante.sirena.org.uk ([2001:470:1f1d:6b5::3] helo=debutante) by heliosphere.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1e4mZF-0007Wp-DV; Wed, 18 Oct 2017 11:31:21 +0000 Received: from broonie by debutante with local (Exim 4.89) (envelope-from ) id 1e4mZF-0003yH-0n; Wed, 18 Oct 2017 12:31:21 +0100 From: Mark Brown To: Pierre-Louis Bossart In-Reply-To: <20171005185243.4174-5-pierre-louis.bossart@linux.intel.com> Message-Id: Date: Wed, 18 Oct 2017 12:31:21 +0100 Cc: alsa-devel@alsa-project.org, tiwai@suse.de, Liam Girdwood , vinod.koul@intel.com, broonie@kernel.org, Andy Shevchenko Subject: [alsa-devel] Applied "ASoC: Intel: cht_bsw_rt5645: cosmetic fixes" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: Intel: cht_bsw_rt5645: cosmetic fixes has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 6cdf01a5addfd3a2b2918fccc76535f20eb2cda9 Mon Sep 17 00:00:00 2001 From: Pierre-Louis Bossart Date: Thu, 12 Oct 2017 18:37:59 -0500 Subject: [PATCH] ASoC: Intel: cht_bsw_rt5645: cosmetic fixes Reorder variable names, change MCLK test, change quirks No functional change Suggested-by: Andy Shevchenko Signed-off-by: Pierre-Louis Bossart Acked-by: Liam Girdwood Reviewed-by: Andy Shevchenko Signed-off-by: Mark Brown --- sound/soc/intel/boards/cht_bsw_rt5645.c | 73 ++++++++++++++++----------------- 1 file changed, 35 insertions(+), 38 deletions(-) -- 2.14.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/intel/boards/cht_bsw_rt5645.c b/sound/soc/intel/boards/cht_bsw_rt5645.c index d553e2b67c92..6ccb599c1082 100644 --- a/sound/soc/intel/boards/cht_bsw_rt5645.c +++ b/sound/soc/intel/boards/cht_bsw_rt5645.c @@ -21,13 +21,13 @@ */ #include -#include #include +#include +#include #include #include #include #include -#include #include #include #include @@ -53,7 +53,7 @@ struct cht_mc_private { struct clk *mclk; }; -#define CHT_RT5645_MAP(quirk) ((quirk) & 0xff) +#define CHT_RT5645_MAP(quirk) ((quirk) & GENMASK(7, 0)) #define CHT_RT5645_SSP2_AIF2 BIT(16) /* default is using AIF1 */ #define CHT_RT5645_SSP0_AIF1 BIT(17) #define CHT_RT5645_SSP0_AIF2 BIT(18) @@ -101,13 +101,11 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, } if (SND_SOC_DAPM_EVENT_ON(event)) { - if (ctx->mclk) { - ret = clk_prepare_enable(ctx->mclk); - if (ret < 0) { - dev_err(card->dev, - "could not configure MCLK state"); - return ret; - } + ret = clk_prepare_enable(ctx->mclk); + if (ret < 0) { + dev_err(card->dev, + "could not configure MCLK state"); + return ret; } } else { /* Set codec sysclk source to its internal clock because codec PLL will @@ -122,8 +120,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, return ret; } - if (ctx->mclk) - clk_disable_unprepare(ctx->mclk); + clk_disable_unprepare(ctx->mclk); } return 0; @@ -258,11 +255,11 @@ static const struct dmi_system_id cht_rt5645_quirk_table[] = { static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) { - int ret; - int jack_type; - struct snd_soc_codec *codec = runtime->codec; struct snd_soc_card *card = runtime->card; struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card); + struct snd_soc_codec *codec = runtime->codec; + int jack_type; + int ret; if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) || (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) { @@ -320,26 +317,26 @@ static int cht_codec_init(struct snd_soc_pcm_runtime *runtime) rt5645_set_jack_detect(codec, &ctx->jack, &ctx->jack, &ctx->jack); - if (ctx->mclk) { - /* - * The firmware might enable the clock at - * boot (this information may or may not - * be reflected in the enable clock register). - * To change the rate we must disable the clock - * first to cover these cases. Due to common - * clock framework restrictions that do not allow - * to disable a clock that has not been enabled, - * we need to enable the clock first. - */ - ret = clk_prepare_enable(ctx->mclk); - if (!ret) - clk_disable_unprepare(ctx->mclk); - ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); + /* + * The firmware might enable the clock at + * boot (this information may or may not + * be reflected in the enable clock register). + * To change the rate we must disable the clock + * first to cover these cases. Due to common + * clock framework restrictions that do not allow + * to disable a clock that has not been enabled, + * we need to enable the clock first. + */ + ret = clk_prepare_enable(ctx->mclk); + if (!ret) + clk_disable_unprepare(ctx->mclk); + + ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ); + + if (ret) + dev_err(runtime->dev, "unable to set MCLK rate\n"); - if (ret) - dev_err(runtime->dev, "unable to set MCLK rate\n"); - } return ret; } @@ -545,15 +542,15 @@ struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */ static int snd_cht_mc_probe(struct platform_device *pdev) { - int ret_val = 0; - int i; - struct cht_mc_private *drv; struct snd_soc_card *card = snd_soc_cards[0].soc_card; struct sst_acpi_mach *mach; + struct cht_mc_private *drv; const char *i2c_name = NULL; - int dai_index = 0; bool found = false; bool is_bytcr = false; + int dai_index = 0; + int ret_val = 0; + int i; drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC); if (!drv) @@ -590,7 +587,7 @@ static int snd_cht_mc_probe(struct platform_device *pdev) /* fixup codec name based on HID */ i2c_name = sst_acpi_find_name_from_hid(mach->id); - if (i2c_name != NULL) { + if (i2c_name) { snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name), "%s%s", "i2c-", i2c_name); cht_dailink[dai_index].codec_name = cht_rt5645_codec_name;