From patchwork Wed Oct 18 11:44:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116268 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5965133qgn; Wed, 18 Oct 2017 04:47:20 -0700 (PDT) X-Received: by 10.99.98.6 with SMTP id w6mr13611088pgb.189.1508327240845; Wed, 18 Oct 2017 04:47:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327240; cv=none; d=google.com; s=arc-20160816; b=vAy3TPbwcFxL9ByhZVXmgYFh7gOxra9aRU7bZw/uscFe67N0m4coevwqNjK98Jo+Te rjzC/hOpGQBFJH8ZzFU9L8KL4tVsWeA7+Ji+Zx8A4CBsHLiJ53Q39eLayhSaiOhwPHQu qKCQfS0JYLudhuCKg1jBYTsrlPuJ0dw47EBFe6RSzFg79hglpHdziAfPB2X4KkrDyu46 SAGezik5pGpGnzCHYrfdxEnA2Ao0IB5lvImaVgaEYEjZ+ZQPqvVBClRTVnQ2jPfi8yiw mH/nyWJjz6SRWJIlVexegC/DM6wwE6/Xa1LD/HIAcaVtwJA3rmwRFui/eYAVrfsaKO8/ qU9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=196DxAdiAIubhXPg58CYxaK7OcAX+X/0A5rx2xTS8Ns=; b=EvqfxBugJ+PwxDnyGGgUmTEKCCqdVyWd2MJlUQb6ZPtX70CBME/SRxvCGJE68dyG/h mviykGkw8f5k0MdQnLKnLBgdVXZwvNL0YDBjn6oFvjo+ut7pjuYTVpm9HkrlMEFVAosk 3kHOs+Fzw6W6jxveMefIyqocC6dNGVaTeeapoBt+9gQJc9zGvr80wJayy58Z8BxguwWF KNB5zqEmCS/5MYoGhsHdttRWhcJ7FzEfDzWCvlmIr4FPWLLlXmn4mQs0CvFThSVhe0TG ol1rzmj2rrL+hs/XQ8YZB0BJbyU63gMOyP9S+E4vq07aYGJwfaDaMEN9AIeqDMqRisN3 wz7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=fKWlvjvl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f6si7609860plt.152.2017.10.18.04.47.20; Wed, 18 Oct 2017 04:47:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=fKWlvjvl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932419AbdJRLrS (ORCPT + 27 others); Wed, 18 Oct 2017 07:47:18 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:44856 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754406AbdJRLrN (ORCPT ); Wed, 18 Oct 2017 07:47:13 -0400 Received: by mail-wr0-f195.google.com with SMTP id l24so4711480wre.1; Wed, 18 Oct 2017 04:47:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=196DxAdiAIubhXPg58CYxaK7OcAX+X/0A5rx2xTS8Ns=; b=fKWlvjvl6l4paefvJUVxddSFeod+0wB1dKrvEfDvfxbQMfCPycl4vVuZnR66B0qiC/ 7R4sjjpfDEfmG1MpqOB+irk5VfRZlNGU/y0tSpInTui7pmZPk8a3H4s6deuKe0Wn02AY iEYW2Am4DJKqKXm7uIZM3WqjmNRGSFEilYUxfV8lwSn8WnBG818+47KMLPi7YXhCTSgD 8cy3r2h8N+gNnL/w1IhaBMoV50rJ0VLNZb5A3apYjioJ9i/ET/959T4y5iJqhIxdejeg KLhWLdjCwTuOHW8II77tuT9nhn8HSmzNZvheaDUPsBeuUWRJK82eX3a355eCl1dzGtUC PkPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=196DxAdiAIubhXPg58CYxaK7OcAX+X/0A5rx2xTS8Ns=; b=ahwba5Yp6CcZlk4YZ2C6cZrGrS5p61gpSFXbupUHnJWUwWa08rYmRrmt7kozpoXjfh HB0nMXGWgoSmd37sWxorK+pSJNYFsDyE2/YS4R1SwXjhUtWfocnKH5QJpeDNkBfMjRud Y5tUkQ8sHNQKtRlkifkWZmqfYdzNMK/MeeQoWMwdR1JreSJSuW3A7wZJ9V0B6nEDWmwa QnBGHK4Dgr/2u/cn+HNmS0nox9NiUOqykTVJLQeYAH0K9C0L31+pfVAW+vc/UoUNnHuu ZXiVv430F/qu+3Pp2quQjQ8JMyQvGtM+SoiAbiyZg/o1U66iAeuzoJtyyWV59Da4KzUW KZ+g== X-Gm-Message-State: AMCzsaX1T+vWVUshmqb6zCYQ8/jqYdDGVpWRH/OpZFoEaXE38DI+2gcQ 3PBYmA8SbzQm6Ojz4Bemt08= X-Google-Smtp-Source: ABhQp+TVr+cPRT2E66R5hLCQwgxS92mWnbGzRmrrH7DibQsN13rCKH73Eco66L1IE7dxmBAI68LomA== X-Received: by 10.223.146.37 with SMTP id 34mr6309024wrj.79.1508327232228; Wed, 18 Oct 2017 04:47:12 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:11 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 01/10] dt-bindings: net: Restore sun8i dwmac binding Date: Wed, 18 Oct 2017 13:44:49 +0200 Message-Id: <20171018114458.17891-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt -- 2.13.6 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; From patchwork Wed Oct 18 11:44:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116277 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5967993qgn; Wed, 18 Oct 2017 04:50:50 -0700 (PDT) X-Received: by 10.159.197.73 with SMTP id d9mr14809740plo.415.1508327449921; Wed, 18 Oct 2017 04:50:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327449; cv=none; d=google.com; s=arc-20160816; b=U2yKINJcEm+GsuC2jrIX1Vq8+acmX5p/HYJPARLt1UzDbaIcB8Sz42l+EnFaBP3qJE rHScRe0248ZAkDhTLrz+omGCqTcB8IM31r5Y+CCLrjZJ/Xulo/1j4saeuD3+Cru5g8Q0 b5VxcmmwExe6d0YOzL0WJzetnp+XDY+8zME9vzHE9Kg5phWao4m3oIxjhkMawJuwRr+b VOOHHzwqITeTlvZVe+suV6DuSfCljNQ85bbtG1iVIp32ST8UTXThJNDgzSksmiJhXWtU IQ5C2hGRPFJAx7PHUWLiWVeprFOWuUfjYh6lvsKs2uaXph6T6fFT+nB52THjWZvD77Gt 7z3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5P+HlfgX3fVnMN7Pr03Rg2Aiuf8NHwIUrVNrT8eNeyo=; b=XOfbQ+v5JAFN3AFfxzyjC/JVUfdvYkQwIfsYIygPfoTy8avnkJo4wiCRkdfQDkHEbz EY4ab40A9JdJadj5n0uZpM6k+q6kk1tT5u+zC1RfdxWFfWr/C36P4MMUpR6TSJBMiSDa fO2h5fGa3EgPsDbmQ9uioBybBBBQjfzZGwdW4bub5hzluoCK6ikCFwTOZCNylclPfWyS DDrKM0vVGBXQC4qX1QSxEygh5uZ2UUF73x6HTCYc98iBEsnBR0Xo7MLgaRpMc07qdnO/ LaLLtzJC4mSBLMD5qF8mREzzF+UiMOPWG2oPXJjNfJWguJ7ROgcpIbCwHg+i2zziOePb 5Yzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BGThfYxC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d72si7304866pfe.596.2017.10.18.04.50.49; Wed, 18 Oct 2017 04:50:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=BGThfYxC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756042AbdJRLur (ORCPT + 27 others); Wed, 18 Oct 2017 07:50:47 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:50773 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754826AbdJRLrP (ORCPT ); Wed, 18 Oct 2017 07:47:15 -0400 Received: by mail-wr0-f193.google.com with SMTP id q42so4707979wrb.7; Wed, 18 Oct 2017 04:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5P+HlfgX3fVnMN7Pr03Rg2Aiuf8NHwIUrVNrT8eNeyo=; b=BGThfYxCoAJ93j//LsvbBSpx0UslatyqrZnLUF4I+VLnj0JYiiB6tREPQi8XHn5hzf 4CIgVOBbNWcPBG/bONB2riIHMmFeJY25ZWfJvyWyelSyUlsa7GGdv3LJuyDiXykWK5+h JC87Zp7gWVRmuuPg+1yYx1Qnt6t8LveV6hkbwwOuEZ38XAONX8tKYlJrGrR8WqyHDKU6 c5xEOIwBjYm0AmSbWkCZrD2VViqpnD7Oxz6LM7qcW+mzz8khYDIotquVI5v4luavWSMr LGDxSpqSnA4/bAWtom3hXcoNdPB3+d5RBDPpDb7p0nAlvzHR+7oQWsbGFuDibu4K+t0c m5Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5P+HlfgX3fVnMN7Pr03Rg2Aiuf8NHwIUrVNrT8eNeyo=; b=WJncK496ljvw819xdUqvlsmKT/DTUbq22t5Zgr0JEPcL6CM/MrbRqPOToDGgYHpKoA i+wYw6btE5R0cTXTzsqcrfKrcgVrf2ZnGX4Ao2/FS6ehKKPLlaD8oJPfLSGGBpSPHJZK QdseS2TbLkrOfUNSzBy5hGoVirNevBDNL3Zp2119zGUc7gBqgju8p7W3KiMDREPgA4UG 8ZaX1SKH2kTg5rgrlRpql96Py1lfWl8/K5bpqwctic2K5BlXMZ8HQby5F0aEcfvl13CF +leA/rE9/kUt36mayZqSHhT35C02+LDrug0qGSTOLCd9IJpu5MYWW1Ed99gVHqulLFRo 6oTw== X-Gm-Message-State: AMCzsaWY8G7ZuKj9Dtk5bVj/bfEjPDs16P1N/C5nncglw4MpZQacWVwQ MIbsweZiOO6MmtfUFvrxySo= X-Google-Smtp-Source: ABhQp+ShP9o2rtryupjaN1ZJiUFXdidLqwTRRuqgaU6iJQYg+kU03JmFmnRachG/l/ywU0hKBzHE4w== X-Received: by 10.223.136.218 with SMTP id g26mr6890618wrg.86.1508327233425; Wed, 18 Oct 2017 04:47:13 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:12 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 02/10] arm: dts: sunxi: Restore EMAC changes Date: Wed, 18 Oct 2017 13:44:50 +0200 Message-Id: <20171018114458.17891-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore arm DT about dwmac-sun8i This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 ++++++++ arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19 +++++++++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 +++++++++++++++++++++++ 11 files changed, 147 insertions(+) -- 2.13.6 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index b1502df7b509..6713d0f2b3f4 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -56,6 +56,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -102,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index e1dba9ffa94b..f2292deaa590 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -111,6 +112,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 73766d38ee6c..cfb96da3cfef 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -66,6 +66,25 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..78f6c24952dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,10 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 1bf51802f5aa..b20be95b49d5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index a1c6ff6fd05d..82e5d28cd698 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index d0b80fda2f6b..6d98bcfbe877 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 72ca01b93f1b..cbc499b04de4 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,10 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -74,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 97920b12a944..6dbf7b2e0c13 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -61,3 +61,19 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c1bd09dab3da..d762098fc589 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -408,6 +408,32 @@ clocks = <&osc24M>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; From patchwork Wed Oct 18 11:44:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116276 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5967531qgn; Wed, 18 Oct 2017 04:50:20 -0700 (PDT) X-Received: by 10.84.210.105 with SMTP id z96mr15067012plh.325.1508327420351; Wed, 18 Oct 2017 04:50:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327420; cv=none; d=google.com; s=arc-20160816; b=Ddj5v9xkSYtLx/O4EHrAhEFierGZh+5x6MUzMMfaoXXPQ2RhSNf9S1JWXtDgWQ4syN 6JH3VQ/fu/NppQZVdbO/tRHBsYCtb/HhcJfTRWn/kR0tIGJxg7lY6DBFhNU2OtsnP3Bu HjOZFxaF4JTe8ADh5YGJNe7RLanxR97HlXc0Cxc/9T938mj87j2CM8HILVxQZw/H5miY mEgMqmjg8lZvLxP58K4KWacSII9okZ1e/nkOK5HXbQHFPO4KpixSo6gtmF4c69KkfIRQ nEQv1/N6YVwkuZHeLqHUh5qYPAEH76LKpmVc0PTDwwCLHXNv6cbEEdqzDSuzbKNBgcSq zebQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Kn248nSN/JyhPY/5wKhpZm5Zut73sbqjskGrQsQYrEc=; b=f5amDy2bWlpypjfUn2navJd10eS7bcOMAyhONkTb+JzrjgkJVqe8MqgKuLp2XIvLmJ w7OZuGODPo0gpq9iGnusDUaifP+m0g0l084a4YLVU2XdmL4WuOYikYIb985WdR9qYYas P9BMuZa+YkzTSq9xmGnjVlGh6WOSB7AhyrWDPZl0KV33+YhXvf0VJBTcIuhTvYd/vRWw ej7TnV++HXmz9lEi+vB1rof+qEGdetdFps5qeP9qbHmaS/hNXMTYjggc9dizxermpWGD eVXAGtqtWt2m1WK+2WMvmRjgdWfTDGQ1XwldeEDRJxdukP0HiZtuKE4rRyraSSCjPd85 R+Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=QplQIMf3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f5si4282390plj.703.2017.10.18.04.50.20; Wed, 18 Oct 2017 04:50:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=QplQIMf3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755823AbdJRLuS (ORCPT + 27 others); Wed, 18 Oct 2017 07:50:18 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46963 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932294AbdJRLrQ (ORCPT ); Wed, 18 Oct 2017 07:47:16 -0400 Received: by mail-wm0-f68.google.com with SMTP id m72so9517618wmc.1; Wed, 18 Oct 2017 04:47:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kn248nSN/JyhPY/5wKhpZm5Zut73sbqjskGrQsQYrEc=; b=QplQIMf3CErJciePr6bqq6z6gFbFZw8jNXmkb2nt7vsaAzafgHWjHwGi+JlA5LvAA9 5PDgg8ww+Vxdy1Yl8eQD92i3F7JgWHFI4i+SxF1vnFZvIJffV8BB2j5Wt1r9Z37QVfBp fp32JIfLnj03S8UJrnlVepxGbz34vzCLXKk1bkKcahhGTpiCQXQ13hYvo67Fj5Kf/ttb PNbHjoSc+sxRvHO2VDmZwPJF3+N480XFDjnMhLZ0kqWAphnP5hRREal61HJroOvVRfuc 1SqBbA+JAibYw9mFZpvGGKQK/KwQFFNoUeeveCLoFSEVJ8pvPxeq3POdHaIbSfL7JxLk qoPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kn248nSN/JyhPY/5wKhpZm5Zut73sbqjskGrQsQYrEc=; b=AOVNSIKcV5QIOwr4PAIwW9L6p6oEJ3aqLnqcQdPjcnlNpRb967h05FQIJv+oJIk0dA lofij4+Ca6z4oh6TPiUDo4ON2KM+fn50ZCHLSA2FKV/t158i8SrRXjTwaByQnCVkGff4 vYjejuQHZC9y+zStIJYXMT7TJHd9VhSwKM9W7lvGvoNUOAsEcZ/dEJv9ejJQ7ekHbs5m FvBqOCUf2iURgDR/Xy2x8dekZMZ6r5QUma0fve6J7yRTmAedo/jSPovwR5sanEL9SJlR YG2Hs743l3NzPakJCeLtWtGJUBiDKF887V7tATiWFmlHx9i9t25tisaAQoAxT7ndIOk2 tf1A== X-Gm-Message-State: AMCzsaVtjobzSinv+lcn2R6417ZQ5q1jGwd/HQ+dJou7G2eElsc6Lg44 2PZfeqXPrNa96U+z5cEOh4c= X-Google-Smtp-Source: ABhQp+S9n9tQrrdT+uLH6DfJQErIYZowG64aeQhF206bomtSdvAPJhndDyou+NLnTNEEq9JQ6Tevlg== X-Received: by 10.28.55.2 with SMTP id e2mr6517977wma.60.1508327234606; Wed, 18 Oct 2017 04:47:14 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:14 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 03/10] arm64: dts: allwinner: Restore EMAC changes Date: Wed, 18 Oct 2017 13:44:51 +0200 Message-Id: <20171018114458.17891-4-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore arm64 DT about dwmac-sun8i This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ 8 files changed, 135 insertions(+) -- 2.13.6 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index d347f52e27f6..45bdbfb96126 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -51,6 +51,7 @@ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -69,6 +70,14 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -79,6 +88,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index f82ccf332c0f..24f1aac366d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -48,3 +48,18 @@ /* TODO: Camera, touchscreen, etc. */ }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index d06e34b5d192..806442d3e846 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -51,6 +51,7 @@ compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -71,6 +72,15 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&ext_rmii_phy1>; + status = "okay"; + +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -81,6 +91,13 @@ bias-pull-up; }; +&mdio { + ext_rmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17ccc12b58df..0eb2acedf8c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -53,6 +53,7 @@ "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -76,6 +77,21 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 905af406dbd3..0650a1cda107 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -517,6 +517,26 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 1c2387bd5df6..6eb8092d8e57 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,6 +50,7 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -108,6 +109,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 4f77c8470f6c..a0ca925175aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,6 +59,7 @@ }; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -136,6 +137,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 6be06873e5af..b47790650144 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,6 +54,7 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -143,6 +144,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; From patchwork Wed Oct 18 11:44:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116275 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5966968qgn; Wed, 18 Oct 2017 04:49:40 -0700 (PDT) X-Received: by 10.84.133.163 with SMTP id f32mr14003778plf.387.1508327380330; Wed, 18 Oct 2017 04:49:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327380; cv=none; d=google.com; s=arc-20160816; b=gRt+/VMHXH+DR8PaKR9BYoSWRJii618WpSbQOs8iE24cmqNPQNZEYeCCOfBF1mg+1U x9AigbePphaYwX+h0i3XclGvaC0dRm4ddjHk4tT7B1z2QPw4wGKl76xteduAoPKr+PZS DlXBodrEtZL8d0+BMW87d2W9FbzGaE2vC/Pg/ExzwLhNTDGpCy0Cfrz0XycnO1dOll63 DAN3kOpelN5+k18Mn8aibhMz5A1uIG24SsZ+wWe8DxewG/ETgLFG3/j00dN0AU59qAQl zZeULOhR5ptT48wN9eByXE/FPnV8erLinBSIROdSwcVZs4CRmvfrN2i3U+l9FDugz1Y0 Cnrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=E0VPhLeGsS7zd3Hf+jpXoDsn5fDc2YZtoH6gJi+lA30=; b=vd2BihLvgA06U1m05GPLmuhfOh/V6rEdMD7uySztxJbx9OXn4O/9y5DlcuM62fTa31 dUJuIgdOpqJU77yPHqv2s67cihgpbpQTvf/fjPXGKt8ubkYeFyFgXffCDuaSk+/tZzre HeZRc2PVw0F7hRVnSEQqqGOSKEeAzrCMBGm2+2WHMlI0W6s1SxEOxxjXYK/6zZh1FKPm HiEqnDfWwznDvxgD6esyBYHdcZaBMyzlOOPRyBFB4jDaFGL808a/SQ3Q894z3ZsEZ9nu nXD0K/vGacb529/kk09fidnHmEXpix7YOGzHe+v/yBFX9a/AzppMhLgqTrYKa3XhYPnj vDig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=MRJMkZUD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f7si6752733pgq.406.2017.10.18.04.49.40; Wed, 18 Oct 2017 04:49:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=MRJMkZUD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755557AbdJRLti (ORCPT + 27 others); Wed, 18 Oct 2017 07:49:38 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:50545 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754386AbdJRLrR (ORCPT ); Wed, 18 Oct 2017 07:47:17 -0400 Received: by mail-wm0-f67.google.com with SMTP id u138so9489263wmu.5; Wed, 18 Oct 2017 04:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E0VPhLeGsS7zd3Hf+jpXoDsn5fDc2YZtoH6gJi+lA30=; b=MRJMkZUDajg1vhPOc4sqdome3tTuQ8H7Arfoq7Bz2iqk2lXafsbffLqsGqx8TTVSxI CxkNur7cBfarB0ZlyINizONJWauD3y9sNH0KatH6r3cZh8K03+ye4Jk5s8xAvuDoPY0X 6EH1uB1SqDgbG2ZUacq+QEdvtU7lbAzR4DL3y3RFlL3vz4g6n+V8k8wnqhIImBhgXV/Q KUruOsONRYRQFz6bTOxDesm2AcHWU7vwmRdnxmhUhIgqBah1h/3CCLAQrpDJoZKvVD5N eI6qjOUgCVRGAsOl7c6pEYlwY4+9fjQ/wXDNs0FTuac61PkbAuhbbb8yVH0jhEaeqILL 6ijw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E0VPhLeGsS7zd3Hf+jpXoDsn5fDc2YZtoH6gJi+lA30=; b=KkfsJsfnOMRR3vDrToIirzJ7K+qRD+nTH14AxUe9UuhRpmyH2JXXmUEEwRDFY3NuE4 a7RLh5JpR1SfjwarhUkkH53ymAisRqNt1DO4/dYy+UysMxV0jhrHeaTIGp5nJHbPA6L4 xaA4h/9ADkvNtMNunukQq0Zz4XzHo+QO6ifYai96bbULq90ipyHTCmgNRSNKuQX204Vw OZ2orFj1Nu0fgqD+xBqafymAfBgJ/uvH6KbX0hjQcY2mFnFoWpZMPOJEu6ctns6QVsyW DvN9mGdV7f+Mf9m+mqczln7StMm4z2ePdWv5ORyshfyunx0Y35VCnp7nU1+ipSTQ6mzD 5Y1A== X-Gm-Message-State: AMCzsaVNN6U1+U6B0JvctKpjyIzpwQtBcHTwXVV3XsRhNymighin4w63 jCtragY8Z9AYxXjeR9kvfAM= X-Google-Smtp-Source: ABhQp+Q5aJms/ZdmXDmfAgGbyIL1qN6a4QgFXU2EJonqMIWljDk5T8E1YYcHDzSDvPsEmLhDICZJbA== X-Received: by 10.28.22.2 with SMTP id 2mr5943517wmw.47.1508327235827; Wed, 18 Oct 2017 04:47:15 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:15 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 04/10] net: stmmac: sun8i: Restore the compatibles Date: Wed, 18 Oct 2017 13:44:52 +0200 Message-Id: <20171018114458.17891-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore compatibles about dwmac-sun8i This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles") Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.13.6 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 39c2122a4f26..fffd6d5fc907 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } static const struct of_device_id sun8i_dwmac_match[] = { + { .compatible = "allwinner,sun8i-h3-emac", + .data = &emac_variant_h3 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = &emac_variant_v3s }, + { .compatible = "allwinner,sun8i-a83t-emac", + .data = &emac_variant_a83t }, + { .compatible = "allwinner,sun50i-a64-emac", + .data = &emac_variant_a64 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); From patchwork Wed Oct 18 11:44:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116272 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5966127qgn; Wed, 18 Oct 2017 04:48:38 -0700 (PDT) X-Received: by 10.98.10.153 with SMTP id 25mr14326175pfk.60.1508327318783; Wed, 18 Oct 2017 04:48:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327318; cv=none; d=google.com; s=arc-20160816; b=fdTmhxn/OroKMjbuQa2ypEInbIygdgaxCMjfEPb+QNz+Q0qvuPyNFjbxKjufoWDsnw m3kBqpoJDj3ZU+20VuIFa6vOym5HrgK/SrZabjRr7hB657vlD6O+Bx5k7Zg5xZGKWt8L cQec+mcUjj5aum01pOUCc+Z9qPKELihOzHMTIgx/xxHJJTUbGPvvF1dXgFvyKdRuFFTZ 599XOPAqN4enXzUx0maSK50Tx9wLUn2JMJwuQ5behykfckGIiB6F70XjyWYzKvbfYSew rnWMu8WtIsj8mNtb4ixF88dgiOzEkeoTvOBDF1/6W4EQeCJTBldUdRbs9hQvQ0tKbN2K dnJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4359aIbDyeAzMYI4UIa0MNdQ60F1ZYcchUvlj6q41ug=; b=R16a6kb/pZ65JRckDhwjolsvR2XVIXtDoxq0BD8t/jvXBC36TwJn875AhhlGfo2/rR dzQafKdQcrz1sGh5W/6hwhQRowsMDvRu+X1RCuW2mbJDknGCQ212R3aTTMBokBe5ewQ+ b8Y97Jy1OmuBgBjYlxoyYaCn16v4Oej8YKvysEpvMYFD4Hl4DSwFXJYBW90Y6Pp2gelG s6Jk7zGTy/SewJbI4IzghYxtSxK8FDCwiWA/znKtdbi6mjaEqZ3c+13TCoHBMJg29nk2 hN55mwmp/ovD1R4GXuuy1jc3SDAgK67hJYVRF4AXUSeLiR/aOM70jBdTagc+VEbQx/cs t6hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=oRjQJTyr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o15si6896216pgq.475.2017.10.18.04.48.38; Wed, 18 Oct 2017 04:48:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=oRjQJTyr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932549AbdJRLrW (ORCPT + 27 others); Wed, 18 Oct 2017 07:47:22 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:45545 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932406AbdJRLrS (ORCPT ); Wed, 18 Oct 2017 07:47:18 -0400 Received: by mail-wr0-f193.google.com with SMTP id k7so4706861wre.2; Wed, 18 Oct 2017 04:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4359aIbDyeAzMYI4UIa0MNdQ60F1ZYcchUvlj6q41ug=; b=oRjQJTyrBDP/biSLycJmz2Rr1Lau2L5OvrxLfeQ+tuPaPJIbbNZvJ6XBRs7WhwUxWA jGQ1JSF8HPFmPfnHP+A6VlWUKDV9v7Lm50yiBoGNMxmDbD2iwCn2EE55HLVf+LcfWk6T SwakVW424pDR6Ym3VxjoHz3pLmavbJ6EDzHNKVHPCJ5rcwjxFfRGTZb18EqsItmShL3U du1BJQRare0oE42TCNMV6mIoMMUU3ccl6zrhJZP/yi8ZkasqALlMwKYd3/xOuZnGP4kj xyzFgEP++jiC2badhOeMTBBLpc2kW+6KumBlRr+8SemF9035NUvvluPBKn42tzXQljQn UvVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4359aIbDyeAzMYI4UIa0MNdQ60F1ZYcchUvlj6q41ug=; b=WIyL+J5y8Ypyp8FU0nVqjBGdrd+oUc4ljkpxpjZD4SQ1qI7omlgJA5233uyutSkCFH 9Qerrw/thebnOeuwmV0YC0Fa2alf+GQ5t70o1PzMsN9uGEXMES9oJgDMe4G8DXGf75oW wYsuKOGFEYzeCKYUg/QXSzVaqaWT07CYwvq/CEb0xAsARonRqNHIH1NWE+xJfJqsgOtz lpHtCYJi3Znmad5iVyJdPG0jU/38/1gcHE0+sBfMM7uUo71V4vNh3jE93GR41s8Wfc5o 249pG6ZUrTsddF2zLbW1GP3GMtTBnU7mqdPco9T8Ldiwur+NgyQD8AQawerBJLH0j62o EIbA== X-Gm-Message-State: AMCzsaXf10aQcbXl7uqgTHJmnopOjLxhXhhF80WApPlEzimUVzAHTGpt cX61ycfDF/zLSHs7Mx9kZHc= X-Google-Smtp-Source: ABhQp+QXA/7vucDR8+5ncv4Cvey0DCwmpiqwJ7zm+lECmO969utxKlX716BJlufhuxBtaiLjj21hTQ== X-Received: by 10.223.136.246 with SMTP id g51mr6082593wrg.226.1508327236961; Wed, 18 Oct 2017 04:47:16 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:16 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Wed, 18 Oct 2017 13:44:53 +0200 Message-Id: <20171018114458.17891-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 139 +++++++++++++++++++-- 1 file changed, 127 insertions(+), 12 deletions(-) -- 2.13.6 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..0ae7d2096375 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,38 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the mdio node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux" + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +87,113 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; }; From patchwork Wed Oct 18 11:44:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116269 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5965212qgn; Wed, 18 Oct 2017 04:47:27 -0700 (PDT) X-Received: by 10.84.211.79 with SMTP id b73mr14928918pli.214.1508327247299; Wed, 18 Oct 2017 04:47:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327247; cv=none; d=google.com; s=arc-20160816; b=Y5M8/Vwl1n14TzbWYvEm9xu/UjQ1eUQMVnGDHvkwZn4OlaSlTSXkYiDZoalo6iu+pm 4HSBP9C0KyIbZH+hlcQ2tVqS54vBxb/C8AUm1FFxH+B+UCMndkEx/hgv3tRDEwNk7O80 XuP1WuaDmufrOxvZv9aEN2uwl2xrP3nACwGNnQ64hjb1PIMvRaAD+X9rv3cPlh+sBaCC c6J2MfCHk5wQUg72N1vldSC389Wa19uhxWf8YjranmCAIjXEZLBvRzfk02XOY0BQIZoY 3XtJKrSc1KWFdS5L4UscTIlLPRqugO7PQlSDhzYCsRWhyVLQNOs/z4kd8AjAvaB8Vmur 4eYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Lv7RDQhJG4bETTumew24ke21WaCXhBTbZLi5r0SVAak=; b=bx4yb19Q8bee/SGxCMYjsAfLKzKlaNT5zeMSc6J3ayQibIMfjwpZspAzdcBBaaGwaj y1dwjHAdEhLFaR9LX9lq3IE0rMVxcmboNQHwN8OLSfBb4ghtDuCGr5twm6EAgSQAL6ak sjJYj8w028/7TQtxxpVjehDoH/s21gvSIRNoGqo5YDEsylZffWusLXi5rVZqEhnvmq6P 9HBvY7JyyNKVSKwKAocWpCsltssUXentjRObDb8Jz9cNjREEUzL/cNyoboEhErXXT7P4 v80QGoIcbBr9lAyWzQXaCNKC9hK/+FLodDlxQul1q5yl/i91vfbxVeKLVIpW1Mu2Jv0r /0BQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=R9bpmghQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f6si7609860plt.152.2017.10.18.04.47.26; Wed, 18 Oct 2017 04:47:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=R9bpmghQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932683AbdJRLrZ (ORCPT + 27 others); Wed, 18 Oct 2017 07:47:25 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:50173 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754406AbdJRLrT (ORCPT ); Wed, 18 Oct 2017 07:47:19 -0400 Received: by mail-wr0-f196.google.com with SMTP id g90so4700249wrd.6; Wed, 18 Oct 2017 04:47:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lv7RDQhJG4bETTumew24ke21WaCXhBTbZLi5r0SVAak=; b=R9bpmghQXYY+MdE+1kH/RYjmzBOIdz0a2ZpFXul4XiYmD5M6hSxHp5Pb0EgOtYeIg3 oBXP9ZMkbyt4yLgI+QE1MMXLWbhPC/FUDqJkbX/cz+CxkHxRdt3u7kF96oX/7ZyVtBWt sWHkKmPeg82NAgA30FbrfqKB9qS3L+kxI5MiMdUzOz6Bic3+OdI+ERaKCa3gbuMg4Fog qkcw/nUfWgZG/S1igbxFj7oflzK2vq4G+T/fPIXBEN/V2jC26kD37aKxWw9wrm1SWr57 6bd0DzrgYDYwZ6zZ8CnmUlovvHhz0/DWKvSa28ohoUWd87VlKS6DTwq6FuxMOODkoKOs 080A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lv7RDQhJG4bETTumew24ke21WaCXhBTbZLi5r0SVAak=; b=ELfCaJFhPEFKhwu60drXc7ElT4teS9f702n/9ihqyfGLOZdYQahPA16q2hBKEsUsBb QHqV1mGHgDPCbU3YCj7Zvh7nT3kWMk3y4a50xkYTnFlUF+IjJswyxF4r5v8AUFRwdJ3A UH8YTpusgmBuABd5OhSz9OunypoD5KhYBUi7/thIsFPuya61Er+aZ4Ow26dOvsKaeoGX 0GsWWvQWDbxAUcWHxQho8WcsBOwMFjIqvrTMjywGFlUBbbg0cV+R5kF11c8iylrzzTSu zAm5I0/A32w2oOY1Z5BXuyxPFOu9pXSgUO52LhmEnUePHgZX/T/a4KgOObIpcfGYcB1u oudA== X-Gm-Message-State: AMCzsaVhVcngVl1Dc1yO8gu2n9mi2ov1ENyFz+4ZupmRJONKfWitFXgY 3Jff1vt6eydwshKL4dy3D1w= X-Google-Smtp-Source: ABhQp+Sq5IRluZT6wHcRgXPqcc7e3T6YstaGDGcGlzSBaRx1pionM9giftePDOwc9LdXmQx2gCqnHQ== X-Received: by 10.223.188.133 with SMTP id g5mr5882549wrh.204.1508327238122; Wed, 18 Oct 2017 04:47:18 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:17 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 06/10] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac Date: Wed, 18 Oct 2017 13:44:54 +0200 Message-Id: <20171018114458.17891-7-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since dwmac-sun8i could use either an integrated PHY or an external PHY (which could be at same MDIO address), we need to represent this selection by a MDIO switch. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) -- 2.13.6 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d762098fc589..895816f4d741 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -422,14 +422,35 @@ #size-cells = <0>; status = "disabled"; - mdio: mdio { + mdio0: mdio { #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; From patchwork Wed Oct 18 11:44:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116274 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5966708qgn; Wed, 18 Oct 2017 04:49:20 -0700 (PDT) X-Received: by 10.98.57.215 with SMTP id u84mr14438539pfj.300.1508327360578; Wed, 18 Oct 2017 04:49:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327360; cv=none; d=google.com; s=arc-20160816; b=CBuzbd5wwi+SQOTnXX/M8LRYs5bgWc1EfoPxh2EEUqY4ZN0aL/ujvrqv7+nA+eO8Mt 1rykx6UkNpMGnzaeAOtdXQmprX9Wk/RnS+ALDVQH2gDupvy9MQ7fFraeztTIXloz54gB KuXJvVvo5cWD3jXyYPaIIlR1eIDjuwoQmCFwfKDr9VXgrWU2JVqJcG4fSWPyrMQ/qtUG UIcyFvFXpAXfWOYGrDT9rmsTRGNmVye56iB1LY1wbfliGMhSL/QEZgQ99tWpqBNYg75K d0paHaOaFVeuW1BVyVbnvoqePSpgTS28mLhXP0IyBNvEgpixUB/Ll3KKxxHLFrEhZdPC Cn2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kySJbReCgN8XQH+0WQMI45hSZVs8RnyxnuAEb2RgxtY=; b=fICcot5nARe5edp2SRLmb83Fc4C1rxz1ylt6KJ7DOgODX7NOr6jq1EAglBH8h38Ffp il6gSWgJtSBNOx6/t5D8PM8vB0ETlU2uXhisTWsohgwzdiGDUrBCrMrEWUGT1pc3Y21p XZSF3R5RbPXYJ1XuKKLf7wPRK0QL7AEeR2rjszcSG8N7t9voMs/JbxpNE6QyW4vF3knb r5DLC3HSxgPS/3d/PBOJO8jhFEjDsn0UuXEvzbT53fmVTCqajzkXI7ww4ceuNJsJH7ev aDplp1A1YGCx6MWe19WP9lcFNnfSXdrqOxRYBaMG+qkzVrTdFrkMSV02Y3dynGyUQb7R vHsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=EbdBYn7o; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h10si7357131pfa.477.2017.10.18.04.49.20; Wed, 18 Oct 2017 04:49:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=EbdBYn7o; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755453AbdJRLtS (ORCPT + 27 others); Wed, 18 Oct 2017 07:49:18 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:51506 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755117AbdJRLrU (ORCPT ); Wed, 18 Oct 2017 07:47:20 -0400 Received: by mail-wr0-f194.google.com with SMTP id j14so4703557wre.8; Wed, 18 Oct 2017 04:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kySJbReCgN8XQH+0WQMI45hSZVs8RnyxnuAEb2RgxtY=; b=EbdBYn7o771hFVqeWKbIWY9xY/c0ByJfM46sN+E8xvCfwJCCKUW+BWtMBE6F64TqJq Fb6v5z+fXPciqg8vM6ru1kCCy1gf9jtOWN6oAq+hME1i7ywZIrk1khPsXEIl0oeP5fNu bR/kGPTzqCb/BIJO2U/5qh/ZFRxG/v1n+RqOf2gWrY1R34mSI7e54PSNMkf8qkx9z3M/ i7ok5Z2od5+WMG02ZRHo+UBbtBbwkc/AfJPPDb/jmZk3WNeNm2PI9PTmenSWeeCVQMwg LNjyggNomGGzDAeUXl01SAsn74KuORE+UQVyjIreLZwbXkF+7wzEDxUPIRb7LhB5cwmc cpTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kySJbReCgN8XQH+0WQMI45hSZVs8RnyxnuAEb2RgxtY=; b=PClByO4bAuZRm5yeQPPDiXJTu36xiVFP2FdR7Xu99mBFXZD7Mj97IxKQszA7w/KYts pi7aJDzcgEqZEr4VtHhtc3c1jXGnGEDKBcFxtvDDH5Rq9c8s6ZFbd1y3lLPktiV2lPWn J+TbbDzMseKRqoeUJsqHapVMVW70xllqg7FquJpuv0mhKtCLB1Szn0pqSzU7lOih/a/+ wUfHRMrZcGMEPBYsOsAhTfxEfpcKB8HfmvA3QSaL7pVIKpLgqHBXpkoMFo2W/VeE5tk/ 5GXmm6zt5FJYGuhyrCaM67DGDId7lRoRvetOrNNDM5ieka97cQSi5cv/c11rPEIpo56R jzJA== X-Gm-Message-State: AMCzsaVVkjQt01N0mak5T2K6xSp8gmQ4dRCInYq4qlaE2maVvcpRHm4E B9ED5urT3bzVB7QrIqu/3yU= X-Google-Smtp-Source: ABhQp+TdJuCPDsaiBkPIg6CfzJSUSbAEBLSq55yXJBmbhzU7QivQOY7Zq+RtuI2YVm5xIjtAB4YvfQ== X-Received: by 10.223.136.14 with SMTP id d14mr6286775wrd.215.1508327239226; Wed, 18 Oct 2017 04:47:19 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:18 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 07/10] arm64: dts: allwinner: add snps, dwmac-mdio compatible to emac/mdio Date: Wed, 18 Oct 2017 13:44:55 +0200 Message-Id: <20171018114458.17891-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.13.6 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 0650a1cda107..0a2074f86f2c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -532,6 +532,7 @@ #size-cells = <0>; mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; From patchwork Wed Oct 18 11:44:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116273 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5966311qgn; Wed, 18 Oct 2017 04:48:52 -0700 (PDT) X-Received: by 10.98.15.22 with SMTP id x22mr14457627pfi.13.1508327332700; Wed, 18 Oct 2017 04:48:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327332; cv=none; d=google.com; s=arc-20160816; b=VeUWQm0JqGH1HCm5TyFUBVv7rAJrhlC460zbiBa94FYE99GBf/x+tAH6255hQpKrXk 2QONh9ts8lY6+U5MRyG15M6t8pLB31x28p4AbFO07Hh+6Gy1cMHiOsntLouPik0yWAeK hodz6Ezz2i4pFgdixd5SrKbtrdohrfqiEpCutD5c88R5y2oUE9qNzMfOezEzWSI4X20s DWvlAs+CHGQcmZ62l6asv6jxskTeL61obHNNu/U01wun5gHmQBUpKn88jHMvvzbnQd5d fBKA1XjDDAxeXjyxSi4RoptqXgCO3V8RYcOdgU9xUUxOL2VnX69DlAt0PQ4P+4pHb+Wn ut0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=b0Gm3D+IVgaMcITsAdwjjB+YIuRbCDg5sWPrMTvxyFc=; b=O0/jU+VXFC+V78c7qcneCANWyhWd+EpudZB4rMrQcdupyjln0alFgUq2hMducCkyU4 H3e6P8nOKgFK019K8ScyKMYspHvPWZ8C/amyL0aUmOicqz3GHxMZ0f0bAPcD1xVmq3ae GxQRR+a2ENkDL0LI9lbBzIT3OX2Ddg+lQvb7+1benzbjhrDTBlgv2c6MkbCYCUjZJjps K/1GvLxY5HxpNiY0wZsg5deXzLYybDYF+WTGSxh9QKalpmR4uB/kmROclEXkztiPjdyU hw3TMsdFa59lQjFB/tpTPN6gALMn7lITHNfa/gx6RTBeSt2ucLDFXUBdNr5lNiT/9GXg hShw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=UyIvccgZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i9si6799043pgq.152.2017.10.18.04.48.52; Wed, 18 Oct 2017 04:48:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=UyIvccgZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933094AbdJRLsu (ORCPT + 27 others); Wed, 18 Oct 2017 07:48:50 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:43512 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932426AbdJRLrV (ORCPT ); Wed, 18 Oct 2017 07:47:21 -0400 Received: by mail-wm0-f68.google.com with SMTP id m72so12375831wmc.0; Wed, 18 Oct 2017 04:47:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b0Gm3D+IVgaMcITsAdwjjB+YIuRbCDg5sWPrMTvxyFc=; b=UyIvccgZQyXboCSnXcrrD0nz7utpzMmLrHZ+TnAJvtyx6e4WztAPrJzs+LR7AUjsS2 ezUPQswXDEaFhnldFbN2eIlRTxFkcbNG3VORR8Usx8hRSK78xYjMt6Xpaijwbh8DufJO SV1VyNLeCPRdmykM6u6+8jDxFDx0Gk7I0tDvAUC+LYXwdxBvO5bHC3Fsa61Ief58hLjd 8P6NVD6gWXKHaKeTHNbRvPKfxln+asYD5q/6scXsco489SQIHUsF0vaFl+/rfvFAbjOn oKV9lekvZ9FYsYOUZwlT7jreok2SZjt+OuMXmUW+ERPyPuGrgbdr/Sdy+TvkBnSM3Jcb y33w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b0Gm3D+IVgaMcITsAdwjjB+YIuRbCDg5sWPrMTvxyFc=; b=scnowW0q5VgYjDOEqlfISUsId2N13od72ylgPnvRGJi5Syl1JXRI5UsGSzVq6vdmM7 DCPGx1OBkrztVG6Wnk/7guI4r685B0UcPw0jt2cgaUqtH6qyq30npNg8b3IyO1w0kk7V tsjskuEd9RskOOqdKWqNMriXs3EjrelchlyIJ8tBlnOhPS7XjXAX7qJ5fen+qDDP9QOl TOf5muPIrQiuK2KTY2U46pqEQc1Rl0VV4VH6Rjuh+Rv8hpmY1d8mo6nsbMnfF/0Bslv+ ECUsHrFZAeopy+unDW5TAGPSChEeAkSBUuhT3FpKEvh9s2qb4IiYZ0ts3LXEOYVzEXGz +gWQ== X-Gm-Message-State: AMCzsaX+sMCwWYjLfXN5pP8dkhKLMwiLfw6pxKwj7y2QHHy+tQOrTMyP q8XDSp67Kfs+KLd2d/kvKQ8= X-Google-Smtp-Source: ABhQp+Ss9vBnh6q8sL+UXnW/cw+kdHt9uQqIhpWKsGDobaKx4Ut35oz79FX42QXuiK4YLq3Y+O3HUA== X-Received: by 10.28.14.195 with SMTP id 186mr6028674wmo.56.1508327240431; Wed, 18 Oct 2017 04:47:20 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:19 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 08/10] net: stmmac: snps, dwmac-mdio MDIOs are automatically registered Date: Wed, 18 Oct 2017 13:44:56 +0200 Message-Id: <20171018114458.17891-9-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Since these compatible is automatically registered, dwmac-sun8i compatible does not need to be in need_mdio_ids. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.13.6 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 8a280b48e3a9..9e616da0745d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, bool mdio = true; static const struct of_device_id need_mdio_ids[] = { { .compatible = "snps,dwc-qos-ethernet-4.10" }, - { .compatible = "allwinner,sun8i-a83t-emac" }, - { .compatible = "allwinner,sun8i-h3-emac" }, - { .compatible = "allwinner,sun8i-v3s-emac" }, - { .compatible = "allwinner,sun50i-a64-emac" }, {}, }; From patchwork Wed Oct 18 11:44:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116271 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5965847qgn; Wed, 18 Oct 2017 04:48:17 -0700 (PDT) X-Received: by 10.101.78.201 with SMTP id w9mr13415925pgq.402.1508327297645; Wed, 18 Oct 2017 04:48:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327297; cv=none; d=google.com; s=arc-20160816; b=EK7LevSylxB/CsIFWlDx9SU1WIl3rh/QVb4PK5ul7gqLdLtzxbS1kpSA/PbbQSBpFl eabuUUkDMcfWdAlHDaAWaGnGuJzkppPs4DNkK91933P3Ga6fZRzsEhhESBwPaaoXufs4 C/ep3ucawJT1uVdpIY3+35mLBGyQgPkQduj8t8mfOvr6T0kdifpfdaBOd2dXMe/rX/50 wCtZJrvH9LPfsIM4IKFL8r6a/czLViAQxZmff5ssNB3c+MBlfxd0ltjhfKSan0wsjRHP OZwWRY06+8zbDkft49ek9pD6UG/QXvhGgag2u96pxEXheZ8NFxkeL+2N8SINk/7cZcXC lkJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=stc+HFd33E8d2YAUGDZJ2X50zOIqK12tvhrQ7cBqyoc=; b=aQl7d8J+ll8ya9YVNZNtX2WDeRJUkC06xj+Xhg6fCZf/Z/SLdQ4DhWth+Dq3N0/n8G MBr2ahrIjUlZ9RXtvzM1QCITNot0mLkBWHiqDMXkgeIyb7/FE7a1YV5wmEIt9hwe02gQ jqFTYJPbJY6dzqWCOkAnCojv1Yv/1xrDniD8+ErQpMcIyTeWDnzCrTuSGDM33ibker4p LC9V7rigpG8C2XgyKjIegDwSdCbIWEjM+QHXxIwI8VFPNg9QvIHEqz9sbSGWNNu/onpi GLZH9cKT7LG8EbSgzJozcmSevPwTN1GfY3L0+1ITLI4ttLjYRz1T1UqxLoWj5iLyq20B Wtag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=H0wN5Dv+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w6si6851038pgc.681.2017.10.18.04.48.17; Wed, 18 Oct 2017 04:48:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=H0wN5Dv+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755145AbdJRLsP (ORCPT + 27 others); Wed, 18 Oct 2017 07:48:15 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:57320 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932540AbdJRLrX (ORCPT ); Wed, 18 Oct 2017 07:47:23 -0400 Received: by mail-wm0-f65.google.com with SMTP id l68so9645114wmd.5; Wed, 18 Oct 2017 04:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=stc+HFd33E8d2YAUGDZJ2X50zOIqK12tvhrQ7cBqyoc=; b=H0wN5Dv+xognjWy8DEUJPdDYSDilB19Mow8c90cR1e3fUrUi1f9uHkSjjaN37ppTU9 eCeFCOsDaQ901TPbIjo88fkih8Jws4TMtRATfPyhjmmanmBKxpRH9G1Ch1jJkY/Ej2EI bZDOXxOfybqHxaPF5A+SueHo4bOfiKNicVMD1rD9aBnlMDZUUPrk5qvt6dwXGtAB1gT/ 40mKrJYPrGj7BxvgV2kC07p2pb8Ikaj/h4DmGEsHmesc+ep1dRotOiJ2psG6vnS7OeYN 7PZSU8CcDsL2zV2KfWReOSlze0ju4OvjKCiJ7EmzhvODduVL+uEFZVsMGVUajXrFtnhC sWdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=stc+HFd33E8d2YAUGDZJ2X50zOIqK12tvhrQ7cBqyoc=; b=a/ki0Ov8LJpsM6HiCqg7ViMDiJIfd611vsVXz3cgEsAKpnK4E0RfcBG4SXvSFolGak ywoS0X7aYJib0OPcBph7Vsn/qkjt8t0QMVLzzi5GaA0BTm1Eep1efssPZFwMBQIF5DPy /jvuGCHkLaOJ9zSREtvUGs+/xgVeHbh6vFkpHC/hsVBKrN/bby6YhAYwBdAuSeLfWk7F hRURxqjjJckTrtTxNvtXyX/eMxrHrtNI1N16jZJFta6zP7kh0bFc52ey0BpUuONWizUB 9AnqOWxbeNqEWtmP3smwF0aZBAe0VV9MeZOHOz4dHNyjxQBMjkj/4BrVcQOWckL0S/u1 Fn6Q== X-Gm-Message-State: AMCzsaUq8rMRcXgV2tL0zTwo8wne7zoO0P5Ym153WU49mkvH6v3v6BDd YRhe3B/zvr71uxM9vP7sJVE= X-Google-Smtp-Source: ABhQp+RJCFtC+JzeGmQ690YFucCK2aDtxWKSKa31qhsqWQkeTuKwYl0Ggo62R/KlhLxRI1cQaaJglQ== X-Received: by 10.28.158.13 with SMTP id h13mr5709881wme.47.1508327241681; Wed, 18 Oct 2017 04:47:21 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:21 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 09/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Date: Wed, 18 Oct 2017 13:44:57 +0200 Message-Id: <20171018114458.17891-10-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Allwinner H3 SoC have two distinct MDIO bus, only one could be active at the same time. The selection of the active MDIO bus are done via some bits in the EMAC register of the system controller. This patch implement this MDIO switch via a custom MDIO-mux. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++++++++++++++-------- 2 files changed, 224 insertions(+), 130 deletions(-) -- 2.13.6 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 97035766c291..e28c0d2c58e9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -159,6 +159,7 @@ config DWMAC_SUN8I tristate "Allwinner sun8i GMAC support" default ARCH_SUNXI depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX ---help--- Support for Allwinner H3 A83T A64 EMAC ethernet controllers. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index fffd6d5fc907..7741235093b9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -41,14 +42,14 @@ * This value is used for disabling properly EMAC * and used as a good starting value in case of the * boot process(uboot) leave some stuff. - * @internal_phy: Does the MAC embed an internal PHY + * @soc_has_internal_phy: Does the MAC embed an internal PHY * @support_mii: Does the MAC handle MII * @support_rmii: Does the MAC handle RMII * @support_rgmii: Does the MAC handle RGMII */ struct emac_variant { u32 default_syscon_value; - int internal_phy; + bool soc_has_internal_phy; bool support_mii; bool support_rmii; bool support_rgmii; @@ -61,7 +62,8 @@ struct emac_variant { * @rst_ephy: reference to the optional EPHY reset for the internal PHY * @variant: reference to the current board variant * @regmap: regmap for using the syscon - * @use_internal_phy: Does the current PHY choice imply using the internal PHY + * @internal_phy_powered: Does the internal PHY is enabled + * @mux_handle: Internal pointer used by mdio-mux lib */ struct sunxi_priv_data { struct clk *tx_clk; @@ -70,12 +72,13 @@ struct sunxi_priv_data { struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap *regmap; - bool use_internal_phy; + bool internal_phy_powered; + void *mux_handle; }; static const struct emac_variant emac_variant_h3 = { .default_syscon_value = 0x58000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -83,20 +86,20 @@ static const struct emac_variant emac_variant_h3 = { static const struct emac_variant emac_variant_v3s = { .default_syscon_value = 0x38000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true }; static const struct emac_variant emac_variant_a83t = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rgmii = true }; static const struct emac_variant emac_variant_a64 = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -195,6 +198,9 @@ static const struct emac_variant emac_variant_a64 = { #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ +#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) +#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 +#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 /* H3/A64 specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ @@ -634,6 +640,159 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv) return 0; } +/* Search in mdio-mux node for internal PHY node and get its clk/reset */ +static int get_ephy_nodes(struct stmmac_priv *priv) +{ + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + struct device_node *mdio_mux, *iphynode; + struct device_node *mdio_internal; + int ret; + + mdio_mux = of_get_child_by_name(priv->plat->mdio_node, "mdio-mux"); + if (!mdio_mux) { + dev_err(priv->device, "Cannot get mdio-mux node\n"); + return -ENODEV; + } + + mdio_internal = of_find_compatible_node(mdio_mux, NULL, + "allwinner,sun8i-h3-mdio-internal"); + if (!mdio_internal) { + dev_err(priv->device, "Cannot get internal_mdio node\n"); + return -ENODEV; + } + + /* Seek for internal PHY */ + for_each_child_of_node(mdio_internal, iphynode) { + gmac->ephy_clk = of_clk_get(iphynode, 0); + if (IS_ERR(gmac->ephy_clk)) + continue; + gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); + if (IS_ERR(gmac->rst_ephy)) { + ret = PTR_ERR(gmac->rst_ephy); + if (ret == -EPROBE_DEFER) + return ret; + continue; + } + dev_info(priv->device, "Found internal PHY node\n"); + return 0; + } + return -ENODEV; +} + +static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) +{ + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + int ret; + + if (gmac->internal_phy_powered) { + dev_warn(priv->device, "Internal PHY already powered\n"); + return 0; + } + + dev_info(priv->device, "Powering internal PHY\n"); + ret = clk_prepare_enable(gmac->ephy_clk); + if (ret) { + dev_err(priv->device, "Cannot enable internal PHY\n"); + return ret; + } + + /* Make sure the EPHY is properly reseted, as U-Boot may leave + * it at deasserted state, and thus it may fail to reset EMAC. + */ + reset_control_assert(gmac->rst_ephy); + + ret = reset_control_deassert(gmac->rst_ephy); + if (ret) { + dev_err(priv->device, "Cannot deassert internal phy\n"); + clk_disable_unprepare(gmac->ephy_clk); + return ret; + } + + gmac->internal_phy_powered = true; + + return 0; +} + +static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) +{ + if (!gmac->internal_phy_powered) + return 0; + + clk_disable_unprepare(gmac->ephy_clk); + reset_control_assert(gmac->rst_ephy); + gmac->internal_phy_powered = false; + return 0; +} + +/* MDIO multiplexing switch function + * This function is called by the mdio-mux layer when it thinks the mdio bus + * multiplexer needs to switch. + * 'current_child' is the current value of the mux register + * 'desired_child' is the value of the 'reg' property of the target child MDIO + * node. + * The first time this function is called, current_child == -1. + * If current_child == desired_child, then the mux is already set to the + * correct bus. + */ +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, + void *data) +{ + struct stmmac_priv *priv = data; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + u32 reg, val; + int ret = 0; + bool need_power_ephy = false; + + if (current_child ^ desired_child) { + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); + switch (desired_child) { + case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: + dev_info(priv->device, "Switch mux to internal PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; + + need_power_ephy = true; + break; + case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: + dev_info(priv->device, "Switch mux to external PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; + need_power_ephy = false; + break; + default: + dev_err(priv->device, "Invalid child ID %x\n", + desired_child); + return -EINVAL; + } + regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); + if (need_power_ephy) { + ret = sun8i_dwmac_power_internal_phy(priv); + if (ret) + return ret; + } else { + sun8i_dwmac_unpower_internal_phy(gmac); + } + /* After changing syscon value, the MAC need reset or it will + * use the last value (and so the last PHY set). + */ + ret = sun8i_dwmac_reset(priv); + } + return ret; +} + +static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) +{ + int ret; + struct device_node *mdio_mux; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + + mdio_mux = of_get_child_by_name(priv->plat->mdio_node, "mdio-mux"); + if (!mdio_mux) + return -ENODEV; + + ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, + &gmac->mux_handle, priv, priv->mii); + return ret; +} + static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) { struct sunxi_priv_data *gmac = priv->plat->bsp_priv; @@ -648,35 +807,25 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) "Current syscon value is not the default %x (expect %x)\n", val, reg); - if (gmac->variant->internal_phy) { - if (!gmac->use_internal_phy) { - /* switch to external PHY interface */ - reg &= ~H3_EPHY_SELECT; - } else { - reg |= H3_EPHY_SELECT; - reg &= ~H3_EPHY_SHUTDOWN; - dev_dbg(priv->device, "Select internal_phy %x\n", reg); - - if (of_property_read_bool(priv->plat->phy_node, - "allwinner,leds-active-low")) - reg |= H3_EPHY_LED_POL; - else - reg &= ~H3_EPHY_LED_POL; - - /* Force EPHY xtal frequency to 24MHz. */ - reg |= H3_EPHY_CLK_SEL; - - ret = of_mdio_parse_addr(priv->device, - priv->plat->phy_node); - if (ret < 0) { - dev_err(priv->device, "Could not parse MDIO addr\n"); - return ret; - } - /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY - * address. No need to mask it again. - */ - reg |= ret << H3_EPHY_ADDR_SHIFT; + if (gmac->variant->soc_has_internal_phy) { + if (of_property_read_bool(priv->plat->phy_node, + "allwinner,leds-active-low")) + reg |= H3_EPHY_LED_POL; + else + reg &= ~H3_EPHY_LED_POL; + + /* Force EPHY xtal frequency to 24MHz. */ + reg |= H3_EPHY_CLK_SEL; + + ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); + if (ret < 0) { + dev_err(priv->device, "Could not parse MDIO addr\n"); + return ret; } + /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY + * address. No need to mask it again. + */ + reg |= 1 << H3_EPHY_ADDR_SHIFT; } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { @@ -746,81 +895,21 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); } -static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) +static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) { - struct sunxi_priv_data *gmac = priv->plat->bsp_priv; - int ret; - - if (!gmac->use_internal_phy) - return 0; - - ret = clk_prepare_enable(gmac->ephy_clk); - if (ret) { - dev_err(priv->device, "Cannot enable ephy\n"); - return ret; - } - - /* Make sure the EPHY is properly reseted, as U-Boot may leave - * it at deasserted state, and thus it may fail to reset EMAC. - */ - reset_control_assert(gmac->rst_ephy); + struct sunxi_priv_data *gmac = priv; - ret = reset_control_deassert(gmac->rst_ephy); - if (ret) { - dev_err(priv->device, "Cannot deassert ephy\n"); - clk_disable_unprepare(gmac->ephy_clk); - return ret; + if (gmac->variant->soc_has_internal_phy) { + /* sun8i_dwmac_exit could be called with mdiomux uninit */ + if (gmac->mux_handle) + mdio_mux_uninit(gmac->mux_handle); + if (gmac->internal_phy_powered) + sun8i_dwmac_unpower_internal_phy(gmac); } - return 0; -} - -static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) -{ - if (!gmac->use_internal_phy) - return 0; - - clk_disable_unprepare(gmac->ephy_clk); - reset_control_assert(gmac->rst_ephy); - return 0; -} - -/* sun8i_power_phy() - Activate the PHY: - * In case of error, no need to call sun8i_unpower_phy(), - * it will be called anyway by sun8i_dwmac_exit() - */ -static int sun8i_power_phy(struct stmmac_priv *priv) -{ - int ret; - - ret = sun8i_dwmac_power_internal_phy(priv); - if (ret) - return ret; - - ret = sun8i_dwmac_set_syscon(priv); - if (ret) - return ret; - - /* After changing syscon value, the MAC need reset or it will use - * the last value (and so the last PHY set. - */ - ret = sun8i_dwmac_reset(priv); - if (ret) - return ret; - return 0; -} - -static void sun8i_unpower_phy(struct sunxi_priv_data *gmac) -{ sun8i_dwmac_unset_syscon(gmac); - sun8i_dwmac_unpower_internal_phy(gmac); -} - -static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) -{ - struct sunxi_priv_data *gmac = priv; - sun8i_unpower_phy(gmac); + reset_control_put(gmac->rst_ephy); clk_disable_unprepare(gmac->tx_clk); @@ -849,7 +938,7 @@ static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) if (!mac) return NULL; - ret = sun8i_power_phy(priv); + ret = sun8i_dwmac_set_syscon(priv); if (ret) return NULL; @@ -889,6 +978,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; int ret; + struct stmmac_priv *priv; + struct net_device *ndev; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -932,29 +1023,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } plat_dat->interface = of_get_phy_mode(dev->of_node); - if (plat_dat->interface == gmac->variant->internal_phy) { - dev_info(&pdev->dev, "Will use internal PHY\n"); - gmac->use_internal_phy = true; - gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); - if (IS_ERR(gmac->ephy_clk)) { - ret = PTR_ERR(gmac->ephy_clk); - dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret); - return -EINVAL; - } - - gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL); - if (IS_ERR(gmac->rst_ephy)) { - ret = PTR_ERR(gmac->rst_ephy); - if (ret == -EPROBE_DEFER) - return ret; - dev_err(&pdev->dev, "No EPHY reset control found %d\n", - ret); - return -EINVAL; - } - } else { - dev_info(&pdev->dev, "Will use external PHY\n"); - gmac->use_internal_phy = false; - } /* platform data specifying hardware features and callbacks. * hardware features were copied from Allwinner drivers. @@ -973,9 +1041,34 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); + goto dwmac_exit; + + ndev = dev_get_drvdata(&pdev->dev); + priv = netdev_priv(ndev); + /* The mux must be registered after parent MDIO + * so after stmmac_dvr_probe() + */ + if (gmac->variant->soc_has_internal_phy) { + ret = get_ephy_nodes(priv); + if (ret) + return ret; + ret = sun8i_dwmac_register_mdio_mux(priv); + if (ret) { + dev_err(&pdev->dev, "Failed to register mux\n"); + goto dwmac_mux; + } + } else { + ret = sun8i_dwmac_reset(priv); + if (ret) + goto dwmac_exit; + } return ret; +dwmac_mux: + sun8i_dwmac_unset_syscon(gmac); +dwmac_exit: + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); +return ret; } static const struct of_device_id sun8i_dwmac_match[] = { From patchwork Wed Oct 18 11:44:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116270 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5965261qgn; Wed, 18 Oct 2017 04:47:32 -0700 (PDT) X-Received: by 10.98.69.145 with SMTP id n17mr2533034pfi.310.1508327252787; Wed, 18 Oct 2017 04:47:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327252; cv=none; d=google.com; s=arc-20160816; b=oYIjwwmVSlY7IGJZreNOrGtpFqCeTbYvSui9PVwU38PKM/+06cvU+5iNcMxOCvyCGT P4Nb8Ff9WC6l8/9zWyxPpMmwqpkVT0oqMNaZCFTVJHBss7Fw+fydjT/WJgp+bsIu5kKl kNE/r89XH2+JpmRhaWb93Fg2gVO9JrE5jGVVC0mKZLnw1SaE2AIRt0lj3kZOkqlSNu9R tA6u11/snn6oc/Smn80B9oy+0tPzHq7j+imakkEQIker5TtmM4RBsFDZSWgYAO0ZqMzY OmMjPLcFJkQSg1Qzjb8nIpuMKM5UcfFboH10oX8l3wV0VtomW3kxapVNcNdJMAbv3yv3 ESag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tCZB/NGM+w1xoo97gT9wf+T7z4yiIOopH9ZToq6T5Cc=; b=tkPcvt6+NFJNRgJnvlnRLlpTq8kfDREOgC0unZcOkcznt2i0HtNJdkWeQ8kpVAtglv LSG5QWV2NUvPBiN1uL6tCecgRWpFdgiwIfwLP0fdxs4ileJauM9+xC716q1jWGmmtQxP EgiUeRXfe7+Xawbg8swFlrSbHoyFLFEAi6xawHXPum/WJuijLGXchH5oDlJslgiCKmL9 Q/WqzpBEwUeu+YsYSLe3a/wOOvi1EGktjjlyfFcBaRsz5g89W5IhOwUNolk8vBSjOYQO CvWpFS/kVa6xNhbYIU5WLV0Wh2y9hxlH2rNFUnrRRd+vg9dvVun3nSboewjFosH5Hjgb bz8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=PLCs1b3G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f6si7609860plt.152.2017.10.18.04.47.32; Wed, 18 Oct 2017 04:47:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=PLCs1b3G; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932795AbdJRLr3 (ORCPT + 27 others); Wed, 18 Oct 2017 07:47:29 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:50581 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932616AbdJRLrZ (ORCPT ); Wed, 18 Oct 2017 07:47:25 -0400 Received: by mail-wm0-f66.google.com with SMTP id u138so9489946wmu.5; Wed, 18 Oct 2017 04:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tCZB/NGM+w1xoo97gT9wf+T7z4yiIOopH9ZToq6T5Cc=; b=PLCs1b3GKFfbjMJpWP8YihyMtm6unaMF2NYoU/HgMDizJtZUHGCxvpHFgbA7/jw19B BH4vE2jRLq7mwCZbuFaUghE0PVRW0FV3d2eVgRaTs/xoJwOWNb+KkOMrE7PlhCi2WF1s 9AaoshjPDyQwIhPlWY5A2GrOVdC9sR+qH9epNPB00yFYXhqfA0HiOJtEzRNY49ma8rlS Sk2MJbX7CWXD79t+XIcOoYmYg/Wgw0QbyBz1lCXogK2U8cwY4HiMbFY/ad22mzgRXhvr Vhyt279qxfJkSJMeKB/YJqURyPJrJvzsodVj+pp7cp5Qp6+nfzcURKEy5y8S4qPu+0ng EVfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tCZB/NGM+w1xoo97gT9wf+T7z4yiIOopH9ZToq6T5Cc=; b=f9El9Wz51PuNwwnTYCNfXiIkA93TL/3Yle4lQvSdOAnsY3vUTQtlNZ4QeLJe5WKvIQ 3OxK5d/Xuu3f/d4IizeU1LuW8WdgaNjhLvR/w0MYaFWS/DIRzd44g5wGiShuV0v0x8Xs EPONERWgKcSrlFpDqpit9pcd+hHC4kX3j9E/fo5FYoP5VHeWQ166pqneFoluwHRR4fZ8 T1lyxhSXM1fGxtlLGFMr91CfgnmbbNVMMU5ZHzPh+A3ezq9balZ5GIWRbooqc+qULSmx b2ScFul7MG43xgPhtFI9iEmLcqe6u3J4btkIF47vuBbFyj87GXNZzOMzY3/DEixJWh1W WhiA== X-Gm-Message-State: AMCzsaVX9yoxUt15Edw9UA0z3SIY4ynSHagxgUVt5uxPhfHGVY8TH6/u L7G/GFLIALbRO5NmEDz8rv4= X-Google-Smtp-Source: ABhQp+QZYI3FivIz1BVvq5/0fsj3xebgOI1BYao3OwiVGj04GoriXYcVsT9dlPzrazZ6rPrLZ7h4Ug== X-Received: by 10.28.69.210 with SMTP id l79mr6160531wmi.117.1508327242795; Wed, 18 Oct 2017 04:47:22 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:22 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 10/10] of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes Date: Wed, 18 Oct 2017 13:44:58 +0200 Message-Id: <20171018114458.17891-11-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Each child node of an MDIO node is scanned as a PHY when calling of_mdiobus_register() givint the following result: [ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c30000/mdio/mdio-mux has invalid PHY address [ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0 [ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1 [...] [ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30 [ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31 Since mdio-mux nodes are not PHY, this patch a way to to not scan them. Signed-off-by: Corentin Labbe --- drivers/of/of_mdio.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.13.6 diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c index d94dd8b77abd..90f3ac87c98f 100644 --- a/drivers/of/of_mdio.c +++ b/drivers/of/of_mdio.c @@ -190,6 +190,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) struct device_node *child; bool scanphys = false; int addr, rc; + static const struct of_device_id compatible_muxes[] = { + { .compatible = "mdio-mux" }, + {} + }; /* Do not continue if the node is disabled */ if (!of_device_is_available(np)) @@ -212,6 +216,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) /* Loop over the child nodes and register a phy_device for each phy */ for_each_available_child_of_node(np, child) { + if (of_match_node(compatible_muxes, child)) + continue; + addr = of_mdio_parse_addr(&mdio->dev, child); if (addr < 0) { scanphys = true; @@ -229,6 +236,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np) /* auto scan for PHYs with empty reg property */ for_each_available_child_of_node(np, child) { + if (of_match_node(compatible_muxes, child)) + continue; + /* Skip PHYs with reg property set */ if (of_find_property(child, "reg", NULL)) continue;