From patchwork Fri Oct 20 12:44:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 116491 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp114354edb; Fri, 20 Oct 2017 05:51:53 -0700 (PDT) X-Received: by 10.101.88.14 with SMTP id g14mr4493158pgr.198.1508503913820; Fri, 20 Oct 2017 05:51:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508503913; cv=none; d=google.com; s=arc-20160816; b=cl/Oi31Q+6+ekz1zWz54VC7kB1vzElHbb1zkPufC7wtwvNLXgxW5/xxhJ9iVmXhl1F 3CrHJNxU3X353Ha1+5DLT0/FjOeUiNK9UkYw090rLMZr74umDVjX9zFCxXvOLMnYB9tL qVhqfbsp9/lmUjRkOPTCl1rRjED4Su3UmtNIunrjTYfsh8vrmgxR9d+vqi2QaOYt7fiA 03z5tflz2MDdugEgynk0yBjZ5R126ynxAHRnxSiFdtr39L6IavlzovHvMiND1xD6ndgX Q+Jakz3SPjuvEzB1gjCiNSmeTv/dkW1ZTsdf9++/m8WkODa/Rubi5jx9UzmYxdwJ40Ll dfJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=s0h5p9PHfIszM/5cypG5zY0y9wsS+yXxSdxTe+2kNXE=; b=eAdgR12EmR8hPA35RdhnkNBo2GpN9sdo9cIpdDcmJ68u9Umig/DPsoN5WK82FpCYWI UmEp/65l4Qsrod13HgIIixkXYCygId8+dZYpSlVtVXBgbckiZffYqtFKxrHlL5g1WOJf u5xU1d3jWv8CGmkkXjrW4QoAAoYYkY4XR1quAOf6aN4czt/8qJ5gbo9/V/Ug1AubnRJi 0V0QxdiHnpCL8dgrMT+I7hwFniHt6fQKl97xLdGAL8ZUM+kGKPSeHpM/HlUuRsSXygtD Upskcugk7vab0PpQ/FjUeR87UeQK6IKbBPv5RjSYtEvJWrhThVIVlyNfRh+Db+KgkzV2 WGzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jX6OZu/D; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m68si739798pfm.561.2017.10.20.05.51.53; Fri, 20 Oct 2017 05:51:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jX6OZu/D; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751154AbdJTMvw (ORCPT + 6 others); Fri, 20 Oct 2017 08:51:52 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:47223 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751085AbdJTMvw (ORCPT ); Fri, 20 Oct 2017 08:51:52 -0400 Received: by mail-lf0-f65.google.com with SMTP id k40so13089204lfi.4 for ; Fri, 20 Oct 2017 05:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=E7JGw+sGiuBkhfxFd5Lh7SsC/QsanHUc8ZpkvmQf5ds=; b=jX6OZu/DFDPU+aaf8Q5rtIh0vXvt2UgCarUpRIax8KSKLLuoS4VfSfQYSb0dQmG87M k+1mXCgVGKAP3BUk8P/fNFJB0zQxMfF5qEcmP4BlrrHaofuqSd5fXFuAnDFky/XOiVMB wApsNetdZ9gAjfs+cSqVImQHKLmgW9J3HouZM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=E7JGw+sGiuBkhfxFd5Lh7SsC/QsanHUc8ZpkvmQf5ds=; b=kcC2b9A3tjaNJEIKSke+XWSNjlcdz5+IMGlnpkAC7uSz1WV1M8YkKYQcdoedE/R86w j0Lcru50BsyGSyYnVT91ar0xijUTo3I07Qykq6Zrfk7qgo9LofQ7xhejvVcqdCJdvE3c nCnGg5BntKHxGHYNSGvsfXiHZIgELkKt1yRdc5MmdyBiQrm4ypGMKIpxUkr+GmKKauHe L5q+MPEwCqQKnf36F2/5E7cWqqIfNrsCG7YgGJVYqwot5DTBNJRBDJ+6oqvelS6DDU3X p1jxXKexzbF6GaSQYxwmnM7bOPHdf36duSqFOLi8qE4AbGC/sEu69FLWp2sT5ppnpNPM KC/A== X-Gm-Message-State: AMCzsaWojyzH0zkC89sUuBBWHcmhqTPfJA3r35XaHl8IyjLXlWsgzAwO A7lvdJcjdccJTQWvfaIy/Byptr47ihE= X-Google-Smtp-Source: ABhQp+QMifSYW+S9GIYZOwculfGO1BSlsNf3P67PQVPomMnT+m6ycbGLpGLX35pY0R9b3qKcu4wnQg== X-Received: by 10.46.89.10 with SMTP id n10mr2172947ljb.149.1508503569284; Fri, 20 Oct 2017 05:46:09 -0700 (PDT) Received: from localhost.localdomain (c-5f7c71d5.014-348-6c756e10.cust.bredbandsbolaget.se. [213.113.124.95]) by smtp.gmail.com with ESMTPSA id c23sm181812lfh.65.2017.10.20.05.46.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Oct 2017 05:46:08 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Kelvin Cheung Subject: [PATCH] gpio: loongson1: fix bgpio usage Date: Fri, 20 Oct 2017 14:44:05 +0200 Message-Id: <20171020124405.7394-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org When no flags are given, the native endianness is used to access the MMIO registers, and the pin2mask() call can simply be converted to a BIT() call, as per the default pin2mask() implementation in gpio-mmio.c. Cc: Kelvin Cheung Signed-off-by: Linus Walleij --- drivers/gpio/gpio-loongson1.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/gpio-loongson1.c b/drivers/gpio/gpio-loongson1.c index 72b64039241a..fca84ccac35c 100644 --- a/drivers/gpio/gpio-loongson1.c +++ b/drivers/gpio/gpio-loongson1.c @@ -11,6 +11,7 @@ #include #include #include +#include /* Loongson 1 GPIO Register Definitions */ #define GPIO_CFG 0x0 @@ -22,11 +23,10 @@ static void __iomem *gpio_reg_base; static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset) { - unsigned long pinmask = gc->pin2mask(gc, offset); unsigned long flags; spin_lock_irqsave(&gc->bgpio_lock, flags); - __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | pinmask, + __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) | BIT(offset), gpio_reg_base + GPIO_CFG); spin_unlock_irqrestore(&gc->bgpio_lock, flags); @@ -35,11 +35,10 @@ static int ls1x_gpio_request(struct gpio_chip *gc, unsigned int offset) static void ls1x_gpio_free(struct gpio_chip *gc, unsigned int offset) { - unsigned long pinmask = gc->pin2mask(gc, offset); unsigned long flags; spin_lock_irqsave(&gc->bgpio_lock, flags); - __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~pinmask, + __raw_writel(__raw_readl(gpio_reg_base + GPIO_CFG) & ~BIT(offset), gpio_reg_base + GPIO_CFG); spin_unlock_irqrestore(&gc->bgpio_lock, flags); }