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dkim=none (message not signed) header.d=none; intel.com; dmarc=none action=none header.from=amd.com; Received: from BN6PR1201MB2467.namprd12.prod.outlook.com (2603:10b6:404:a7::8) by BN7PR12MB2754.namprd12.prod.outlook.com (2603:10b6:408:2b::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3305.25; Mon, 31 Aug 2020 06:53:32 +0000 Received: from BN6PR1201MB2467.namprd12.prod.outlook.com ([fe80::2160:a344:3b0e:cf3e]) by BN6PR1201MB2467.namprd12.prod.outlook.com ([fe80::2160:a344:3b0e:cf3e%8]) with mapi id 15.20.3326.025; Mon, 31 Aug 2020 06:53:31 +0000 From: Nehal Bakulchandra Shah To: mathias.nyman@intel.com, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Sandeep.Singh@amd.com, yuanmei@lenovo.com Cc: Nehal Bakulchandra Shah Subject: [PATCH] xhci: workaround for S3 issue on AMD SNPS 3.0 xHC Date: Mon, 31 Aug 2020 06:52:46 +0000 Message-Id: <20200831065246.1166470-1-Nehal-bakulchandra.Shah@amd.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: MAXPR0101CA0001.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::11) To BN6PR1201MB2467.namprd12.prod.outlook.com (2603:10b6:404:a7::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 255.255.255.255 (255.255.255.255) by MAXPR0101CA0001.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:c::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.19 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: 8eTul6gWNjpgYLCgHygPgt9pXgJUWyjuVvqRH9B8tEHwQrEPC8orGQ1ExTXu0bQBJhPcLiGTgCQKHdwVa7dgA2xmIPNnIFRZK7pSe9FOpkcVFv9w+GQehTjd70rIRPGKaHLTMt35oSZY/gky1JVg4nOfBnIr3rIg7graF+IjziUgtftQxP89+n6yo2oQB3rvXfzIXOAB+4aq1wY9+gs+yxgpr38mDkPqb0ZNDQ2RNEqXcChE8oy2BGoOhmlrUlsp4tDOIZLoSVZJuXRNn52wLmF/YWl8fjzOy0Rsm996Gp/10rtM2080FYHoJ90TnEMLis85WdvvrfC3f+eoHIT0/WGGJBz5rYLgfB1A4Ands+JN2VZiGO9wx0JjqSLNLQCGmEvz1JWzjjaAjdsoN2dfk4QI4/MgkwuwiXlGibvLZmAzJ8S20OsnDp93uWRBypmvdGIQePkoO3hxsgq3lmwUEg59KnVgY7W1uXPDV7tw3HPzRB1PAgGU/6fdjPCs42M1s8Rp0MIQK80WL9zggObrSzAXqJsUtW4dmzF9Tmvs0+cmfFZgeufNIP3pe/ys1PXAuX1S5GyreKpRiiafX/tR3dKdCO1HPBVKoO63l58/a8lR5ftTGWokSSsAQ3ri7lwdVGv++47WuzEx9ToF+eLouw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1a1de47-4dcd-4926-c831-08d84d7a92a2 X-MS-Exchange-CrossTenant-AuthSource: BN6PR1201MB2467.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2020 06:53:31.6104 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9UUhYsQdJblPG81QQL8fKskbW4pX+EDnPNPSVPlKVNGTrblzR++MzF15BVZ6kGil X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2754 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Nehal Bakulchandra Shah On some platform of AMD, S3 fails with HCE and SRE errors.To fix this, sparse controller enable bit has to be disabled. Signed-off-by: Nehal Bakulchandra Shah --- drivers/usb/host/xhci-pci.c | 12 ++++++++++++ drivers/usb/host/xhci.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 3feaafebfe58..865a16e6c1ed 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -160,6 +160,9 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) (pdev->device == 0x15e0 || pdev->device == 0x15e1)) xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; + if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) + xhci->quirks |= XHCI_DISABLE_SPARSE; + if (pdev->vendor == PCI_VENDOR_ID_AMD) xhci->quirks |= XHCI_TRUST_TX_LENGTH; @@ -371,6 +374,15 @@ static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) /* USB 2.0 roothub is stored in the PCI device now. */ hcd = dev_get_drvdata(&dev->dev); xhci = hcd_to_xhci(hcd); + + if (xhci->quirks & XHCI_DISABLE_SPARSE) { + u32 reg; + + reg = readl(hcd->regs + 0xC12C); + reg &= ~BIT(17); + writel(reg, hcd->regs + 0xC12C); + } + xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev, pci_name(dev), hcd); if (!xhci->shared_hcd) { diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index ea1754f185a2..ea966d70f1ee 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1874,6 +1874,7 @@ struct xhci_hcd { #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36) +#define XHCI_DISABLE_SPARSE BIT_ULL(37) unsigned int num_active_eps; unsigned int limit_active_eps;