From patchwork Mon Feb 20 09:14:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 94189 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1240441qgi; Mon, 20 Feb 2017 01:31:42 -0800 (PST) X-Received: by 10.98.79.150 with SMTP id f22mr24800789pfj.55.1487583102401; Mon, 20 Feb 2017 01:31:42 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a89si18067013pfl.214.2017.02.20.01.31.42; Mon, 20 Feb 2017 01:31:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751068AbdBTJbl (ORCPT + 7 others); Mon, 20 Feb 2017 04:31:41 -0500 Received: from szxga02-in.huawei.com ([45.249.212.188]:2871 "EHLO dggrg02-dlp.huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751133AbdBTJbk (ORCPT ); Mon, 20 Feb 2017 04:31:40 -0500 Received: from 172.30.72.57 (EHLO DGGEMM401-HUB.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AIS29300; Mon, 20 Feb 2017 17:31:11 +0800 (CST) Received: from DGGEML402-HUB.china.huawei.com (10.3.17.38) by DGGEMM401-HUB.china.huawei.com (10.3.20.209) with Microsoft SMTP Server (TLS) id 14.3.301.0; Mon, 20 Feb 2017 17:31:07 +0800 Received: from wind-Tecal-RH2285.huawei.com (10.67.212.71) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Mon, 20 Feb 2017 17:30:59 +0800 From: Jiancheng Xue To: , , CC: , , , , , , , Pan Wen Subject: [PATCH v2 1/2] arm: hisi: add ARCH_MULTI_V5 support Date: Mon, 20 Feb 2017 17:14:50 +0800 Message-ID: <1487582091-24695-2-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487582091-24695-1-git-send-email-xuejiancheng@hisilicon.com> References: <1487582091-24695-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.71] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0201.58AAB760.000A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5592cbc1202ad619393bdc8b27b3a2bd Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Pan Wen Add support for some HiSilicon SoCs which depend on ARCH_MULTI_V5. Signed-off-by: Pan Wen --- This patch is same as the first version. arch/arm/mach-hisi/Kconfig | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index a3b091a..03d8379 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,12 +1,14 @@ config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 + select ARM_VIC if ARCH_MULTI_V5 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI select POWER_SUPPLY + select PINCTRL + select PINCTRL_SINGLE if ARCH_HISI @@ -18,8 +20,6 @@ config ARCH_HI3xxx select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select PINCTRL - select PINCTRL_SINGLE help Support for Hisilicon Hi36xx SoC family @@ -48,8 +48,6 @@ config ARCH_HIX5HD2 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select PINCTRL - select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family endmenu