From patchwork Mon Oct 23 18:56:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116861 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4974885qgn; Mon, 23 Oct 2017 12:02:16 -0700 (PDT) X-Received: by 10.84.248.142 with SMTP id q14mr10935582pll.307.1508785336437; Mon, 23 Oct 2017 12:02:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785336; cv=none; d=google.com; s=arc-20160816; b=cNwtPQNILpkhoR2miJrQK+ZkZpIyqF2Mh2pKF23ByEP4bt6f9nfLAjFA1FgJAfj0F7 0PsMszNyQ5U5P6z3C4iya3zYPTAAIRUHn1ikzB2tg7qi7dYnCDl7mBE6pazACexJPbqq ly/l0SP0/chtLuoWRMA4VwQh9n6ETr8R0mr61DqB68WXov6yI0GFWrdNT4tQp2vUdEFF e3oS/OgWm1/A8pZ/cT+uQZoU52H6inKpSSGRGR2YofhpDlaLvUcpaDCdKqieTvVxRTP9 mBFHw9VURhFcbo2Qqf3sJHbWUTHxWlaju6z+dRsRTB3AbLd1ovM3SmSXLSQYr+ULd5Fk vfyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=196DxAdiAIubhXPg58CYxaK7OcAX+X/0A5rx2xTS8Ns=; b=E8TWl8psQ3bB/Yjs8CHNxOZjLtTggISl+xCBOcS0IkoAZ1HUoSCPMxSmOxS5+RACKq GHbuizFjDQNfRbWNTF2WzvHlYI+Tl6e1fpnTJerl9NTfoQhSBDof49IJ1W5t9uXMjkBM 6xFiK3cfSwrTXBBBcJwRRJ0mjzuXejDFn5bAIaGML1c36ZWeLqRTBxUucd2YLGhZxOaz ybbue+Sct2JdVS+lF2MZ3FAK7OE2yXd6n8gqyn9DVrPJS7ZtlaRyo+g99ua1c6o89tsU 6bmOsbFJ8zvKYXvyQuu8Obmb7aSZbQtt7bOabk9j6mP0YqVA0Q70bhr8RWQzopHGQAXf BDOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=MTA/gcd2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j75si5759332pfj.26.2017.10.23.12.02.16; Mon, 23 Oct 2017 12:02:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=MTA/gcd2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751890AbdJWS6r (ORCPT + 27 others); Mon, 23 Oct 2017 14:58:47 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:56266 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751851AbdJWS6n (ORCPT ); Mon, 23 Oct 2017 14:58:43 -0400 Received: by mail-wm0-f68.google.com with SMTP id u138so11764635wmu.4; Mon, 23 Oct 2017 11:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=196DxAdiAIubhXPg58CYxaK7OcAX+X/0A5rx2xTS8Ns=; b=MTA/gcd2BTyrUM05IdFHkmeK4DRrjacNGK7ui1Yn2W/Mag/KrvLnuh09vsEhVwnkEG xLehVcJcCmWkraRvk6vioRiKh1dqiw2nCHg5jDGq1lgXy3YbMFzhQyW//pEMOL8gYwC7 NvOxXBEwOMRkjISqKmg+UZI0Pz0sKSnpLlxzgMEbd3wS2ly9GQr9IxkoUUNuGDiz/g5P dIhYLh2RckyXHBEy7UQJ3mzy3ytOWNCCr3aKpkg2jq8JeJoI28k4QF3g9CzC29gbiy1t GpkCBIXbx8l92Lym+lsW+5JfdcPjVu8aalDbpYuKHJRI99p0S9HKA06L3/GDgf0BsKGd 9EOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=196DxAdiAIubhXPg58CYxaK7OcAX+X/0A5rx2xTS8Ns=; b=lPVdCYv+xmBlC9Skmne4LQrbv3qvQhw4tGGSUYiRpQHJI1hrxCbmxHObWvuXNraqB9 frRIhgGd7IaUzXGH17MDHlsv0Si7Ea2uJZjRSwq0X7vLQL2RFndCkAYaaSM1D8kEOMD1 55jE+ugHD17moTC7NwlPppYGEVp8n9dsKy2/lVo62d7+CW6vIYrwORqPPgJvVHWPOoA9 oL4WOJeHRVRWvxK0SZo8z9fUhEc+CoNpp94/fsM9KPTlYl6oUgDwAB2wfb/loOoHpMJX nUkBuD8AjyNwxUWghvmWatuFu/bW3dt5W9pMZfeOsR/78PkBidp1oli9XT/KakGugEBJ sV3Q== X-Gm-Message-State: AMCzsaVzhatunmktn9zUsKOKfk6uczgvVYZC4YPr5MuuNbRHTmQCafdQ 9KwVMIDRwEdswojDdsWiexg= X-Google-Smtp-Source: ABhQp+QZxL4Cv8wm1MiZ/6VzDWyzj9k5WVwu/ODdg2cVBDbLktCAH5r4Ph8gnl1o7jIMOFsfuTKopw== X-Received: by 10.28.211.66 with SMTP id k63mr5815216wmg.33.1508785121800; Mon, 23 Oct 2017 11:58:41 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:41 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 01/10] dt-bindings: net: Restore sun8i dwmac binding Date: Mon, 23 Oct 2017 20:56:17 +0200 Message-Id: <20171023185626.31793-2-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore dt-bindings documentation about dwmac-sun8i This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac binding") Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt -- 2.13.6 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt new file mode 100644 index 000000000000..725f3b187886 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -0,0 +1,84 @@ +* Allwinner sun8i GMAC ethernet controller + +This device is a platform glue layer for stmmac. +Please see stmmac.txt for the other unchanged properties. + +Required properties: +- compatible: should be one of the following string: + "allwinner,sun8i-a83t-emac" + "allwinner,sun8i-h3-emac" + "allwinner,sun8i-v3s-emac" + "allwinner,sun50i-a64-emac" +- reg: address and length of the register for the device. +- interrupts: interrupt for the device +- interrupt-names: should be "macirq" +- clocks: A phandle to the reference clock for this device +- clock-names: should be "stmmaceth" +- resets: A phandle to the reset control for this device +- reset-names: should be "stmmaceth" +- phy-mode: See ethernet.txt +- phy-handle: See ethernet.txt +- #address-cells: shall be 1 +- #size-cells: shall be 0 +- syscon: A phandle to the syscon of the SoC with one of the following + compatible string: + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller + - allwinner,sun8i-a83t-system-controller + +Optional properties: +- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0) +- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0) +Both delay properties need to be a multiple of 100. They control the delay for +external PHY. + +Optional properties for the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- allwinner,leds-active-low: EPHY LEDs are active low + +Required child node of emac: +- mdio bus node: should be named mdio + +Required properties of the mdio node: +- #address-cells: shall be 1 +- #size-cells: shall be 0 + +The device node referenced by "phy" or "phy-handle" should be a child node +of the mdio node. See phy.txt for the generic PHY bindings. + +Required properties of the phy node with the following compatibles: + - "allwinner,sun8i-h3-emac", + - "allwinner,sun8i-v3s-emac": +- clocks: a phandle to the reference clock for the EPHY +- resets: a phandle to the reset control for the EPHY + +Example: + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; +}; From patchwork Mon Oct 23 18:56:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116854 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4971016qgn; Mon, 23 Oct 2017 11:58:54 -0700 (PDT) X-Received: by 10.159.194.196 with SMTP id u4mr11071492plz.49.1508785134163; Mon, 23 Oct 2017 11:58:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785134; cv=none; d=google.com; s=arc-20160816; b=lbFi5mC+wvnY+aN9HU/YX1FU8VCHXCdk+VVjFbks5jl0R+OuzfIn9d4tSOav5/LiW7 5r8Kvo/WVupN/NxWPSEHmze6rXLW/R+Dbq4ZMK56GWE+hVUrNyA0iWjK8Q+qQLZSoG5k 3m1xOTUIHAr7CqfJPvQfgmyaE8l+gMOt9xVbQgPUa6awJszk4FtFy5JAzqX/3XlseiOy 9b7HZOZvyLXfiZp7kTdr9YZl7YWNJfH9AEIpz0mnXcsb8urm4NZbfETZeh+wFSzW7P8x J8nD8BZrC+C5hEB3DEe/EC19TLL07TXniQ1QHpGIjv02QH6rXni0nKXbfkpup/ANZn1Q FVsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6LIXNk6ibZItomYu8z67F1aDztDGqA+I7XIzZW7LH1c=; b=j8GEVrWze93QFy0L7dEtpJxLh46LdDvAW7WyRHVzh+JbbJv1XaDmcEqSoD681VZIAx IOwxNX0fYX7u55oY9keGQCDGdjx+sW4RNcB0ofobIqA9QynVeTAPupuGDJYnKceDPz/A VC2DsIux/jc7IkKObefzwGWwTY9Ad+oUYIASDeRb4UdHoiCpkH/SxtgaDoRsyu15esOw R37F1I6rS4T1UDGQdOtObfzMBlQd6dpR6D1KI9hBPOEbRZQkSx6uGJPoOUTM50r2JF1f WEF52Vni7BP3KYe6/M0EBt/7lTbtLpqg0QGRVo7IIB/qfigASO97I2OxfoYPx+GtrK+Z ffWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=jmxngEOT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ay2si1564297plb.434.2017.10.23.11.58.53; Mon, 23 Oct 2017 11:58:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=jmxngEOT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751943AbdJWS6v (ORCPT + 27 others); Mon, 23 Oct 2017 14:58:51 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:45424 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751854AbdJWS6o (ORCPT ); Mon, 23 Oct 2017 14:58:44 -0400 Received: by mail-wm0-f66.google.com with SMTP id q124so11438611wmb.0; Mon, 23 Oct 2017 11:58:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6LIXNk6ibZItomYu8z67F1aDztDGqA+I7XIzZW7LH1c=; b=jmxngEOTCtyue3/wmSbd1hctYksbXzzxRLJ3VjXoGzO68S4+iC0jlH71P8JlnLtudN 40blMdj8L1V1u0PmhlLktXIEIxSqnLFfBwHnd6VHwyc0Lw25y3ineH+TOPQ1B9ubZ+S9 pzFcHzUpLxOGu2M8axcpA2tS6+uDsc+JJb3kyTJgfdApPGJL9zJEAk55h4yZPEBu2afF rY5fJqi69dpuIgGxRGzVBpbIY8R0BvUYlwKSTZxPbI0zrUVPRFE+/cfeLNOoU88pju+x OhuQVV3TySxZKJBmreHBlf98SPw/qeTguhKbuo6IMAUacc4BfseXHKW3BhCCq/cJZQj3 UEkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6LIXNk6ibZItomYu8z67F1aDztDGqA+I7XIzZW7LH1c=; b=Nt+Pngyi9/QnhNrQ9hiizlnCozj/p9NTX9f7U18r2EayCKS68wx//FSnTyjgjVJDby rhVMKwxICtzdiwzOhKYzvJGjARB2EIpOaCDAoIqRJ+mA0CwYbeBwQ67O5bbZO572TsYS vPAYBoBdlB4SfTKnQiRZ15FvVggR2os1vzdAeHM5XCmzBiIe0OCsnQIy7AgyhjqVKbxS KrRtI1BE9l89M7bVyXiuFHJQ3JJZAbjgVFGqLS2RXDGhG/uX3gsYJtm22OwwRixyNm6o 3DZBMca2REabQLBpL2OvxptvGHV350Ew34qxXCTbrREByh7gd3HnhvB/BIhBGbbNeIN4 l2Yw== X-Gm-Message-State: AMCzsaV1JtNhaKmSpC4YYwb6x6SyIrDSk0vGBYL2jrx1qq7X77e6rdqO fP2wCh3Gs7veu+iN8N/192s= X-Google-Smtp-Source: ABhQp+RChafEyZ2wQdPMqPWc9qp91mDAssfsGwZkAG1tgkdZDYLq3G9GWt+K+9Bd7ZJaseG587fktA== X-Received: by 10.28.7.78 with SMTP id 75mr6068092wmh.31.1508785122939; Mon, 23 Oct 2017 11:58:42 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:42 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 02/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Mon, 23 Oct 2017 20:56:18 +0200 Message-Id: <20171023185626.31793-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 139 +++++++++++++++++++-- 1 file changed, 127 insertions(+), 12 deletions(-) -- 2.13.6 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..3e37db10fa02 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,38 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the emac node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux" + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +87,113 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; }; From patchwork Mon Oct 23 18:56:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116863 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4975716qgn; Mon, 23 Oct 2017 12:02:55 -0700 (PDT) X-Received: by 10.98.14.75 with SMTP id w72mr14078900pfi.341.1508785375597; Mon, 23 Oct 2017 12:02:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785375; cv=none; d=google.com; s=arc-20160816; b=e6J3bnSCHCj+S/d74/b4DSQmNGyX7bep125TxMyv2sNdrpBytcyNMgdocysRz1BBN4 KmBEGHHcb1i3S8yor2LgJIdCRsLFi5u7zpBbHZPWa+lS9GyZVJO0RiS+vufHorUG1Fcm bBUsAB5UTR2pX+JEXdWs645orcKZBBsbQqz6Bx/PzTUrE3vsONe8GLs5CxAiLec3VeKW 7K31SKVJ+TGVeXIRgZty35joAwXhUbOMdupCgBkKerIWYn0ml4vI5uFm+ayiirkD+BMK ClgKz3v5mxpEjO7mu2/ypOH8PfFVp42WFGVXiIYziE6aVuY+5QAiRJo5ySYZojDaowjX Wkew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=bZoVHS3dVwiMo0Kx9CpA8ml5rqRdl2WFAzPrr/Qotjg=; b=SHp5jOynEjp6ZUopA9IvCwbejPIWqlYwiif/I1rTRIs5WP6TJ2ANb1jJQPf01Wolot baYDwASQUJy0wr7+LRz7J+fvjKmQIsdcm93m2CG1tB6R9zQ3gTMRUGbNYWoeiSMxk+7v IR3pFkajl4iC2kAHv+jY704nqJpPvVPA0AC9IcNIMkiiUXM2eQqicCQAbZaFroEtRNqT IT+zPaKcrLme04VV6fT59T71A3V7DjgjiF/kEkxX0IOQCN7U4/n2URY7RtbZ1c2CJG+C 09w1nJWtDCUwVTS8mKZ/sgf+GueUQSSSicRQt8KRXIncr333MPCtgaH6biGprovD7Y39 mmDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=IKmyJfa4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n22si4368372plp.580.2017.10.23.12.02.55; Mon, 23 Oct 2017 12:02:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=IKmyJfa4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932373AbdJWTCy (ORCPT + 27 others); Mon, 23 Oct 2017 15:02:54 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46092 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751855AbdJWS6p (ORCPT ); Mon, 23 Oct 2017 14:58:45 -0400 Received: by mail-wm0-f68.google.com with SMTP id m72so11436272wmc.1; Mon, 23 Oct 2017 11:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bZoVHS3dVwiMo0Kx9CpA8ml5rqRdl2WFAzPrr/Qotjg=; b=IKmyJfa4Ci42HgzE058gjD2oJD7p3+g21jGCW3nA4++g3AZ3xBLTdrH+EpZZHaXY3d 2cSJLTIUttEZqMgWJBUECrUMI09JKkz27K3+QKTGgzNXPos/itTzUwRjyjUA7iR7qkbU s2mDPS1vIJJSYDPmN/unbp806/c109heIvPKolspCN1KNEdToZsE3xGW8MJxg6VWDAMQ BTtBBljYxZLHZvWNAhc50jUNxAjbqQDR2too0HSVY6/qhOEkW7yYSv67tvgNuNbyqVFI /sIZa1gMM6LwPv0OrbTVDAUkx+Gd7ZfMA3rqSqt2ep3HoIdyhyzJ+Nm8LXfda1t5HqIi zZYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bZoVHS3dVwiMo0Kx9CpA8ml5rqRdl2WFAzPrr/Qotjg=; b=c8ccoaKdm1ApEXtwcPnZYiQ8FLlZuHL091AfWt9IDzFjonhBmHHgG91ZLted6lBWid cOt1LtVMul2dwk/HmvLNLa7cEkqFFNO2mHi3m842+HCFUVQfpVpk0yOPrd7w9WkIL3uK PcL+T+KXt+TfJZ2BjS+oy1yzTlKmEUMYieTlBUuc0N/bjI3PsY+vfCEXXXhXXloHAwVs mpVS8s/cFaG2tqfvH6r1vgvB2k5qO2G86qLf1jx2V1pqrgAc015Ny5dKdZp53o2sF5Xt 87aAHlgVySsCTEO7TB/bH8PKBVy16josX5KRZhmw9VPOneBUQg/J4VkMLlZ10o52PzCj NYFA== X-Gm-Message-State: AMCzsaXm8FWjhw+TAAKkOtaLEs86XkvF8IGDFUTLrYvNOMr2d0N5QU/E HUH5wSP8iQCjYk8LfBSbY3Q= X-Google-Smtp-Source: ABhQp+QPIL/Cm3yeYKVswGM7l4W+uyONs2a/eOFQC86hwH/lFT/Ie66cWDWFttsMyiFf4/ae8lGKIA== X-Received: by 10.28.8.212 with SMTP id 203mr6001430wmi.43.1508785124020; Mon, 23 Oct 2017 11:58:44 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:43 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 03/10] arm: dts: sunxi: h3/h5: Restore EMAC changes Date: Mon, 23 Oct 2017 20:56:19 +0200 Message-Id: <20171023185626.31793-4-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore sunxi-h3-h5.dtsi This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.13.6 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index c1bd09dab3da..d762098fc589 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -408,6 +408,32 @@ clocks = <&osc24M>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; From patchwork Mon Oct 23 18:56:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116862 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4975120qgn; Mon, 23 Oct 2017 12:02:27 -0700 (PDT) X-Received: by 10.99.109.75 with SMTP id i72mr12590966pgc.268.1508785347480; Mon, 23 Oct 2017 12:02:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785347; cv=none; d=google.com; s=arc-20160816; b=BsQLC6Kdv3klhV+VIigYUoBfo88I1T/AEI6eaDd+7p+ZzV9HBdEbWA6GcAu4IL+3aq GHWoOZAuZBw15aK6TxCnj+AIAnXQwhhhKpee6DYL9mH9/oEkhgcOc/CEEE+mP7VYFQ+C 43H/HigjsnV3UBK+56hMrBHOWmye1QrNcZKz/bSDgv7SStigPCCEXIQ6pXqtgzC5jSLR OhFpRCEvdACiGZayB82D+K6Wg4lnxSPO/ro57PlL9QA5XAynqxeJTxPfRxdpvXmvgNsi LRyuvmMu0J8Y2rKil8uwbuDRpG36FE8rZxsyqIQIcLdw2PTwCFvXs9e2xj7SAAcBRdZ+ ssHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=FsFsbIiqmHBRnLpB+InMslJ3S9ZLQSUWBUH/FfTP94E=; b=hlyTmhwyDiAtrdhXL8rlF+8++r6J0EXmdImfo9wDRFLlyqKF7/fkQcEABgOez3dT3W eJxLSSMMhJtxmQk/O/BOKzy/Qx3S9mWGbLWpi4KYEDep3LCEHq6BLVcuGQc3hS6xGLxD ocs6fCVpgWUflIYzeG0WT/b6k3zbeOBrIMegP4phESp3Lb6vJ0UmxGOoFkke/qHophQJ kG0xFjgo0rObf6U2zduiWsSaswHvVsIXLBdUdgCOtu2plYfctCVSlv9mABWRYxW9CMVB rBsPdF0LEXBg4+EC4levR4culY/ryWpmbcYkdo6uhCYxdwi0mQAV7++MP1nBHz0O6g6t lzRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=cV12/qCJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n22si4368372plp.580.2017.10.23.12.02.27; Mon, 23 Oct 2017 12:02:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=cV12/qCJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932336AbdJWTCX (ORCPT + 27 others); Mon, 23 Oct 2017 15:02:23 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:46096 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751857AbdJWS6q (ORCPT ); Mon, 23 Oct 2017 14:58:46 -0400 Received: by mail-wm0-f67.google.com with SMTP id m72so11436376wmc.1; Mon, 23 Oct 2017 11:58:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FsFsbIiqmHBRnLpB+InMslJ3S9ZLQSUWBUH/FfTP94E=; b=cV12/qCJ8HqgRvaa3drlNoNJhLkH9yxnMl+wOyzT5cImtCzEmkOpnZKU/MzZAh5Ll7 9H1/ozoUGNeYjGvB5NgeW75raI3gVg3+G5jz7tMcTiKhqCJX2MmhO5jNTfDZvO8KrcK8 ewYfegUztYKy9m420/Ck5/5qa/BblNlrxtu/LNokWBJfMZEuNaQMrZCtpYLqZwnpkrfL ZAv6okc7o4pmx6QUuypDbmCjrR2TxCpRQA4qURMzpiIFYNXuciNvxVMb2ZKGyLN7jwZv QF3/zEUUn7IMMlB1HQaaS/ULLDAbamc5yPyjSx6dELmUdavrKcHBgCvzNqFfRvcBTvGo 0Mcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FsFsbIiqmHBRnLpB+InMslJ3S9ZLQSUWBUH/FfTP94E=; b=JSSj1Old3Q0qDoLAnipTnQFFHjOni26ZyAhE5oWPd9VivPoeQt6eIjw/PpyMhUuIPm g5X+2kehULPyADbLteIFpxRdFmx1bqx2YPtuToKFsVlzc4ANGz3hznJ47BNW/n+EUq2v JOrq1ScEDl2Sb0xM1lAkwp7SCI3PpywjZhbySdnfJd96yAegTVj4nB27BPTPbkiUu2LQ M+IQtQiv3N+FuAOgGnXYO70Am+ulLj7GLN6eSBpfNIxmClIRMJPVE+OKQf9n0iohYTon NlYxa4ju5hEodRhDfRUUYSp470TnUX/dzH4m3ziIGGrtuew5hS1/MLi0PMXt6Ba4yHl0 l/gQ== X-Gm-Message-State: AMCzsaWX6Cf0Guqt+yc3u+puQj8kfw7pQ56xODEsvzvP2r9DEEHUS7mc aQh9aO3zsrExocJ/u52XESY= X-Google-Smtp-Source: ABhQp+QoQGb0g0UNgCe/fQzSeLiMQ1eXnKS3gGtUli2Lr/BgrAFxXe12Vrq51b+GHN/MuP82bxjLkg== X-Received: by 10.28.231.25 with SMTP id e25mr4606502wmh.157.1508785125134; Mon, 23 Oct 2017 11:58:45 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:44 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 04/10] arm: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac Date: Mon, 23 Oct 2017 20:56:20 +0200 Message-Id: <20171023185626.31793-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since dwmac-sun8i could use either an integrated PHY or an external PHY (which could be at same MDIO address), we need to represent this selection by a MDIO switch. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) -- 2.13.6 diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d762098fc589..aa60b7fd18f2 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -422,14 +422,35 @@ #size-cells = <0>; status = "disabled"; - mdio: mdio { + mdio0: mdio { #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; }; }; }; From patchwork Mon Oct 23 18:56:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116860 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4974453qgn; Mon, 23 Oct 2017 12:01:57 -0700 (PDT) X-Received: by 10.99.123.83 with SMTP id k19mr12376028pgn.338.1508785317122; Mon, 23 Oct 2017 12:01:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785317; cv=none; d=google.com; s=arc-20160816; b=WVcart7cEZgmmx6WU8YmThnIboy2MgbS9trQXhhm3b3RJ3Tbltp2MJmN0dDQV58Dr3 W67VeSB+HZaghz1TCRlWnbZPt1CzSWcgr929HkYCcNcXFRPlN7wIZX6i40NHi2PzYk60 frgzIoxSn0RWZGh6hbzJh+YV1WKeE4MJ7It+LWhtgFHTWJg5SjkNg8vJ9b4DebyaQGpT J+WDEMJQ1uTRy6qIG8RWYAjVlgXutd07rVdjlTpvorGoKK2MKlhH5jtoNSdiIUdeGy2T GvbSvku6K/oRpwCfHryjVaffaYSFLpp6vxUyv+cXbW50jPvyCEGClEAhwBWrDhhEcUk8 5UuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=9IB/uMwtdnfnx9QK4kyt7l9p9uWyVB82vrumDZUIISw=; b=v2wQrRr8r7lHqA4Yr9jJGJuP2zkZPkTi0BbclKm+mwCzzZaZRjxfKh3R5ivuEKEIpy 7YPCBRLCeXO+1kgxBtRsSWDlYrOKrLdJkkCXHZySnXZ50SvD7Hx+PehMd9SkWuaEU3rM IzUwPXcQ/6HWaGVbUtHOvTLhJqcDsq3m3n9BCuJvXmQrJ8x/YQcZ7Dmu/yzrsdjHTHF8 eloqe2fR2DuTgZIY29FgVBWLv0Wo72NCApO+ZmVLADHSE3VwfYzBA+Wi2dkX8W7NsWuZ 068YgRWGwzH8P5sN3bku41jG0GSgBG+VNwtrmfrf6zZN1Ol8GY0Rg0UAquytWAMpyOLC dshw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=nGVk8FqJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k126si5739743pfc.348.2017.10.23.12.01.56; Mon, 23 Oct 2017 12:01:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=nGVk8FqJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932195AbdJWTBz (ORCPT + 27 others); Mon, 23 Oct 2017 15:01:55 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:47467 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751889AbdJWS6s (ORCPT ); Mon, 23 Oct 2017 14:58:48 -0400 Received: by mail-wr0-f193.google.com with SMTP id y39so18429910wrd.4; Mon, 23 Oct 2017 11:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9IB/uMwtdnfnx9QK4kyt7l9p9uWyVB82vrumDZUIISw=; b=nGVk8FqJpkb/nqGVx0hYY4dRrtKrgiax1V8Xhcv8XRtLpD1HfvWvpnvmcai0zJ0xbR LhnhG7iKAIjjqaf6Sge6mGdZ5ns8p5nwgzKuLVSnqnoEMH41YBa8gG0CYtgdJITnN5pB zF2YpTIYTa/Ri4AVq+0IzTrMh5dOcm8yqz5Ee/7Tnd8V82KRFl3/3KHeoyEPwfYT0uVD UhXy8YYKd8C0Pe6KoanhT3NsjyJKW2ZGum17Cb0UML2/sEEcAOIB1hyxEGYP3QtXfaIN EK6eY103I4edoHFX6B6ZUumaQikIkA9ShQlHUD2oqksOQJ/QZZKAeRsZq7ZrNCdhixt3 iILQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9IB/uMwtdnfnx9QK4kyt7l9p9uWyVB82vrumDZUIISw=; b=lBN1JtMxz0RHOyCV7gXpU4pMACRWcevRbuoFgpyDNgn0K/7pdIyGg3GIVyPl7Mm5uF kASAYZSxs13mSwZ0dxQUZiXBWaVaEu+6pkET2RBAyX+eDyg7xDRrkFQVxjkCpmgNnh3o /vmH+fj6ntU9IBqdgXfY0tBPflx9scq74Xd2HPG51WuCPjlR/hUygVuT3xRciotUy8j5 4p9MKOw6GmtWurIuMRCe+4QIHCc/+GN/rc5P7O127Vxqb3xC16WRFLnsK0Pf6pIabV1L 4H4PulymjYOwAy/VgOse5+0dlKAcdWSj+IXN/4fooCd4bFshNGidxsgWSkKnHv3H6FC+ OAtA== X-Gm-Message-State: AMCzsaWgozPkPMnscg9x8HwdRAJgagjvu+CZQB21H2+mBa2DRBy90Wip ph6qAe47t9Hnhvn5pVjevdM= X-Google-Smtp-Source: ABhQp+RWgu8/UZvQ/vqhyJ5llPkLE6DAjJRB6hOPtjVE9JBl4Ewob0fwveIG+UI/vxzNf+9W5jhCkw== X-Received: by 10.223.165.67 with SMTP id j3mr11461272wrb.271.1508785126423; Mon, 23 Oct 2017 11:58:46 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:45 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 05/10] arm: dts: sunxi: Restore EMAC changes (boards) Date: Mon, 23 Oct 2017 20:56:21 +0200 Message-Id: <20171023185626.31793-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore all boards DT about dwmac-sun8i This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++++ arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19 +++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 +++++++ arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 ++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 ++++++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++++++++++++++++ 10 files changed, 121 insertions(+) -- 2.13.6 diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts index b1502df7b509..6713d0f2b3f4 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts @@ -56,6 +56,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &xr819; }; @@ -102,6 +104,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index e1dba9ffa94b..f2292deaa590 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -52,6 +52,7 @@ compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -111,6 +112,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts index 73766d38ee6c..cfb96da3cfef 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -66,6 +66,25 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 8d2cc6e9a03f..78f6c24952dd 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -46,3 +46,10 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 1bf51802f5aa..b20be95b49d5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index a1c6ff6fd05d..82e5d28cd698 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -97,6 +98,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 8b93f5c781a7..a10281b455f5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,6 +53,11 @@ }; }; +&emac { + /* LEDs changed to active high on the plus */ + /delete-property/ allwinner,leds-active-low; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index d0b80fda2f6b..6d98bcfbe877 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -52,6 +52,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -117,6 +118,13 @@ status = "okay"; }; +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 72ca01b93f1b..cbc499b04de4 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,10 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + reg_gmac_3v3: gmac-3v3 { compatible = "regulator-fixed"; regulator-name = "gmac-3v3"; @@ -74,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 97920b12a944..6dbf7b2e0c13 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -61,3 +61,19 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; From patchwork Mon Oct 23 18:56:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116859 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4973476qgn; Mon, 23 Oct 2017 12:01:09 -0700 (PDT) X-Received: by 10.159.254.13 with SMTP id r13mr10682045pls.267.1508785269054; Mon, 23 Oct 2017 12:01:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785269; cv=none; d=google.com; s=arc-20160816; b=Nl39ykf3FY7+6Eskwxo9x5uqZME47ysO876eAhRywnZ/SkX0wPBomm324/2/sSjXzq 9ywlJuE1UEBRiGh4mhd/G6+xxtyDjp6WfnR2LCzSgPqIwgHnM7ydnZURNWdwSc4iXRTf eosLK2egFgtd7N8pg95qokNdA6xpyDuv0YjRn8NYmOcAGlWJNrAOrywUbLN/375g1rp4 z8mcCG6Af+ti6kawFIXrMwP5ZT93ohHCMiuoCg2tNxIfLNpBzba9D/q4rpydBnBzY4xw 1Vffd58ZzMKJKt25whbHh7NJ9vVceDoyfESa5h4nv/B6tUECwqPIgAFzZ+4ageGBEIzg ejVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Kn248nSN/JyhPY/5wKhpZm5Zut73sbqjskGrQsQYrEc=; b=Ep/yo8io9dpVWgyq2MccLvJ0XpDKsYsXtLMdxt7iwZz9Ypguhp8HSU+eOsMoAkbpSJ 7zJOR3Kcqtc+zn7GoRPcPhcUcb5FUVUEYbVU3GCot7jeyz6o3U8n3gVL1wamWxvQrMe2 +sXL245cqJxA0ya5jVwXCVoWQUvww6ycLN91Zi+me2enN9sVIWtQnVbUBF9KcOcEsl5Y 91MIC1C0Y9YT3bpor/fiGOxu+7yyoOZDG/nGlzGvRZ7nhh5wH+bNjcmqNDH/LCiAN39V FLt8PKLuf0hAKBDcrNNWV+J5Qz4ZH59LIb/avY34siojE1TLepmSpOgsrjJ6zxxU7ayr YzxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=mKgKNL5k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f16si5249332pgt.658.2017.10.23.12.01.08; Mon, 23 Oct 2017 12:01:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=mKgKNL5k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751905AbdJWTBH (ORCPT + 27 others); Mon, 23 Oct 2017 15:01:07 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:44844 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751674AbdJWS6t (ORCPT ); Mon, 23 Oct 2017 14:58:49 -0400 Received: by mail-wr0-f193.google.com with SMTP id z55so12351944wrz.1; Mon, 23 Oct 2017 11:58:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kn248nSN/JyhPY/5wKhpZm5Zut73sbqjskGrQsQYrEc=; b=mKgKNL5kW3BNLywSycYdmCdpX25tXHKc841djQKS38A/y7PuxchBEU3hxkYMoaX6GS FDUSJl2CsgCX9LngX3l3Lsy5M+M7Ckk/ITqSC9TrpNma4RfUZmnMp+WpFSN0FLKSGzHV mOd4UFpPV61DAz5dpXEiOlDLNtJMcOh2gLhNRvG2wTV6hUrnLy6jgUFKFtXNBWc9Ciri IrQxGPemzUSG0l6J9nmq8hQpzJmC82aZEkr/76qCrqljaI7MUUgAnnqi08BGyA65S8ja LvUtNV9SmU8LaCc56MCXAdS2tNKeLqyRFNwfFRo+LzisHu6Cpys4Uti39bxjOmC63egB R8CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kn248nSN/JyhPY/5wKhpZm5Zut73sbqjskGrQsQYrEc=; b=J2jM7v7x0u2ICzZgObIYlhsgVgNz4IYniNPOz2Q8Vpygxu2emYiipyslIUdizLsNRE rY4nde0UI2Dq6dzPtcT9iNZEmd6sbqFQ7n6hksYAZ8+GIwnbWFqF/hMGQZ7RLhpC7fIx btuirIoBnjEbNHlgZDRd878Y3wwJpMYnRGt42NR+duQYjOcETGvHru/1hrkCJAkMXBNn y6JIj8MN9qkpB8CMZ+L6OheGoYcW62kb8GPpdJOSjki4hG9kzUQTjR/VjvRy16VrlkA9 Pb7tDiQ6e4NjMj0+rbrPl+GgdP8N0U4Aa/UZLDmDKP+LA7nnmB2PxgYRJE7ertNugzHx ZPsQ== X-Gm-Message-State: AMCzsaWRqi8qKjTirY5NoXVzL81ILxkFpy2ENvgJLG6dpESQlycsMQBi 2WLIfcAbvXZ9qTeeyfOB47A= X-Google-Smtp-Source: ABhQp+TDGr5UEjFCREyLHmGLMTBK5iXn4Hf76gKwKEOA4q2zifR5ya0eYq2n7LaZwtS0T8P4odXJ+g== X-Received: by 10.223.143.51 with SMTP id p48mr4873982wrb.104.1508785127556; Mon, 23 Oct 2017 11:58:47 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:47 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 06/10] arm64: dts: allwinner: Restore EMAC changes Date: Mon, 23 Oct 2017 20:56:22 +0200 Message-Id: <20171023185626.31793-7-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore arm64 DT about dwmac-sun8i This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes") Signed-off-by: Corentin Labbe --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++++++++++++++++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 +++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +++++++++++++++++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 ++++++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 +++++++++++++++++ .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +++++++++++++++++ 8 files changed, 135 insertions(+) -- 2.13.6 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index d347f52e27f6..45bdbfb96126 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -51,6 +51,7 @@ compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -69,6 +70,14 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -79,6 +88,13 @@ bias-pull-up; }; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index f82ccf332c0f..24f1aac366d6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -48,3 +48,18 @@ /* TODO: Camera, touchscreen, etc. */ }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index d06e34b5d192..806442d3e846 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -51,6 +51,7 @@ compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -71,6 +72,15 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + phy-handle = <&ext_rmii_phy1>; + status = "okay"; + +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -81,6 +91,13 @@ bias-pull-up; }; +&mdio { + ext_rmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 17ccc12b58df..0eb2acedf8c3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -53,6 +53,7 @@ "allwinner,sun50i-a64"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -76,6 +77,21 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 905af406dbd3..0650a1cda107 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -517,6 +517,26 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun50i-a64-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 1c2387bd5df6..6eb8092d8e57 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -50,6 +50,7 @@ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -108,6 +109,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 4f77c8470f6c..a0ca925175aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -59,6 +59,7 @@ }; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -136,6 +137,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 6be06873e5af..b47790650144 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -54,6 +54,7 @@ compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -143,6 +144,22 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; From patchwork Mon Oct 23 18:56:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116858 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4972865qgn; Mon, 23 Oct 2017 12:00:42 -0700 (PDT) X-Received: by 10.99.115.28 with SMTP id o28mr6831336pgc.340.1508785242850; Mon, 23 Oct 2017 12:00:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785242; cv=none; d=google.com; s=arc-20160816; b=yCjOzBI2XsBFXzWZadqPR82r8GZlbWyhPAhANxXKuCr4GZToAsh/W0LsRIy8aEVpFX nvwz0X6Jm2EVCXR7bLt4TNCvxIiPA2iUAto0PcJSacMKWj5FaIuyDJLDF+oNZGicDeWH SUBn3b+Yi5RKBmNqOc2SyrJSppT5i1wACjVnVVUwRr/03hTtoqbBSqswBENh3AW1ykQs LflKfjSbXkjMJdLRGh3ieN2fRX0C7iOn6x/DT1+pUyN6YuaQmJLMJYBb+D0KsNE71nfj gzc7D/mO3MOc+GXeATth1Tzvkoe/9dvGgoR3z9iZQzZEJdPa45x4vHSpmWPXVmSRKAgS bv1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kySJbReCgN8XQH+0WQMI45hSZVs8RnyxnuAEb2RgxtY=; b=Lyq2kvYXm5CpxHooRz9XxTn7+ZD6xJPDEx8qkdQapAx/hlhj/nxYcmnIStd9+neiED 4nb8v+5hoJKsMHL+6dYqW4OxVLLYLX8gmxditpjP72eZpI89ampFFXuvoh6baDWPEQ42 ob1K9LppYUyge3fIdnxtSGxMzyYtl5frRrJRoPMVnYuYuOsxNeK40n7ZLRgc9JFIT2Qt 3szhQ4bpZWj1w4PhvrY0b8I2JjWSjVUy9epmD+QVljU3Q0Eml/lgQPecwHcDwK4ImTLp 3H+HEEvXC+UeMPomjZxtbj8vocL0rNNjzpkwqOYqDeweDzMwPTFpr0I7/TWjcJhJv0RN AJsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=OKivF++2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i2si5263388pgp.4.2017.10.23.12.00.42; Mon, 23 Oct 2017 12:00:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=OKivF++2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752061AbdJWTAl (ORCPT + 27 others); Mon, 23 Oct 2017 15:00:41 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:55936 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751905AbdJWS6u (ORCPT ); Mon, 23 Oct 2017 14:58:50 -0400 Received: by mail-wr0-f196.google.com with SMTP id l8so5550489wre.12; Mon, 23 Oct 2017 11:58:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kySJbReCgN8XQH+0WQMI45hSZVs8RnyxnuAEb2RgxtY=; b=OKivF++2+hay+OewVmSJwt1t9QU7BJ8zyDBjQZfR+1sc9KhJWSvLpEXv8VNH/XvAzI TbHHlagnwhgpnoUMtikgvIPKj9i8SJjQ4afiZkKMDLZ6Ou8Eyhc/GW0FiUaKQZlDzggP /VVF/sCUNtiJO0IH9hrpQqh5S7pJZYHBxHELarbVB8kQBbPW01lvj4VBppcRc86Ft80t plXFopcEdO8pVq29OZp9GLv0/xSUDaTvQT23KXLwZ2Mxn1t5Wncvy6VDbHTaWDukeGY5 990y+b23F7sWNgfstN0OqMh4/GySClnsjZuvjmzg/MXtEhddmcBpc0tcJ2cxElK6uVtb iUzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kySJbReCgN8XQH+0WQMI45hSZVs8RnyxnuAEb2RgxtY=; b=M/Ok/EjtjcGBH0q+8A3aTM5voslR7oM7qUBPHawY7pjmer+w5VmlaFORgqTwdK7lYh eMZlp5Ole4WhLA96/sm2RuODwMYOPl8HnhCXn+poT+GTCEOgHVHZ91KhUXVreTItrnPC rt8IhG3esDk8sAI3Iiz6P8vfURVciJrwDpeWL5968IPq9JSOvZkfpE/B0B9yyzK74sTT Oold5Fw7QdFLhmZSGWdM5l+Qq4fgAshdbdGl9ptVFHRYdloAR46O6+Wn8bzLoyP5uiPF eL7yzMLNts3ZUQo0aAZudEVTe0a7jNDMu7wv/ttzcAQTHGme6J4l14nNu22t8cKeOrzM WFTA== X-Gm-Message-State: AMCzsaWea578dOplq1qUlJprrWMgfUcD1N1uyyNBIdavOQrKNkAON/9v iXrp0OZE6L25ov1FOz0Dy6g= X-Google-Smtp-Source: ABhQp+QmUFtBa8FNIg16RfpBJ0YwcVZ9bm2+fXSuZXyKkR0Qvs6JicFUQyqs1ivQ69hyqlG6w/0UNg== X-Received: by 10.223.163.143 with SMTP id l15mr1018454wrb.149.1508785128640; Mon, 23 Oct 2017 11:58:48 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:48 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 07/10] arm64: dts: allwinner: add snps, dwmac-mdio compatible to emac/mdio Date: Mon, 23 Oct 2017 20:56:23 +0200 Message-Id: <20171023185626.31793-8-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.13.6 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 0650a1cda107..0a2074f86f2c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -532,6 +532,7 @@ #size-cells = <0>; mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; From patchwork Mon Oct 23 18:56:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116856 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4971950qgn; Mon, 23 Oct 2017 11:59:55 -0700 (PDT) X-Received: by 10.98.74.23 with SMTP id x23mr14096058pfa.205.1508785195260; Mon, 23 Oct 2017 11:59:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785195; cv=none; d=google.com; s=arc-20160816; b=tPd4DiB5PCwBUzXl+4XoHW9005ThIYcKrmv3HVrXffMLPmfDTRXJnhuhlPSWkxDYWN afkfPxbqh3esdwI7rWIaqagyroWZb2FWncfMKC9339Bw6jrGgOJfEQGPrE7lMjR7WboY XE/mCUNzPvHzizR6Xx/1PTmsNx/KBchqz/vUDqlMzKRtKyOr1zo57g25Wv3yWMZjvtdM kZYjT+w8C0DkRwMPBChaTZkH44+5XESavX7mN8Hsfr9ByAMD7kQN3RFsb2RjJcC+Vzev K8/a5M4RvFurpE+wRDBijHDlm7FJBGXEhUkUhJA8H/0omlwwU5zjHyMeG4nUJGHQ+77g Jwmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SD96LGCJ92R9np+MmDHeox2iRyFDSnokyqvldaaOX8M=; b=fZ2oWtoiUHgYOZTdF8Nqo0GSYTCRIIsocr9ABdh8OakQFHygVLvdPCvunjZnO51qny g/jiK/NKu02LOLR+pvcewAzoyzKfS70lSK0R6iss7uTeVn2lMms5RneqLqNWXptdocQJ 5+qswlb9oOYFupW9TRVxzG5TtKfpPuaY2Ki9cNjXhSVOJwF7Hakl7Y8Sv8nW/GUhH4Gn 9gsU1JLyj+Cl9iZMqGd3f/jUDZmcmioFKXMrIkA+Skj8zt5gtY6keTSA6FaQk3mFcXDF ncAbuH8E8dJ5KcuAase5X7lno/puBYyx7TLQYwwhF85vZtK2xz8zkySNZgR0BqmJo673 pCRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=AA908h1K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e4si5253763pgn.134.2017.10.23.11.59.54; Mon, 23 Oct 2017 11:59:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=AA908h1K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751965AbdJWS64 (ORCPT + 27 others); Mon, 23 Oct 2017 14:58:56 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:50798 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751942AbdJWS6w (ORCPT ); Mon, 23 Oct 2017 14:58:52 -0400 Received: by mail-wm0-f68.google.com with SMTP id u138so11407681wmu.5; Mon, 23 Oct 2017 11:58:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SD96LGCJ92R9np+MmDHeox2iRyFDSnokyqvldaaOX8M=; b=AA908h1KxRJho46o1U0RG8/qfIJyDDJdcq0/c2wTpGVfmtDDt/S1NkJ/enYgELtgCQ G3fxJlVFqM4u9ZZVPWsiIjlXC8JcrpVL17k6aS1fHwSwlFIvBN9qlkSDc/UHiYaip6Tc Tymxf1Ia85UYZQalOjjVd0fyc+6wQvhHEWTLe6+ARNcKHOAWtBlAhxM0wHsjvpE6LJ3A Rzzewq3KRv3Wbf/Sn7YRmSdg5l8FoxXpvejFmS9CQv/kXU1kTYHzy1QnaWC9JrI/5RdU GwakqPJYm8qdhMXPINa6xnLbtR7oGwG3lkV3XGvNls7o7ofiOF0equIXHRslgd4xZgED p7vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SD96LGCJ92R9np+MmDHeox2iRyFDSnokyqvldaaOX8M=; b=Nxg115T5nGEMemgeDzW8C+xUO7PokstcA2h4NlwSG558VAYiYy3VB5wnvB1yhTvigs /te8r8UXmvFdnyHM1/gS6U+V4iGgStrFyj/Rr9wuh2Cca9eSfyZjTpcCSbVzP5zp+JnX Qwk75+KElcF5Gmv4WMb/at4pXXPkspp7tYRn/Nit3O2mUL1hmpaXg/12wP07q3k0oI73 KT3YbaAR//HlsElIb00xdaTaNIUoguJZWsZLT5rcGG0jqQYiBgyKBIdcyMADeLUui/I4 oct3i9l/OsZZrZ+2R+AMV6/RvXNn5tIzSPHs53A/2qX8uUeFs+KdZjbNzYXr/V9XEbyK puFg== X-Gm-Message-State: AMCzsaU/EcPhW6ulh4m++2iHJElz8Om5Ih+6Cisap0bJ7FOFMwx9qyKk nozghzx6xF5RrBGw6xr/Hbs= X-Google-Smtp-Source: ABhQp+T2VYTrQKZ6AKjWScwcm1iXQTSlEg9B1AI6HmAoDbipy4/QuLabKcZCCXBOv1Pp8u9X3B2gGg== X-Received: by 10.28.207.130 with SMTP id f124mr6964927wmg.88.1508785131062; Mon, 23 Oct 2017 11:58:51 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:50 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 09/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Date: Mon, 23 Oct 2017 20:56:25 +0200 Message-Id: <20171023185626.31793-10-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Allwinner H3 SoC have two distinct MDIO bus, only one could be active at the same time. The selection of the active MDIO bus are done via some bits in the EMAC register of the system controller. This patch implement this MDIO switch via a custom MDIO-mux. Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++++++++++++++-------- 2 files changed, 224 insertions(+), 130 deletions(-) -- 2.13.6 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 97035766c291..e28c0d2c58e9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -159,6 +159,7 @@ config DWMAC_SUN8I tristate "Allwinner sun8i GMAC support" default ARCH_SUNXI depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX ---help--- Support for Allwinner H3 A83T A64 EMAC ethernet controllers. diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index 39c2122a4f26..b3eb344bb158 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -41,14 +42,14 @@ * This value is used for disabling properly EMAC * and used as a good starting value in case of the * boot process(uboot) leave some stuff. - * @internal_phy: Does the MAC embed an internal PHY + * @soc_has_internal_phy: Does the MAC embed an internal PHY * @support_mii: Does the MAC handle MII * @support_rmii: Does the MAC handle RMII * @support_rgmii: Does the MAC handle RGMII */ struct emac_variant { u32 default_syscon_value; - int internal_phy; + bool soc_has_internal_phy; bool support_mii; bool support_rmii; bool support_rgmii; @@ -61,7 +62,8 @@ struct emac_variant { * @rst_ephy: reference to the optional EPHY reset for the internal PHY * @variant: reference to the current board variant * @regmap: regmap for using the syscon - * @use_internal_phy: Does the current PHY choice imply using the internal PHY + * @internal_phy_powered: Does the internal PHY is enabled + * @mux_handle: Internal pointer used by mdio-mux lib */ struct sunxi_priv_data { struct clk *tx_clk; @@ -70,12 +72,13 @@ struct sunxi_priv_data { struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap *regmap; - bool use_internal_phy; + bool internal_phy_powered; + void *mux_handle; }; static const struct emac_variant emac_variant_h3 = { .default_syscon_value = 0x58000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -83,20 +86,20 @@ static const struct emac_variant emac_variant_h3 = { static const struct emac_variant emac_variant_v3s = { .default_syscon_value = 0x38000, - .internal_phy = PHY_INTERFACE_MODE_MII, + .soc_has_internal_phy = true, .support_mii = true }; static const struct emac_variant emac_variant_a83t = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rgmii = true }; static const struct emac_variant emac_variant_a64 = { .default_syscon_value = 0, - .internal_phy = 0, + .soc_has_internal_phy = false, .support_mii = true, .support_rmii = true, .support_rgmii = true @@ -195,6 +198,9 @@ static const struct emac_variant emac_variant_a64 = { #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ +#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT) +#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1 +#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2 /* H3/A64 specific bits */ #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ @@ -634,6 +640,159 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv) return 0; } +/* Search in mdio-mux node for internal PHY node and get its clk/reset */ +static int get_ephy_nodes(struct stmmac_priv *priv) +{ + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + struct device_node *mdio_mux, *iphynode; + struct device_node *mdio_internal; + int ret; + + mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); + if (!mdio_mux) { + dev_err(priv->device, "Cannot get mdio-mux node\n"); + return -ENODEV; + } + + mdio_internal = of_find_compatible_node(mdio_mux, NULL, + "allwinner,sun8i-h3-mdio-internal"); + if (!mdio_internal) { + dev_err(priv->device, "Cannot get internal_mdio node\n"); + return -ENODEV; + } + + /* Seek for internal PHY */ + for_each_child_of_node(mdio_internal, iphynode) { + gmac->ephy_clk = of_clk_get(iphynode, 0); + if (IS_ERR(gmac->ephy_clk)) + continue; + gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); + if (IS_ERR(gmac->rst_ephy)) { + ret = PTR_ERR(gmac->rst_ephy); + if (ret == -EPROBE_DEFER) + return ret; + continue; + } + dev_info(priv->device, "Found internal PHY node\n"); + return 0; + } + return -ENODEV; +} + +static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) +{ + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + int ret; + + if (gmac->internal_phy_powered) { + dev_warn(priv->device, "Internal PHY already powered\n"); + return 0; + } + + dev_info(priv->device, "Powering internal PHY\n"); + ret = clk_prepare_enable(gmac->ephy_clk); + if (ret) { + dev_err(priv->device, "Cannot enable internal PHY\n"); + return ret; + } + + /* Make sure the EPHY is properly reseted, as U-Boot may leave + * it at deasserted state, and thus it may fail to reset EMAC. + */ + reset_control_assert(gmac->rst_ephy); + + ret = reset_control_deassert(gmac->rst_ephy); + if (ret) { + dev_err(priv->device, "Cannot deassert internal phy\n"); + clk_disable_unprepare(gmac->ephy_clk); + return ret; + } + + gmac->internal_phy_powered = true; + + return 0; +} + +static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) +{ + if (!gmac->internal_phy_powered) + return 0; + + clk_disable_unprepare(gmac->ephy_clk); + reset_control_assert(gmac->rst_ephy); + gmac->internal_phy_powered = false; + return 0; +} + +/* MDIO multiplexing switch function + * This function is called by the mdio-mux layer when it thinks the mdio bus + * multiplexer needs to switch. + * 'current_child' is the current value of the mux register + * 'desired_child' is the value of the 'reg' property of the target child MDIO + * node. + * The first time this function is called, current_child == -1. + * If current_child == desired_child, then the mux is already set to the + * correct bus. + */ +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, + void *data) +{ + struct stmmac_priv *priv = data; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + u32 reg, val; + int ret = 0; + bool need_power_ephy = false; + + if (current_child ^ desired_child) { + regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®); + switch (desired_child) { + case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID: + dev_info(priv->device, "Switch mux to internal PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; + + need_power_ephy = true; + break; + case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID: + dev_info(priv->device, "Switch mux to external PHY"); + val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; + need_power_ephy = false; + break; + default: + dev_err(priv->device, "Invalid child ID %x\n", + desired_child); + return -EINVAL; + } + regmap_write(gmac->regmap, SYSCON_EMAC_REG, val); + if (need_power_ephy) { + ret = sun8i_dwmac_power_internal_phy(priv); + if (ret) + return ret; + } else { + sun8i_dwmac_unpower_internal_phy(gmac); + } + /* After changing syscon value, the MAC need reset or it will + * use the last value (and so the last PHY set). + */ + ret = sun8i_dwmac_reset(priv); + } + return ret; +} + +static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) +{ + int ret; + struct device_node *mdio_mux; + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + + mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); + if (!mdio_mux) + return -ENODEV; + + ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, + &gmac->mux_handle, priv, priv->mii); + return ret; +} + static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) { struct sunxi_priv_data *gmac = priv->plat->bsp_priv; @@ -648,35 +807,25 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) "Current syscon value is not the default %x (expect %x)\n", val, reg); - if (gmac->variant->internal_phy) { - if (!gmac->use_internal_phy) { - /* switch to external PHY interface */ - reg &= ~H3_EPHY_SELECT; - } else { - reg |= H3_EPHY_SELECT; - reg &= ~H3_EPHY_SHUTDOWN; - dev_dbg(priv->device, "Select internal_phy %x\n", reg); - - if (of_property_read_bool(priv->plat->phy_node, - "allwinner,leds-active-low")) - reg |= H3_EPHY_LED_POL; - else - reg &= ~H3_EPHY_LED_POL; - - /* Force EPHY xtal frequency to 24MHz. */ - reg |= H3_EPHY_CLK_SEL; - - ret = of_mdio_parse_addr(priv->device, - priv->plat->phy_node); - if (ret < 0) { - dev_err(priv->device, "Could not parse MDIO addr\n"); - return ret; - } - /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY - * address. No need to mask it again. - */ - reg |= ret << H3_EPHY_ADDR_SHIFT; + if (gmac->variant->soc_has_internal_phy) { + if (of_property_read_bool(priv->plat->phy_node, + "allwinner,leds-active-low")) + reg |= H3_EPHY_LED_POL; + else + reg &= ~H3_EPHY_LED_POL; + + /* Force EPHY xtal frequency to 24MHz. */ + reg |= H3_EPHY_CLK_SEL; + + ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node); + if (ret < 0) { + dev_err(priv->device, "Could not parse MDIO addr\n"); + return ret; } + /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY + * address. No need to mask it again. + */ + reg |= 1 << H3_EPHY_ADDR_SHIFT; } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { @@ -746,81 +895,21 @@ static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); } -static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) +static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) { - struct sunxi_priv_data *gmac = priv->plat->bsp_priv; - int ret; - - if (!gmac->use_internal_phy) - return 0; - - ret = clk_prepare_enable(gmac->ephy_clk); - if (ret) { - dev_err(priv->device, "Cannot enable ephy\n"); - return ret; - } - - /* Make sure the EPHY is properly reseted, as U-Boot may leave - * it at deasserted state, and thus it may fail to reset EMAC. - */ - reset_control_assert(gmac->rst_ephy); + struct sunxi_priv_data *gmac = priv; - ret = reset_control_deassert(gmac->rst_ephy); - if (ret) { - dev_err(priv->device, "Cannot deassert ephy\n"); - clk_disable_unprepare(gmac->ephy_clk); - return ret; + if (gmac->variant->soc_has_internal_phy) { + /* sun8i_dwmac_exit could be called with mdiomux uninit */ + if (gmac->mux_handle) + mdio_mux_uninit(gmac->mux_handle); + if (gmac->internal_phy_powered) + sun8i_dwmac_unpower_internal_phy(gmac); } - return 0; -} - -static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) -{ - if (!gmac->use_internal_phy) - return 0; - - clk_disable_unprepare(gmac->ephy_clk); - reset_control_assert(gmac->rst_ephy); - return 0; -} - -/* sun8i_power_phy() - Activate the PHY: - * In case of error, no need to call sun8i_unpower_phy(), - * it will be called anyway by sun8i_dwmac_exit() - */ -static int sun8i_power_phy(struct stmmac_priv *priv) -{ - int ret; - - ret = sun8i_dwmac_power_internal_phy(priv); - if (ret) - return ret; - - ret = sun8i_dwmac_set_syscon(priv); - if (ret) - return ret; - - /* After changing syscon value, the MAC need reset or it will use - * the last value (and so the last PHY set. - */ - ret = sun8i_dwmac_reset(priv); - if (ret) - return ret; - return 0; -} - -static void sun8i_unpower_phy(struct sunxi_priv_data *gmac) -{ sun8i_dwmac_unset_syscon(gmac); - sun8i_dwmac_unpower_internal_phy(gmac); -} - -static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) -{ - struct sunxi_priv_data *gmac = priv; - sun8i_unpower_phy(gmac); + reset_control_put(gmac->rst_ephy); clk_disable_unprepare(gmac->tx_clk); @@ -849,7 +938,7 @@ static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) if (!mac) return NULL; - ret = sun8i_power_phy(priv); + ret = sun8i_dwmac_set_syscon(priv); if (ret) return NULL; @@ -889,6 +978,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; int ret; + struct stmmac_priv *priv; + struct net_device *ndev; ret = stmmac_get_platform_resources(pdev, &stmmac_res); if (ret) @@ -932,29 +1023,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) } plat_dat->interface = of_get_phy_mode(dev->of_node); - if (plat_dat->interface == gmac->variant->internal_phy) { - dev_info(&pdev->dev, "Will use internal PHY\n"); - gmac->use_internal_phy = true; - gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); - if (IS_ERR(gmac->ephy_clk)) { - ret = PTR_ERR(gmac->ephy_clk); - dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret); - return -EINVAL; - } - - gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL); - if (IS_ERR(gmac->rst_ephy)) { - ret = PTR_ERR(gmac->rst_ephy); - if (ret == -EPROBE_DEFER) - return ret; - dev_err(&pdev->dev, "No EPHY reset control found %d\n", - ret); - return -EINVAL; - } - } else { - dev_info(&pdev->dev, "Will use external PHY\n"); - gmac->use_internal_phy = false; - } /* platform data specifying hardware features and callbacks. * hardware features were copied from Allwinner drivers. @@ -973,9 +1041,34 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) - sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); + goto dwmac_exit; + + ndev = dev_get_drvdata(&pdev->dev); + priv = netdev_priv(ndev); + /* The mux must be registered after parent MDIO + * so after stmmac_dvr_probe() + */ + if (gmac->variant->soc_has_internal_phy) { + ret = get_ephy_nodes(priv); + if (ret) + goto dwmac_exit; + ret = sun8i_dwmac_register_mdio_mux(priv); + if (ret) { + dev_err(&pdev->dev, "Failed to register mux\n"); + goto dwmac_mux; + } + } else { + ret = sun8i_dwmac_reset(priv); + if (ret) + goto dwmac_exit; + } return ret; +dwmac_mux: + sun8i_dwmac_unset_syscon(gmac); +dwmac_exit: + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); +return ret; } static const struct of_device_id sun8i_dwmac_match[] = { From patchwork Mon Oct 23 18:56:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116855 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4971124qgn; Mon, 23 Oct 2017 11:59:00 -0700 (PDT) X-Received: by 10.98.61.147 with SMTP id x19mr13957853pfj.258.1508785140178; Mon, 23 Oct 2017 11:59:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785140; cv=none; d=google.com; s=arc-20160816; b=t8tcPhn4jMmGT2ZxjbVIiRFcfXrfadqMV4iU3hdI76n2dJ/o52mbZDFI3yAq7ulg5M mFYSHJGFDwVYqLrQUDOXzqcl8YkEfR88vXk4MsXwBHIem2f5hMwuS4b/JRtLIhvfzZo6 rsGS5ZbA6jGHzG27syk3bSbAV/PmRM32yTYr7wP4RR5FfzxDkvXoBOAo+lzYBEfXjgoN c/x9po12l+vqAgRvHOJ/fMsN9QCNnjfjjG2IU+HYR75O4TFA+6w+BI5UQL04gWLAlmDf gyyjiK9tXif/lxouprA2xBojTIk+VrCqx7NHpvVRFdlRD3Do0KSLAUb2VgQkqlkCXIRv lffA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=g4DwBW21baoi+fHJrNBIJ4zYUowYA79ljQDUeIXUjW4=; b=KzrR8QUNaZjBBxVrT+WTD/dV8XQHJyApnhZC8X8oVhpXeaohCASIBnd6Ew0U6D6neP ZR8Yt5wc72s6XisCfr01+OL3FDMTa8BSJ05S6Gjx1Wz7FLm+FcD5Gxz6qu4gN43hhkH6 KhY5JJ8x208ed3P8/afXfWo/zUHBEQLYIW3oYBYyXRhY5rF8kPzomo6bueDRivxoGF3z Y5fzjjLI/9qESYzYfo9PO9AukrG85jvFqqxRNeTnJccrLA8VeDDU5I6XAAvYGq7/dPx7 HRj4eQuElu/lUAUQBvJfGeKUSEXB9bf/PVkfaNXcwvnAibb0aglqwFPHLmGtFkFvYiOh JzkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=rFi9iNq7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ay2si1564297plb.434.2017.10.23.11.58.59; Mon, 23 Oct 2017 11:59:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=rFi9iNq7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751995AbdJWS67 (ORCPT + 27 others); Mon, 23 Oct 2017 14:58:59 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:47477 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751854AbdJWS6x (ORCPT ); Mon, 23 Oct 2017 14:58:53 -0400 Received: by mail-wr0-f194.google.com with SMTP id y39so18430134wrd.4; Mon, 23 Oct 2017 11:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g4DwBW21baoi+fHJrNBIJ4zYUowYA79ljQDUeIXUjW4=; b=rFi9iNq7THXuAdBka++A+yFbgI1oc0Crw045LhvO5mE91wC/4BeYpm7/dO8r5XcC9x Uo6cJ5gvYz/13UGP1xs5zcy9HJTpmg3hVeUFlt5hH8T5vAYRx0amw/6btlXuqsapiEjl 52bbhfLtZ1pR0QpLb6ideQ4lm3HT48lUISNLC3l8aKeFNJYDYb3c2de+LDZJKFaKFFP7 j5t+igORGctTFS4qEB1Pjxfa15nGWDA12+TKAKUe15a4CelCSNGChjSec7A4+EW2c+3+ ij/GktWkpkeZyQTb8JvqBqq15p8fi9kSgeGhlr/PYI5cXSzBjmWKq9yzWMQ8BuwsLD1q jkfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g4DwBW21baoi+fHJrNBIJ4zYUowYA79ljQDUeIXUjW4=; b=jVJs56xTcS63E/fBvd/75mRCfJ3rxS0dmqvwaSAeFGRmua93dkgL9o3APUJ7eRbe1X oBA/vR0GlXffjpHWNgjrJweSj9H1yFl3aogI+7nKreF/gdVEMKD1UOpztdsvzf8oVy0C TOnlBd517PxgO/ZuwknGiUlVQXclKlF9nkcgBYbJ/VvV2wZ4vIUpRRohuf/Kk+f8NrM9 KrIcBLQm+rayG8/R3xTLhAZQlsM87ux0A7BDd4i4/tkeD4YU8S5NXhC6ZAEw9R8SySbT bAiK7j8owTr79W3Z288XDWcu7g4DYL23HSC8ivSxhYmLlsFQWAtEjE4BB8sgWr1lZuq1 TWSA== X-Gm-Message-State: AMCzsaXVLZYqPiJ8euTgUM/BLo2+Ez0cl7XXWAQv/O8RL+HpwT5unaPp 779zTzRTTabv7dnINg9D1t0= X-Google-Smtp-Source: ABhQp+SDLLgWrghQ3i9rJk7ro+mrUBdEkR9SeXk8FLJDuKTtX/j4kASfIK4j6WtizkjnBiBx3Yx+yw== X-Received: by 10.223.160.161 with SMTP id m30mr6491881wrm.27.1508785132183; Mon, 23 Oct 2017 11:58:52 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:51 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 10/10] net: stmmac: sun8i: Restore the compatibles Date: Mon, 23 Oct 2017 20:56:26 +0200 Message-Id: <20171023185626.31793-11-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore compatibles about dwmac-sun8i This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles") Signed-off-by: Corentin Labbe --- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.13.6 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index b3eb344bb158..e5ff734d4f9b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -1072,6 +1072,14 @@ return ret; } static const struct of_device_id sun8i_dwmac_match[] = { + { .compatible = "allwinner,sun8i-h3-emac", + .data = &emac_variant_h3 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = &emac_variant_v3s }, + { .compatible = "allwinner,sun8i-a83t-emac", + .data = &emac_variant_a83t }, + { .compatible = "allwinner,sun50i-a64-emac", + .data = &emac_variant_a64 }, { } }; MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);