From patchwork Tue Oct 24 15:51:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116964 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5915365qgn; Tue, 24 Oct 2017 08:07:49 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TkkF1+DMZtislO8YhoAFIaJuw0Ajmr8DuJYmZc7rsNQBXLPxcl3pubo5n5GW44X+uxTAOB X-Received: by 10.99.123.4 with SMTP id w4mr14734057pgc.438.1508857668986; Tue, 24 Oct 2017 08:07:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857668; cv=none; d=google.com; s=arc-20160816; b=PkzG/w/fEr4L8O5ivoznLsiMP/n1+u8RNvOo4gZ6hrzZ7gmEm3HL/z1FGXNpud9W4n 0ID2Z7aCAUMDObgbc/0K/9yuqyNGBTFrlmEuWUp2CvfhJ67P/fJWiaoONq3LrXHnQtx2 /CsjDbLUw2VbqoXlSoQnfIZYFft61umgvOn7uBT9NXA2VHE1xv1N9Hb4EAHTBWSgunkF Ei53SBm5rMGoZW7X4Tv0+y1Y8W6GSJ0tiasGg5hIocBP0eSARCnCZWZqBGy1lQ4Q41CP QKZX8TjTfgvef1CSYkJkSGNeo+1QY4HDkyP0BgeQ69tB6x6PDWHqnDQQRd1MkYyWN2qG 4eDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=jagK6dR0rjsLkXzVVhYQZsa40ZHcIpFt6QN2Fxq85ks=; b=si8qfOamQJSk1YaHNanFf94BB1Ze251jtyiTGYrmXowqwAmYT7vGwNkQwzN4SQSPKX P7/RWIh/GRQEEye2mJWokgq/hSP93lo7LZ6NaWURe2LOwUEioBH+0ueGtJkBT2MceF7C GohCsIMsxjQ1fwbzS+ug10zHf3PEM80z1OU5eHBFRlX+si9pAy64m6GY5kGkRPZBZutx 5D4kYEIvhmQlCzVw/8WBQEKZKNXH0Wu/m6BmBMCn1XhPXBcDn+PPaDoG7neTuK586Uuh FvVFKDTW2v0IfrecZz2GecBjqvTTEMLqCF7FON7s1188NrQzY56dZMScebzTTPa1ljDt cjOw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w66si345225pfj.218.2017.10.24.08.07.48; Tue, 24 Oct 2017 08:07:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751943AbdJXPHr (ORCPT + 1 other); Tue, 24 Oct 2017 11:07:47 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50534 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751412AbdJXPF2 (ORCPT ); Tue, 24 Oct 2017 11:05:28 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 1ED1742E195B5; Tue, 24 Oct 2017 23:05:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:16 +0800 From: John Garry To: , CC: , , , , Xiang Chen , John Garry Subject: [PATCH 05/19] scsi: hisi_sas: fix SATA breakpoint memory size Date: Tue, 24 Oct 2017 23:51:35 +0800 Message-ID: <1508860309-212397-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen Currently the size of memory we allocate for SATA breakpoint buffer is incorrect. The breakpoint memory size should be as follows: 32 (NCQ tags) * 128 * 2048 (max #devs) = 8MB Currently we only allocate 0.5MB, but get away with it as we never have SATA device index > 128 typically. To conserve precious DMA memory (8MB may not be even available), limit the number of devices per HBA to 1024, which means 4MB of memory required for SATA breakpoint. The 1024 device limit applied to all HW versions. For v3 hw, we need to configure this value. Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 8 ++++++-- drivers/scsi/hisi_sas/hisi_sas_main.c | 6 +++--- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 +- 3 files changed, 10 insertions(+), 6 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 07f4a4c..07538cf 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -29,7 +29,7 @@ #define HISI_SAS_MAX_PHYS 9 #define HISI_SAS_MAX_QUEUES 32 #define HISI_SAS_QUEUE_SLOTS 512 -#define HISI_SAS_MAX_ITCT_ENTRIES 2048 +#define HISI_SAS_MAX_ITCT_ENTRIES 1024 #define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES #define HISI_SAS_RESET_BIT 0 #define HISI_SAS_REJECT_CMD_BIT 1 @@ -342,7 +342,11 @@ struct hisi_sas_initial_fis { }; struct hisi_sas_breakpoint { - u8 data[128]; /*io128 byte*/ + u8 data[128]; +}; + +struct hisi_sas_sata_breakpoint { + struct hisi_sas_breakpoint tag[32]; }; struct hisi_sas_sge { diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 254af67..f49a131 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1613,7 +1613,7 @@ void hisi_sas_init_mem(struct hisi_hba *hisi_hba) s = max_command_entries * sizeof(struct hisi_sas_breakpoint); memset(hisi_hba->breakpoint, 0, s); - s = max_command_entries * sizeof(struct hisi_sas_breakpoint) * 2; + s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_sata_breakpoint); memset(hisi_hba->sata_breakpoint, 0, s); } EXPORT_SYMBOL_GPL(hisi_sas_init_mem); @@ -1706,7 +1706,7 @@ int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost) if (!hisi_hba->initial_fis) goto err_out; - s = max_command_entries * sizeof(struct hisi_sas_breakpoint) * 2; + s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_sata_breakpoint); hisi_hba->sata_breakpoint = dma_alloc_coherent(dev, s, &hisi_hba->sata_breakpoint_dma, GFP_KERNEL); if (!hisi_hba->sata_breakpoint) @@ -1771,7 +1771,7 @@ void hisi_sas_free(struct hisi_hba *hisi_hba) hisi_hba->initial_fis, hisi_hba->initial_fis_dma); - s = max_command_entries * sizeof(struct hisi_sas_breakpoint) * 2; + s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_sata_breakpoint); if (hisi_hba->sata_breakpoint) dma_free_coherent(dev, s, hisi_hba->sata_breakpoint, diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 38eeba9..ac499e9 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -172,7 +172,6 @@ #define DMA_RX_STATUS_BUSY_OFF 0 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) -#define MAX_ITCT_HW 4096 /* max the hw can support */ #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) #error Max ITCT exceeded @@ -377,6 +376,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) /* Global registers init */ hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, (u32)((1ULL << hisi_hba->queue_count) - 1)); + hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd); hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); From patchwork Tue Oct 24 15:51:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116962 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5914742qgn; Tue, 24 Oct 2017 08:07:17 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RaV9Jm7UF1yJkIjlILxI8cHKvn2yJSonE1KaAZR6C9sAyHMqWsvAPNqvLZ4Z4yoIRez4a0 X-Received: by 10.99.186.6 with SMTP id k6mr14969636pgf.195.1508857637074; Tue, 24 Oct 2017 08:07:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857637; cv=none; d=google.com; s=arc-20160816; b=cIyLQM31dSuBxUYjbLibWoVWRCc8i0gKAt006xxiJ4dVkZHDOlH2ht618Jmr5i1q2C ZIG4Pdcv38FNpgJqe4KYE7DTr3+nXZXsP/+D3XfYpv5Wv8Vnp1jb3KXtl+WE6PpA7ihT sEFETTbRbUjuByjRNY6FMEUO0gvxCsIPy3tIJWiLtZZv1K4Z8lEGQhjZI1J6SgRSbjSt NUVz5jry6kNskMLQx75tUAMhrmRAR6AsctSFTJpW2eCajquYUeO+ycTUEeAXOLiPpgL0 tqoJ6LZOlU15aKHCL8TYo1QdgCohrjDfUEa09cwjKedMXton+kAVj4bO7vUaN2kN0a9z jBsA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id m23si299677pgc.492.2017.10.24.08.07.16; Tue, 24 Oct 2017 08:07:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932403AbdJXPHQ (ORCPT + 1 other); Tue, 24 Oct 2017 11:07:16 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:50508 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751398AbdJXPF2 (ORCPT ); Tue, 24 Oct 2017 11:05:28 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E7585C3017A17; Tue, 24 Oct 2017 23:05:22 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:17 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 08/19] scsi: hisi_sas: fix the risk of freeing slot twice Date: Tue, 24 Oct 2017 23:51:38 +0800 Message-ID: <1508860309-212397-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan The function hisi_sas_slot_task_free() is used to free the slot and do tidy-up of LLDD resources. The LLDD generally should know the state of a slot and decide when to free it, and it should only be done once. For some scenarios, we really don't know the state, like when TMF timeout. In this case, we check task->lldd_task before calling hisi_sas_slot_task_free(). However, we may miss some scenarios when we should also check task->lldd_task, and it is not SMP safe to check task->lldd_task as we don't protect it within spin lock. This patch is to fix this risk of freeing slot twice, as follows: 1. Check task->lldd_task in the hisi_sas_slot_task_free(), and give up freeing of this time if task->lldd_task is NULL. 2. Set slot->buf to NULL after it is freed. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 2a209e1..6b4dabde 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -185,13 +185,16 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task, struct domain_device *device = task->dev; struct hisi_sas_device *sas_dev = device->lldd_dev; + if (!task->lldd_task) + return; + + task->lldd_task = NULL; + if (!sas_protocol_ata(task->task_proto)) if (slot->n_elem) dma_unmap_sg(dev, task->scatter, slot->n_elem, task->data_dir); - task->lldd_task = NULL; - if (sas_dev) atomic64_dec(&sas_dev->running_req); } @@ -199,8 +202,8 @@ void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task, if (slot->buf) dma_pool_free(hisi_hba->buffer_pool, slot->buf, slot->buf_dma); - list_del_init(&slot->entry); + slot->buf = NULL; slot->task = NULL; slot->port = NULL; hisi_sas_slot_index_free(hisi_hba, slot->idx); From patchwork Tue Oct 24 15:51:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116973 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5920138qgn; Tue, 24 Oct 2017 08:11:55 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QLLHkM9mM65r11QBJCfGocR1KLP7dkfyPrL2T4aJqB6bx1PiMXHInwFAy9DJ8SY/R1E45H X-Received: by 10.98.53.1 with SMTP id c1mr17119669pfa.248.1508857915863; Tue, 24 Oct 2017 08:11:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508857915; cv=none; d=google.com; s=arc-20160816; b=EuJa2hKykaWI29X2E6wa9EgoWOXNXmQhMzkM7pQ4ONmrCrST/xmCPNhZzKHFDqAzaC uJV3hFVKTvHmeEisP2MxzOXOOIaj7giESmwo0IABNfMV7+1XD+CmRmkiFfIuPZ+xXD78 WcnDPD5NhZCJkhhA2cCBMNkFwgRZZzsikgChRZZst+Hyeol68NL1SC+7iwDKNt/fMNP2 kPpYGTwRSMyBPE7irUAhdnl03QtXBS7WDbQ9Dt/SQAOtkH2VGkiYxMOd6AVbuO9RVPOj odWOczDfKUHFsn3fZ8HD6J551vFs8DP2aeSY8iX8KxDZNNYpoOL2pjHaoLadBrFEQ9Sm nYqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/6JH9BIhbW/AU1s0sp2KUcA+2qkNONTDxU79ygdTxqM=; b=ol+OMytXcc3lHGKeB3rjm098s1AffFfBsLMk4guwj/Xx8wPPRwLlkwo2XbQ5KIZJgV Q8myAh2ZpesVrvs/gZpt4viuLgGz/K3KBHAjea3NX0jywIXjJIjfnmQilfrFMZ0E+cJz jkBazfuJLHzttd6U69Ob+0/r5TJQUIWftQgGU4cvbTfUtxrs8JA4gA4zoBymm2cmsryt wCrUudsAHh+Ns+UD9ORZ74LSSoFpLp0aOHU68XtTzQHpD7N5Bxv9jwtOGuj2vKiTTsYS uS+Tb1uJAt4GUBOw4EzdHHdU4gYE0m81z7aKriRmdyJkE4+X/TWKSqw2fMfPoDTT0kRU S6GQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d2si306282pge.141.2017.10.24.08.11.55; Tue, 24 Oct 2017 08:11:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751750AbdJXPLx (ORCPT + 1 other); Tue, 24 Oct 2017 11:11:53 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9048 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751897AbdJXPLt (ORCPT ); Tue, 24 Oct 2017 11:11:49 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29927; Tue, 24 Oct 2017 23:05:31 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:21 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 18/19] scsi: hisi_sas: add v3 hw support for AXI fatal error Date: Tue, 24 Oct 2017 23:51:48 +0800 Message-ID: <1508860309-212397-19-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0205.59EF56BC.007D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 94da4e68e4a1545de81596c14d9ba973 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan Add support for processing AXI bus fatal errors. If AXI bus fatal error happen, do controller reset to recover. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 125 +++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 18cc3b4..f700482 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -53,6 +53,11 @@ #define HGC_IOMB_PROC1_STATUS 0x104 #define CFG_1US_TIMER_TRSH 0xcc #define CHNL_INT_STATUS 0x148 +#define HGC_AXI_FIFO_ERR_INFO 0x154 +#define AXI_ERR_INFO_OFF 0 +#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) +#define FIFO_ERR_INFO_OFF 8 +#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) #define INT_COAL_EN 0x19c #define OQ_INT_COAL_TIME 0x1a0 #define OQ_INT_COAL_CNT 0x1a4 @@ -1315,6 +1320,114 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) return IRQ_HANDLED; } +static const struct hisi_sas_hw_error axi_error[] = { + { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, + { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, + { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, + { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, + { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, + { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, + { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, + { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, + {}, +}; + +static const struct hisi_sas_hw_error fifo_error[] = { + { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, + { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, + { .msk = BIT(10), .msg = "GETDQE_FIFO" }, + { .msk = BIT(11), .msg = "CMDP_FIFO" }, + { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, + {}, +}; + +static const struct hisi_sas_hw_error fatal_axi_error[] = { + { + .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), + .msg = "write pointer and depth", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), + .msg = "iptt no match slot", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), + .msg = "read pointer and depth", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), + .reg = HGC_AXI_FIFO_ERR_INFO, + .sub = axi_error, + }, + { + .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), + .reg = HGC_AXI_FIFO_ERR_INFO, + .sub = fifo_error, + }, + { + .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), + .msg = "LM add/fetch list", + }, + { + .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), + .msg = "SAS_HGC_ABT fetch LM list", + }, +}; + +static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) +{ + u32 irq_value, irq_msk; + struct hisi_hba *hisi_hba = p; + struct device *dev = hisi_hba->dev; + int i; + + irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); + + irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + + for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { + const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; + + if (!(irq_value & error->irq_msk)) + continue; + + if (error->sub) { + const struct hisi_sas_hw_error *sub = error->sub; + u32 err_value = hisi_sas_read32(hisi_hba, error->reg); + + for (; sub->msk || sub->msg; sub++) { + if (!(err_value & sub->msk)) + continue; + + dev_warn(dev, "%s error (0x%x) found!\n", + sub->msg, irq_value); + queue_work(hisi_hba->wq, &hisi_hba->rst_work); + } + } else { + dev_warn(dev, "%s error (0x%x) found!\n", + error->msg, irq_value); + queue_work(hisi_hba->wq, &hisi_hba->rst_work); + } + } + + if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { + u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); + u32 dev_id = reg_val & ITCT_DEV_MSK; + struct hisi_sas_device *sas_dev = + &hisi_hba->devices[dev_id]; + + hisi_sas_write32(hisi_hba, ITCT_CLR, 0); + dev_dbg(dev, "clear ITCT ok\n"); + complete(sas_dev->completion); + } + + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); + hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); + + return IRQ_HANDLED; +} + static void slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, struct hisi_sas_slot *slot) @@ -1615,6 +1728,15 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) goto free_phy_irq; } + rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), + fatal_axi_int_v3_hw, 0, + DRV_NAME " fatal", hisi_hba); + if (rc) { + dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); + rc = -ENOENT; + goto free_chnl_interrupt; + } + /* Init tasklets for cq only */ for (i = 0; i < hisi_hba->queue_count; i++) { struct hisi_sas_cq *cq = &hisi_hba->cq[i]; @@ -1642,6 +1764,8 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) free_irq(pci_irq_vector(pdev, k+16), cq); } + free_irq(pci_irq_vector(pdev, 11), hisi_hba); +free_chnl_interrupt: free_irq(pci_irq_vector(pdev, 2), hisi_hba); free_phy_irq: free_irq(pci_irq_vector(pdev, 1), hisi_hba); @@ -1974,6 +2098,7 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) free_irq(pci_irq_vector(pdev, 1), hisi_hba); free_irq(pci_irq_vector(pdev, 2), hisi_hba); + free_irq(pci_irq_vector(pdev, 11), hisi_hba); for (i = 0; i < hisi_hba->queue_count; i++) { struct hisi_sas_cq *cq = &hisi_hba->cq[i]; From patchwork Tue Oct 24 15:51:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 116968 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp5917051qgn; Tue, 24 Oct 2017 08:09:17 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TqDJt3ypOhh/rw3z5PT2AuDPbjnzNfwhRslRzcjccb7enqhYU4p5l5T45OplwWHOG27TpY X-Received: by 10.99.105.72 with SMTP id e69mr14883180pgc.50.1508857757190; Tue, 24 Oct 2017 08:09:17 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id c30si294953pgn.815.2017.10.24.08.09.17; Tue, 24 Oct 2017 08:09:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932227AbdJXPJO (ORCPT + 1 other); Tue, 24 Oct 2017 11:09:14 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:9046 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbdJXPJK (ORCPT ); Tue, 24 Oct 2017 11:09:10 -0400 Received: from 172.30.72.58 (EHLO DGGEMS406-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJW29923; Tue, 24 Oct 2017 23:05:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.361.1; Tue, 24 Oct 2017 23:05:21 +0800 From: John Garry To: , CC: , , , , Xiaofei Tan , John Garry Subject: [PATCH 19/19] scsi: hisi_sas: add v3 hw port AXI error handling Date: Tue, 24 Oct 2017 23:51:49 +0800 Message-ID: <1508860309-212397-20-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508860309-212397-1-git-send-email-john.garry@huawei.com> References: <1508860309-212397-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0201.59EF56BB.00B5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 76f8f912e9bdb302233452ad1f43f9e4 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan Add support for servicing AXI errors handling. We do host a controller reset for such errors. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 42 ++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 5 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index f700482..d1bf5af 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -160,6 +160,10 @@ #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) +#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 +#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 +#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 +#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 #define CHL_INT2 (PORT_BASE + 0x1bc) #define CHL_INT0_MSK (PORT_BASE + 0x1c0) #define CHL_INT1_MSK (PORT_BASE + 0x1c4) @@ -417,7 +421,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); - hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); + hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff87ffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff); hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); @@ -1265,6 +1269,25 @@ static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) return res; } +static const struct hisi_sas_hw_error port_axi_error[] = { + { + .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), + .msg = "dma_tx_axi_wr_err", + }, + { + .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), + .msg = "dma_tx_axi_rd_err", + }, + { + .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), + .msg = "dma_rx_axi_wr_err", + }, + { + .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), + .msg = "dma_rx_axi_rd_err", + }, +}; + static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) { struct hisi_hba *hisi_hba = p; @@ -1290,10 +1313,19 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) if ((irq_msk & (4 << (phy_no * 4))) && irq_value1) { - if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | - CHL_INT1_DMAC_TX_ECC_ERR_MSK)) - panic("%s: DMAC RX/TX ecc bad error! (0x%x)", - dev_name(dev), irq_value1); + int i; + + for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { + const struct hisi_sas_hw_error *error = + &port_axi_error[i]; + + if (!(irq_value1 & error->irq_msk)) + continue; + + dev_warn(dev, "%s error (phy%d 0x%x) found!\n", + error->msg, phy_no, irq_value1); + queue_work(hisi_hba->wq, &hisi_hba->rst_work); + } hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value1);