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[209.132.180.131]) by mx.google.com with ESMTPS id r4si22472474pli.158.2017.02.21.08.55.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Feb 2017 08:55:01 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-448906-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-448906-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-448906-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=Q9/U46fp14/CLYcInIHGTfa6tf0C6tqcZ+w284FZBUdOHXv2qdyJn nmrxi87RNsEZQOlz9MOEV1y9BeDWeEbpM+NhoSW8B60m8MI/cE2yYxVFrpd3hVbZ g5b6c8SB2m6RBmeAFTSc/bb5ki7xdBEegp9l3ra4PQoKIwxrOk7yFU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=KKbA4fiNLcPJ0x9EdQUWjy+UDUk=; b=vsytMShHv9HS+0laaow9 81obC6nEQ6LlxSbmvGpfRVTwdkzV0ScmhjMDGo5khIWUGEwdCzgCYboewq917eo6 69oUnyrjz25F9RsXzpSDhLknL1JRKEQL5Ggll/q37yrrCOMfGZsrZZ50YNlQ8GSA laZ0aQd6nyGjbtUaCd5Dczo= Received: (qmail 115343 invoked by alias); 21 Feb 2017 16:54:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115255 invoked by uid 89); 21 Feb 2017 16:54:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:charles, bus, HX-Envelope-From:sk:charles, Charles X-HELO: mail-wm0-f44.google.com Received: from mail-wm0-f44.google.com (HELO mail-wm0-f44.google.com) (74.125.82.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Feb 2017 16:54:33 +0000 Received: by mail-wm0-f44.google.com with SMTP id 196so30305743wmm.1 for ; Tue, 21 Feb 2017 08:54:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=F0fUfOnGMcsCPwsXPLz8OJzhfR6XDNL7EycVjioQgR0=; b=ZDGVIcg87Uk4C5Ede5DeygPyAPH+LCHIXCb84nk7f99qzBBPwIEwbnjDdGhzgXAR9N 73mpR7zNFvxOsWb4yRUloO9v7HKo4nK0ezYBLw3oMEGEXRSHFXH3H7RGPBZMnFTNbI3M 0yqqAwrNfwk7NyQLwBx05xYGw6f8SQixDRSwXQ0KEm+op/ah8vB89xAOwAhpEJ61loQ1 y5jmDEPmgtMPDkeef8hFxGz/5iGRowHivhz7pshmwC1Oajs3k7x5qt8nhtzuRGWSaBIE 5vF5c4YCH0l+yAgnkyQ3T83ENn2YAnIXi6fy9XS1Tf+ami4RT7Zne6kQECPETPreMKHi yqIw== X-Gm-Message-State: AMke39lGDrwANSDe+52EcrPJLmZ2kL9JQkddY0GYrmBkN2bbxxYPV+5nfYCFdLjfl1/T5WMW X-Received: by 10.28.165.196 with SMTP id o187mr25262340wme.6.1487696071840; Tue, 21 Feb 2017 08:54:31 -0800 (PST) Received: from localhost.localdomain ([85.255.232.30]) by smtp.gmail.com with ESMTPSA id i73sm18293060wmd.11.2017.02.21.08.54.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Feb 2017 08:54:31 -0800 (PST) From: charles.baylis@linaro.org To: Ramana.Radhakrishnan@arm.com, kyrylo.tkachov@arm.com Cc: rearnsha@arm.com, gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] [ARM] Refactor costs calculation for MEM. Date: Tue, 21 Feb 2017 16:54:23 +0000 Message-Id: <1487696064-3233-2-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1487696064-3233-1-git-send-email-charles.baylis@linaro.org> References: <1487696064-3233-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis This patch moves the calculation of costs for MEM into a separate function, and reforms the calculation into two parts. Firstly any additional cost of the addressing mode is calculated, and then the cost of the memory access itself is added. In this patch, the calculation of the cost of the addressing mode is left as a placeholder, to be added in a subsequent patch. gcc/ChangeLog: Charles Baylis * config/arm/arm.c (arm_mem_costs): New function. (arm_rtx_costs_internal): Use arm_mem_costs. Change-Id: I99e93406ea39ee31f71c7bf428ad3e127b7a618e --- gcc/config/arm/arm.c | 66 +++++++++++++++++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 24 deletions(-) -- 2.7.4 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6cae178..7f002f1 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9072,6 +9072,47 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost) } \ while (0); +/* Helper function for arm_rtx_costs_internal. Calculates the cost of a MEM, + considering the costs of the addressing mode and memory access + separately. */ +static bool +arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost, + int *cost, bool speed_p) +{ + machine_mode mode = GET_MODE (x); + if (flag_pic + && GET_CODE (XEXP (x, 0)) == PLUS + && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) + /* This will be split into two instructions. Add the cost of the + additional instruction here. The cost of the memory access is computed + below. See arm.md:calculate_pic_address. */ + *cost = COSTS_N_INSNS (1); + else + *cost = 0; + + /* Calculate cost of the addressing mode. */ + if (speed_p) + { + /* TODO: Add table-driven costs for addressing modes. */ + } + + /* cost of memory access */ + if (speed_p) + { + /* data transfer is transfer size divided by bus width. */ + int bus_width = arm_arch7 ? 8 : 4; + *cost += COSTS_N_INSNS((GET_MODE_SIZE (mode) + bus_width - 1) / bus_width); + *cost += extra_cost->ldst.load; + } else { + *cost += COSTS_N_INSNS (1); + } + + return true; +} +/* Convert fron bytes to ints. */ +#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + + /* RTX costs. Make an estimate of the cost of executing the operation X, which is contained with an operation with code OUTER_CODE. SPEED_P indicates whether the cost desired is the performance cost, @@ -9152,30 +9193,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; case MEM: - /* A memory access costs 1 insn if the mode is small, or the address is - a single register, otherwise it costs one insn per word. */ - if (REG_P (XEXP (x, 0))) - *cost = COSTS_N_INSNS (1); - else if (flag_pic - && GET_CODE (XEXP (x, 0)) == PLUS - && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) - /* This will be split into two instructions. - See arm.md:calculate_pic_address. */ - *cost = COSTS_N_INSNS (2); - else - *cost = COSTS_N_INSNS (ARM_NUM_REGS (mode)); - - /* For speed optimizations, add the costs of the address and - accessing memory. */ - if (speed_p) -#ifdef NOT_YET - *cost += (extra_cost->ldst.load - + arm_address_cost (XEXP (x, 0), mode, - ADDR_SPACE_GENERIC, speed_p)); -#else - *cost += extra_cost->ldst.load; -#endif - return true; + return arm_mem_costs (x, extra_cost, cost, speed_p); case PARALLEL: { From patchwork Tue Feb 21 16:54:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 94280 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp531078qgi; Tue, 21 Feb 2017 08:55:18 -0800 (PST) X-Received: by 10.98.200.136 with SMTP id i8mr7345686pfk.120.1487696118776; Tue, 21 Feb 2017 08:55:18 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id h3si2648894pld.13.2017.02.21.08.55.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Feb 2017 08:55:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-448907-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-448907-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-448907-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=ptOwtBF/s20zCcnguyw+u8ksDrcaucXFWoZ8M0rmc0FmG553+x1B7 UsVFZlJxuXlSN/GUS7SVAQDq1shH5zTLq4Ra5KTZRPspnCDEKWi7Vtco8NB1LyDQ 3dBT1xRD+kz9f5CSsj5VQ+oPnpSykXg6ccDnZYckSDdKIOGo+ifojQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=2YBF8/f/5CRh5c99AnzELPOeP7g=; b=PVpjeiegflXbvkxbsXFS v+6jmJ+iyV3Nt119/4IwHqc4IfyqLQFQx6lN+pHdIzRZ5E58Ij4jPyugWASz9/1E cxL0MKNwbqPdhH3TZdlwOGlP3+UoVA3Q0+sF1eOidv/CETX/v7b2PdJ1D5j7OBU2 Z8IoD/Cj4aS7Zvg/zpiVDXE= Received: (qmail 115704 invoked by alias); 21 Feb 2017 16:54:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 115620 invoked by uid 89); 21 Feb 2017 16:54:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=6377, 1376 X-HELO: mail-wr0-f172.google.com Received: from mail-wr0-f172.google.com (HELO mail-wr0-f172.google.com) (209.85.128.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Feb 2017 16:54:35 +0000 Received: by mail-wr0-f172.google.com with SMTP id 97so7306490wrb.0 for ; Tue, 21 Feb 2017 08:54:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w6OCzhHlRJIxS0RPAEx9OaTeMFZ29uxd5ptSrrnWRMI=; b=JsjGbYxe6gW2OkA86af8TOCimlyoUSutRLX4NO1C9lET2BA8DuGvjUvVpBNKXfL9fn q9fhAPN8XJwAeTKTG1wNrbe5mH8ksARhnXGFSc8HlDExbQanhOQjVh9UBYgHoDgHOCea rWvGqiwPHsjHrnhwpfrrmDLFrf/voU3hFD5G96wTiG5K3n6R6FKcA93E1uTp7pyxth/s LAtB96Qtz6AQkRb2WYzxAWT4z2s2ThZIOu/Jrh/RSZV72yLYTh8aTHgymwSgu1OdMn+s dgmTwaqqHtpfVTXdB6GyYd01BKBzEgZ9i4n2iag9Q9o27EX5yfM47o4cTdlf4zIBfUIA 1nYQ== X-Gm-Message-State: AMke39ki7PfqQiKXtzXIJKyuDsfDOLwF03ctHxZNzWrIneLhDKRtwJFmGtFC/yXU4j+fpyIQ X-Received: by 10.223.149.39 with SMTP id 36mr20709286wrs.125.1487696073264; Tue, 21 Feb 2017 08:54:33 -0800 (PST) Received: from localhost.localdomain ([85.255.232.30]) by smtp.gmail.com with ESMTPSA id i73sm18293060wmd.11.2017.02.21.08.54.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Feb 2017 08:54:32 -0800 (PST) From: charles.baylis@linaro.org To: Ramana.Radhakrishnan@arm.com, kyrylo.tkachov@arm.com Cc: rearnsha@arm.com, gcc-patches@gcc.gnu.org Subject: [PATCH 2/2] [ARM] Add table of costs for AAarch32 addressing modes. Date: Tue, 21 Feb 2017 16:54:24 +0000 Message-Id: <1487696064-3233-3-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1487696064-3233-1-git-send-email-charles.baylis@linaro.org> References: <1487696064-3233-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes From: Charles Baylis This patch adds support for modelling the varying costs of different addressing modes. The generic cost table treats all addressing modes as having equal cost. The cost table for Cortex-A57 is derived from http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf and treats addressing modes with write-back as having a cost equal to one additional instruction. gcc/ChangeLog: Charles Baylis * config/arm/aarch-common-protos.h (enum arm_addr_mode_op): New. (struct addr_mode_cost_table): New. (struct cpu_cost_table): Add pointer to an addr_mode_cost_table. * config/arm/aarch-cost-tables.h: (generic_addr_mode_costs): New. (generic_extra_costs) Initialise aarch32_addr_mode. (cortexa53_extra_costs) Likewise. (addr_mode_costs_cortexa57) New. (cortexa57_extra_costs) Initialise aarch32_addr_mode. (exynosm1_extra_costs) Likewise. (xgene1_extra_costs) Likewise. (qdf24xx_extra_costs) Likewise. * config/arm/arm.c (cortexa9_extra_costs) Initialise aarch32_addr_mode. (cortexa9_extra_costs) Likewise. (cortexa8_extra_costs) Likewise. (cortexa5_extra_costs) Likewise. (cortexa7_extra_costs) Likewise. (cortexa12_extra_costs) Likewise. (cortexv7m_extra_costs) Likewise. (arm_mem_costs): Use table lookup to calculate cost of addressing mode. Change-Id: If71bd7c4f4bb876c5ed82dc28791130efb8bf89e --- gcc/config/arm/aarch-common-protos.h | 16 +++++++++++ gcc/config/arm/aarch-cost-tables.h | 54 ++++++++++++++++++++++++++++++---- gcc/config/arm/arm.c | 56 ++++++++++++++++++++++++++++++------ 3 files changed, 113 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 7c2bb4c..f6fcc94 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -130,6 +130,21 @@ struct vector_cost_table const int alu; }; +enum arm_addr_mode_op +{ + AMO_DEFAULT, + AMO_NO_WB, + AMO_WB, + AMO_MAX /* for array size */ +}; + +struct addr_mode_cost_table +{ + const int integer[AMO_MAX]; + const int fp[AMO_MAX]; + const int vector[AMO_MAX]; +}; + struct cpu_cost_table { const struct alu_cost_table alu; @@ -137,6 +152,7 @@ struct cpu_cost_table const struct mem_cost_table ldst; const struct fp_cost_table fp[2]; /* SFmode and DFmode. */ const struct vector_cost_table vect; + const struct addr_mode_cost_table *aarch32_addr_mode; }; diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 68f84b0..e3d257f 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -22,6 +22,16 @@ #ifndef GCC_AARCH_COST_TABLES_H #define GCC_AARCH_COST_TABLES_H +const struct addr_mode_cost_table generic_addr_mode_costs = +{ + /* int */ + { 0, 0, 0 }, + /* float */ + { 0, 0, 0 }, + /* vector */ + { 0, 0, 0 } +}; + const struct cpu_cost_table generic_extra_costs = { /* ALU */ @@ -122,7 +132,9 @@ const struct cpu_cost_table generic_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table cortexa53_extra_costs = @@ -225,6 +237,30 @@ const struct cpu_cost_table cortexa53_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Addressing mode */ + &generic_addr_mode_costs +}; + +const struct addr_mode_cost_table addr_mode_costs_cortexa57 = +{ + /* int */ + { + 0, + 0, + COSTS_N_INSNS (1), + }, + /* float */ + { + 0, + 0, + COSTS_N_INSNS (1), + }, + /* vector */ + { + 0, + 0, + COSTS_N_INSNS (1), } }; @@ -328,7 +364,9 @@ const struct cpu_cost_table cortexa57_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &addr_mode_costs_cortexa57 }; const struct cpu_cost_table exynosm1_extra_costs = @@ -431,7 +469,9 @@ const struct cpu_cost_table exynosm1_extra_costs = /* Vector */ { COSTS_N_INSNS (0) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table xgene1_extra_costs = @@ -534,7 +574,9 @@ const struct cpu_cost_table xgene1_extra_costs = /* Vector */ { COSTS_N_INSNS (2) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table qdf24xx_extra_costs = @@ -637,7 +679,9 @@ const struct cpu_cost_table qdf24xx_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; #endif /* GCC_AARCH_COST_TABLES_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7f002f1..fe4cd73 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1099,7 +1099,9 @@ const struct cpu_cost_table cortexa9_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table cortexa8_extra_costs = @@ -1202,7 +1204,9 @@ const struct cpu_cost_table cortexa8_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table cortexa5_extra_costs = @@ -1306,7 +1310,9 @@ const struct cpu_cost_table cortexa5_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; @@ -1411,7 +1417,9 @@ const struct cpu_cost_table cortexa7_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table cortexa12_extra_costs = @@ -1514,7 +1522,9 @@ const struct cpu_cost_table cortexa12_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table cortexa15_extra_costs = @@ -1617,7 +1627,9 @@ const struct cpu_cost_table cortexa15_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct cpu_cost_table v7m_extra_costs = @@ -1720,7 +1732,9 @@ const struct cpu_cost_table v7m_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ - } + }, + /* Addressing mode */ + &generic_addr_mode_costs }; const struct tune_params arm_slowmul_tune = @@ -9093,7 +9107,33 @@ arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost, /* Calculate cost of the addressing mode. */ if (speed_p) { - /* TODO: Add table-driven costs for addressing modes. */ + arm_addr_mode_op op_type; + switch (GET_CODE(XEXP (x, 0))) + { + case REG: + default: + op_type = AMO_DEFAULT; + break; + case PLUS: + case MINUS: + op_type = AMO_NO_WB; + break; + case PRE_INC: + case PRE_DEC: + case POST_INC: + case POST_DEC: + case PRE_MODIFY: + case POST_MODIFY: + op_type = AMO_WB; + break; + } + if (VECTOR_MODE_P (mode)) { + *cost += extra_cost->aarch32_addr_mode->vector[op_type]; + } else if (FLOAT_MODE_P (mode)) { + *cost += extra_cost->aarch32_addr_mode->fp[op_type]; + } else { + *cost += extra_cost->aarch32_addr_mode->integer[op_type]; + } } /* cost of memory access */